diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
index f3b89ec4..2367ca06 100644
--- a/hw/cheshire_pkg.sv
+++ b/hw/cheshire_pkg.sv
@@ -157,8 +157,8 @@ package cheshire_pkg;
     bit     LlcOutConnect;
     doub_bt LlcOutRegionStart;
     doub_bt LlcOutRegionEnd;
-    dw_bt   LlcUserAmoMsb;
-    dw_bt   LlcUserAmoLsb;
+    dw_bt   LlcUserMsb;
+    dw_bt   LlcUserLsb;
     // Parameters for VGA
     byte_bt VgaRedWidth;
     byte_bt VgaGreenWidth;
@@ -273,6 +273,7 @@ package cheshire_pkg;
   localparam doub_bt AmLlc    = 'h0300_1000;
   localparam doub_bt AmSlink  = 'h0300_6000;
   localparam doub_bt AmBusErr = 'h0300_8000;
+  localparam doub_bt AmTagger = 'h0300_A000;
   localparam doub_bt AmSpm    = 'h1000_0000;  // Cached region at bottom, uncached on top
   localparam doub_bt AmClic   = 'h0800_0000;
 
@@ -389,7 +390,7 @@ package cheshire_pkg;
     aw_bt irq_router;
     aw_bt [2**MaxCoresWidth-1:0] bus_err;
     aw_bt [2**MaxCoresWidth-1:0] clic;
-    aw_bt tagger;
+    aw_bt [2**MaxCoresWidth-1:0] tagger;
     aw_bt ext_base;
     aw_bt num_out;
     aw_bt num_rules;
@@ -410,7 +411,6 @@ package cheshire_pkg;
     if (cfg.Gpio)         begin i++; ret.gpio       = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
     if (cfg.SerialLink)   begin i++; ret.slink      = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
     if (cfg.Vga)          begin i++; ret.vga        = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
-    if (cfg.LlcCachePartition)   begin i++; ret.tagger   = i; r++; ret.map[r] = '{i, 'h0300_a000, 'h0300_b000}; end
     if (cfg.IrqRouter)    begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
     if (cfg.AxiRt)        begin i++; ret.axirt      = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end
     if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
@@ -419,6 +419,9 @@ package cheshire_pkg;
     if (cfg.BusErr) for (int j = 0; j < 2 + cfg.NumCores; j++) begin
       i++; ret.bus_err[j] = i; r++; ret.map[r] = '{i, AmBusErr + j*'h40,  AmBusErr + (j+1)*'h40};
     end
+    if (cfg.LlcCachePartition) for (int j = 0; j < cfg.NumCores; j++) begin
+      i++; ret.tagger[j]    = i; r++; ret.map[r] = '{i, AmTagger + j*'h40, AmTagger + (j+1)*'h40};
+    end
     i++; r++;
     ret.ext_base  = i;
     ret.num_out   = i + cfg.RegExtNumSlv;
@@ -575,8 +578,8 @@ package cheshire_pkg;
     LlcOutConnect     : 1,
     LlcOutRegionStart : 'h8000_0000,
     LlcOutRegionEnd   : 'h1_0000_0000,
-    LlcUserAmoMsb     : 6,
-    LlcUserAmoLsb     : 2,
+    LlcUserMsb        : 0,
+    LlcUserLsb        : 0,
     // LLC Partitioning
     LlcCachePartition : 0,
     LlcMaxPartition   : 0,
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index 671f2a77..8efb68ef 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -514,8 +514,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       .AxiAddrWidth     ( Cfg.AddrWidth          ),
       .AxiDataWidth     ( Cfg.AxiDataWidth       ),
       .AxiUserWidth     ( Cfg.AxiUserWidth       ),
-      .AxiUserIdMsb     ( Cfg.LlcUserAmoMsb      ),
-      .AxiUserIdLsb     ( Cfg.LlcUserAmoLsb      ),
+      .AxiUserIdMsb     ( Cfg.LlcUserMsb         ),
+      .AxiUserIdLsb     ( Cfg.LlcUserLsb         ),
       .slv_req_t        ( axi_slv_req_t          ),
       .slv_resp_t       ( axi_slv_rsp_t          ),
       .mst_req_t        ( axi_ext_llc_req_t      ),
@@ -756,13 +756,12 @@ module cheshire_soc import cheshire_pkg::*; #(
     );
 
     if (Cfg.LlcCachePartition) begin : gen_tagger
-      if (i == 0) begin : gen_wr_tagger
         tagger #(
           .DATA_WIDTH       ( Cfg.AxiDataWidth    ),
           .ADDR_WIDTH       ( Cfg.AddrWidth       ),
           .MAXPARTITION     ( Cfg.LlcMaxPartition ),
-          .AXI_USER_ID_MSB  ( Cfg.LlcUserAmoMsb   ),
-          .AXI_USER_ID_LSB  ( Cfg.LlcUserAmoLsb   ),
+          .AXI_USER_ID_MSB  ( Cfg.LlcUserMsb      ),
+          .AXI_USER_ID_LSB  ( Cfg.LlcUserLsb      ),
           .TAGGER_GRAN      ( 3                   ),
           .axi_req_t        ( axi_mst_req_t       ),
           .axi_rsp_t        ( axi_mst_rsp_t       ),
@@ -771,36 +770,13 @@ module cheshire_soc import cheshire_pkg::*; #(
         ) i_tagger (
           .clk_i,
           .rst_ni,
-          .slv_req_i        ( tagger_req[i]               ),
-          .slv_rsp_o        ( tagger_rsp[i]               ),
-          .mst_req_o        ( axi_in_req[AxiIn.cores[i]]  ),
-          .mst_rsp_i        ( axi_in_rsp[AxiIn.cores[i]]  ),
-          .cfg_req_i        ( reg_out_req[RegOut.tagger]  ),
-          .cfg_rsp_o        ( reg_out_rsp[RegOut.tagger]  )
+          .slv_req_i        ( tagger_req[i]              ),
+          .slv_rsp_o        ( tagger_rsp[i]              ),
+          .mst_req_o        ( axi_in_req[AxiIn.cores[i]] ),
+          .mst_rsp_i        ( axi_in_rsp[AxiIn.cores[i]] ),
+          .cfg_req_i        ( reg_out_req[RegOut.tagger[i]] ),
+          .cfg_rsp_o        ( reg_out_rsp[RegOut.tagger[i]] )
         );
-      end else begin : gen_r_tagger
-        tagger #(
-          .DATA_WIDTH       ( Cfg.AxiDataWidth    ),
-          .ADDR_WIDTH       ( Cfg.AddrWidth       ),
-          .MAXPARTITION     ( Cfg.LlcMaxPartition ),
-          .AXI_USER_ID_MSB  ( Cfg.LlcUserAmoMsb   ),
-          .AXI_USER_ID_LSB  ( Cfg.LlcUserAmoLsb   ),
-          .TAGGER_GRAN      ( 3                   ),
-          .axi_req_t        ( axi_mst_req_t       ),
-          .axi_rsp_t        ( axi_mst_rsp_t       ),
-          .reg_req_t        ( reg_req_t           ),
-          .reg_rsp_t        ( reg_rsp_t           )
-        ) i_tagger (
-          .clk_i,
-          .rst_ni,
-          .slv_req_i        ( tagger_req[i]               ),
-          .slv_rsp_o        ( tagger_rsp[i]               ),
-          .mst_req_o        ( axi_in_req[AxiIn.cores[i]]  ),
-          .mst_rsp_i        ( axi_in_rsp[AxiIn.cores[i]]  ),
-          .cfg_req_i        ( reg_out_req[RegOut.tagger]  ),
-          .cfg_rsp_o        (                             )
-        );
-      end
     end else begin : gen_no_tagger
       assign axi_in_req[AxiIn.cores[i]] = tagger_req[i];
       assign tagger_rsp[i] = axi_in_rsp[AxiIn.cores[i]];