diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
index 4ac92ddf..f6d3b031 100644
--- a/target/xilinx/src/cheshire_top_xilinx.sv
+++ b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -69,9 +69,9 @@ module cheshire_top_xilinx
   // Configure cheshire for FPGA mapping
   localparam cheshire_cfg_t FPGACfg = '{
     // CVA6 parameters
-    Cva6RASDepth      : ariane_pkg::ArianeDefaultConfig.RASDepth,
-    Cva6BTBEntries    : ariane_pkg::ArianeDefaultConfig.BTBEntries,
-    Cva6BHTEntries    : ariane_pkg::ArianeDefaultConfig.BHTEntries,
+    Cva6RASDepth      : 2,
+    Cva6BTBEntries    : 32,
+    Cva6BHTEntries    : 128,
     Cva6NrPMPEntries  : 0,
     Cva6ExtCieLength  : 'h2000_0000,
     Cva6ExtCieOnTop   : 0,