diff --git a/Bender.yml b/Bender.yml
index 2ffb1f36..eda16410 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -56,6 +56,7 @@ sources:
       - target/sim/src/tb_cheshire_pkg.sv
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
+      - hw/newusb_tb/new_usb_tb.sv
 
   - target: all(fpga, xilinx)
     files:
diff --git a/target/sim/vsim/start.newusb.tcl b/target/sim/vsim/start.newusb.tcl
new file mode 100755
index 00000000..5699de54
--- /dev/null
+++ b/target/sim/vsim/start.newusb.tcl
@@ -0,0 +1,13 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Fabian Hauser <fhauser@student.ethz.ch>
+
+set TESTBENCH new_usb_tb
+
+# tclint-disable-next-line command-args
+eval "vsim -c ${TESTBENCH} -t 1ps"
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1