diff --git a/Bender.lock b/Bender.lock
index 7ff732c6..dc6a35ea 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -145,7 +145,7 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp_c910:
-    revision: fef1b0ed97bf1d180c38ef52474bf05e6cba99c8
+    revision: 546ceba4e4b445e29154b078a54425e40a8b877d
     version: null
     source:
       Git: git@iis-git.ee.ethz.ch:nwistoff/pulp_c910.git
diff --git a/Bender.yml b/Bender.yml
index c8abd618..7a7eb246 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -33,7 +33,7 @@ dependencies:
   # soc910:                   { git: "git@iis-git.ee.ethz.ch:nwistoff/soc910.git",                  rev: 7c218d05   }
   # register_interface:       { path: vendor/pulp_register_interface                                                  }
   # soc910:                   { path: soc910/hw/system                                                              }
-  pulp_c910:                { git: "git@iis-git.ee.ethz.ch:nwistoff/pulp_c910.git",               rev: fef1b0ed   }
+  pulp_c910:                { git: "git@iis-git.ee.ethz.ch:nwistoff/pulp_c910.git",               rev: 546ceba4   }
 
 export_include_dirs:
   - hw/include
diff --git a/cheshire.mk b/cheshire.mk
index 16ca3db8..3b78b613 100644
--- a/cheshire.mk
+++ b/cheshire.mk
@@ -221,8 +221,10 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 # Emulation #
 #############
 
-CHS_XIL_DIR := $(CHS_ROOT)/target/xilinx_211223
+# CHS_XIL_DIR := $(CHS_ROOT)/target/xilinx
+# CHS_XIL_DIR := $(CHS_ROOT)/target/xilinx_211223
 # CHS_XIL_DIR := $(CHS_ROOT)/target/xilinx_060124
+CHS_XIL_DIR := $(CHS_ROOT)/target/xilinx_090124
 include $(CHS_XIL_DIR)/xilinx.mk
 include $(CHS_XIL_DIR)/sim/sim.mk
 CHS_XILINX_ALL += $(CHS_XIL_DIR)/scripts/add_sources.tcl
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index 11e6dc0d..9b9783bf 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -656,8 +656,8 @@ module cheshire_soc
     end else begin : gen_c910_core
       (* mark_debug = "true" *) axi_c910_req_t c910_out_req_s1;
       (* mark_debug = "true" *) axi_c910_rsp_t c910_out_rsp_s1;
-      (* mark_debug = "true" *) axi_c910_req_t c910_out_req_s2;
-      (* mark_debug = "true" *) axi_c910_rsp_t c910_out_rsp_s2;
+      axi_c910_req_t c910_out_req_s2;
+      axi_c910_rsp_t c910_out_rsp_s2;
 
       c910_axi_wrap #(
         .AxiSetModifiable ( 1'b1              ),