From 75d4bfdbd7dc6710aec53e1f6a6d4513619992e5 Mon Sep 17 00:00:00 2001
From: Alessandro Ottaviano <aottaviano@iis.ee.ethz.ch>
Date: Wed, 22 Nov 2023 17:35:02 +0100
Subject: [PATCH] hw: Fix Regbus address range in AXI crossbar (#86)

Co-authored-by: bluew <bluewww@users.noreply.github.com>
---
 hw/cheshire_pkg.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
index 5adf1ea4..bf052dba 100644
--- a/hw/cheshire_pkg.sv
+++ b/hw/cheshire_pkg.sv
@@ -332,7 +332,7 @@ package cheshire_pkg;
     axi_out_t ret = '{dbg: 0, reg_demux: 1, default: '0};
     int unsigned i = 1, r = 1;
     ret.map[0] = '{0, AmDbg,   AmDbg + 'h40000};
-    ret.map[1] = '{1, 'h0200_0000, 'h0800_0000};
+    ret.map[1] = '{1, 'h0200_0000, 'h0C00_0000};
     // Whether we have an LLC or a bypass, the output port is has its
     // own Xbar output with the specified region iff it is connected.
     if (cfg.LlcOutConnect) begin i++; r++; ret.llc = i;