From 634e656951604af79f00b8ab84e1f46a9001e32a Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Thu, 14 Sep 2023 17:33:35 +0200 Subject: [PATCH] PG: initial version copied from Ale --- Bender.yml | 2 + hw/cheshire_ext_playground.sv | 277 +++++++++++++++++++++++++ hw/cheshire_ext_playground_pkg.sv | 91 ++++++++ hw/cheshire_soc.sv | 6 +- sw/tests/2d_dma.c | 23 ++ target/sim/src/fixture_cheshire_soc.sv | 43 +++- target/sim/vsim/run_pg.tcl | 9 + 7 files changed, 442 insertions(+), 9 deletions(-) create mode 100644 hw/cheshire_ext_playground.sv create mode 100644 hw/cheshire_ext_playground_pkg.sv create mode 100755 sw/tests/2d_dma.c create mode 100644 target/sim/vsim/run_pg.tcl diff --git a/Bender.yml b/Bender.yml index 98f6b0fbe..106b90fc9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -38,6 +38,8 @@ sources: - hw/bootrom/cheshire_bootrom.sv - hw/regs/cheshire_reg_pkg.sv - hw/regs/cheshire_reg_top.sv + - hw/cheshire_ext_playground_pkg.sv + - hw/cheshire_ext_playground.sv - hw/cheshire_pkg.sv - hw/cheshire_soc.sv diff --git a/hw/cheshire_ext_playground.sv b/hw/cheshire_ext_playground.sv new file mode 100644 index 000000000..ab4758d01 --- /dev/null +++ b/hw/cheshire_ext_playground.sv @@ -0,0 +1,277 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Alessandro Ottaviano + +`include "cheshire/typedef.svh" +`include "axi/typedef.svh" + +module cheshire_ext_playground + import cheshire_pkg::*; + import cheshire_ext_playground_pkg::*; +#( + // Cheshire config + parameter cheshire_cfg_t Cfg = '0, + // Interconnect types (must agree with Cheshire config) + parameter type axi_ext_mst_req_t = logic, + parameter type axi_ext_mst_rsp_t = logic, + parameter type axi_ext_slv_req_t = logic, + parameter type axi_ext_slv_rsp_t = logic, + parameter type reg_ext_req_t = logic, + parameter type reg_ext_rsp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic test_mode_i, + input logic rtc_i, + // External AXI crossbar ports + output axi_ext_mst_req_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_req_o, + input axi_ext_mst_rsp_t [iomsb(Cfg.AxiExtNumMst):0] axi_ext_mst_rsp_i, + input axi_ext_slv_req_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_req_i, + output axi_ext_slv_rsp_t [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_rsp_o, + // External reg demux slaves + input reg_ext_req_t [iomsb(Cfg.RegExtNumSlv):0] reg_ext_slv_req_i, + output reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv):0] reg_ext_slv_rsp_o +); + + // General parameters and defines + `CHESHIRE_TYPEDEF_ALL(chs_playgnd_, Cfg) + + // Generate indices and get maps for all ports + localparam axi_in_t AxiIn = gen_axi_in(Cfg); + localparam axi_out_t AxiOut = gen_axi_out(Cfg); + + localparam int unsigned ChsPlaygndAxiSlvIdWidth = Cfg.AxiMstIdWidth + $clog2(AxiIn.num_in); + + // tied-off + assign axi_ext_slv_rsp_o[PeriphsSlvIdx] = '0; + + + /////////////////////////////////////// + // DSAs' traffic generators (dma(s)) // + /////////////////////////////////////// + + chs_playgnd_axi_slv_req_t [ChsPlaygndNumDsaDma-1:0] dsa_dma_amo_req, dsa_dma_cut_req; + chs_playgnd_axi_slv_rsp_t [ChsPlaygndNumDsaDma-1:0] dsa_dma_amo_rsp, dsa_dma_cut_rsp; + + if (ChsPlaygndNumSlvDevices != Cfg.AxiExtNumSlv) + $fatal(1, "the number of slave devices must be equal to the number of slave AXI ports"); + + if (ChsPlaygndNumMstDevices != Cfg.AxiExtNumMst) + $fatal(1, "the number of master devices must be equal to the number of master AXI ports"); + + for (genvar i=0; i + +`include "cheshire/typedef.svh" + +package cheshire_ext_playground_pkg; + + import cheshire_pkg::*; + + // Number of DSA DMAs + localparam int unsigned ChsPlaygndNumDsaDma = 1; + + // Number of slave peripherals + localparam int unsigned ChsPlaygndNumPeriphs = 1; + + // Number of slave mems + localparam int unsigned ChsPlaygndNumAxiMems = 3; + + // Total number of master and slaves + localparam int unsigned ChsPlaygndNumSlvDevices = ChsPlaygndNumDsaDma + ChsPlaygndNumPeriphs + ChsPlaygndNumAxiMems; + localparam int unsigned ChsPlaygndNumMstDevices = ChsPlaygndNumDsaDma; + + // Narrow AXI widths + localparam int unsigned ChsPlaygndAxiNarrowAddrWidth = 32; + localparam int unsigned ChsPlaygndAxiNarrowDataWidth = 32; + localparam int unsigned ChsPlaygndAxiNarrowStrobe = ChsPlaygndAxiNarrowDataWidth/8; + + // Narrow AXI types + typedef logic [ ChsPlaygndAxiNarrowAddrWidth-1:0] chs_playgnd_nar_addrw_t; + typedef logic [ ChsPlaygndAxiNarrowDataWidth-1:0] chs_playgnd_nar_dataw_t; + typedef logic [ ChsPlaygndAxiNarrowStrobe-1:0] chs_playgnd_nar_strb_t; + + // External AXI slaves indexes + typedef enum byte_bt { + PeriphsSlvIdx = 'd0, + Dsa0SlvIdx = 'd1, + MemWriteSlvIdx = 'd2, + MemDmaReadSlvIdx = 'd3, + MemCoreReadSlvIdx = 'd4 + } axi_slv_idx_t; + + // External AXI masters indexes + typedef enum byte_bt { + Dsa0MstIdx = 'd0 + } axi_mst_idx_t; + + typedef enum doub_bt { + PeriphsBase = 'h0000_0000_2000_1000, + Dsa0Base = 'h0000_0000_3000_1000, + MemWriteBase = 'h0000_0000_4000_0000, + MemDmaReadBase = 'h0000_0000_5000_0000, + MemCoreReadBase = 'h0000_0000_6000_0000 + } axi_start_t; + + // AXI Slave Sizes + localparam doub_bt PeriphsSize = 'h0000_0000_0000_9000; + localparam doub_bt Dsa0Size = 'h0000_0000_0000_9000; + localparam doub_bt MemWriteSize = 'h0000_0000_1000_0000; + localparam doub_bt MemDmaReadSize = 'h0000_0000_1000_0000; + localparam doub_bt MemCoreReadSize = 'h0000_0000_1000_0000; + + typedef enum doub_bt { + PeriphsEnd = PeriphsBase + PeriphsSize, + Dsa0End = Dsa0Base + Dsa0Size, + MemWriteEnd = MemWriteBase + MemWriteSize, + MemDmaReadEnd = MemDmaReadBase + MemDmaReadSize, + MemCoreReadEnd = MemCoreReadBase + MemCoreReadSize + } axi_end_t; + + function automatic cheshire_cfg_t gen_playground_cfg(); + cheshire_cfg_t ret = DefaultCfg; + ret.Cva6ExtCieLength = 'h6000_0000; // all above 0x3000_0000 cached + ret.Cva6ExtCieOnTop = 1; + // External AXI ports (at most 8 ports and rules) + ret.AxiExtNumMst = 1; // For the playground, traffic DMA(s) + ret.AxiExtNumSlv = 5; // For the playground, traffic DMA(s) (config port), system timer + ret.AxiExtNumRules = 5; + // External AXI region map + ret.AxiExtRegionIdx = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadSlvIdx, MemDmaReadSlvIdx, MemWriteSlvIdx, Dsa0SlvIdx, PeriphsSlvIdx }; + ret.AxiExtRegionStart = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadBase, MemDmaReadBase, MemWriteBase, Dsa0Base, PeriphsBase }; + ret.AxiExtRegionEnd = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadEnd, MemDmaReadEnd, MemWriteEnd, Dsa0End, PeriphsEnd }; + ret.BusErr = 0; + return ret; + endfunction + + localparam cheshire_cfg_t ChsPlaygndCfg = gen_playground_cfg(); + +endpackage diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 03566135b..9156acb4c 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1470,9 +1470,9 @@ module cheshire_soc import cheshire_pkg::*; #( end - if (!(Cfg.Dma && Cfg.BusErr)) begin : gen_dma_bus_err_tie - assign intr.intn.bus_err.dma = '0; - end + //if (!(Cfg.Dma && Cfg.BusErr)) begin : gen_dma_bus_err_tie + // assign intr.intn.bus_err.dma = '0; + //end /////////////////// // Serial Link // diff --git a/sw/tests/2d_dma.c b/sw/tests/2d_dma.c new file mode 100755 index 000000000..1f8f19374 --- /dev/null +++ b/sw/tests/2d_dma.c @@ -0,0 +1,23 @@ +#include +#include +#include +#include "util.h" +#include "dif/dma.h" + +int main(void){ + + // Size of transfer + volatile uint64_t size_bytes = 8; + // Source stride + volatile uint64_t src_stride = 0; + // Destination stride + volatile uint64_t dst_stride = 0; + // Number of repetitions + volatile uint64_t num_reps = 128; + volatile uint64_t *dst = 0x50000000; + volatile uint64_t *src = 0x40000000; + + sys_dma_2d_blk_memcpy(dst, src, size_bytes, dst_stride, src_stride, num_reps); + + return 0; +} diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 2c7ebac84..80e8d2782 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -11,8 +11,8 @@ module fixture_cheshire_soc; `include "cheshire/typedef.svh" import cheshire_pkg::*; - - localparam cheshire_cfg_t DutCfg = DefaultCfg; + import cheshire_ext_playground_pkg::*; + localparam cheshire_cfg_t DutCfg = ChsPlaygndCfg; `CHESHIRE_TYPEDEF_ALL(, DutCfg) /////////// @@ -57,6 +57,13 @@ module fixture_cheshire_soc; logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i; logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o; + // External slaves + axi_slv_req_t [DutCfg.AxiExtNumSlv-1:0] axi_ext_slv_req; + axi_slv_rsp_t [DutCfg.AxiExtNumSlv-1:0] axi_ext_slv_rsp; + // External masters + axi_mst_req_t [DutCfg.AxiExtNumMst-1:0] axi_ext_mst_req; + axi_mst_rsp_t [DutCfg.AxiExtNumMst-1:0] axi_ext_mst_rsp; + cheshire_soc #( .Cfg ( DutCfg ), .ExtHartinfo ( '0 ), @@ -76,10 +83,10 @@ module fixture_cheshire_soc; .rtc_i ( rtc ), .axi_llc_mst_req_o ( axi_llc_mst_req ), .axi_llc_mst_rsp_i ( axi_llc_mst_rsp ), - .axi_ext_mst_req_i ( '0 ), - .axi_ext_mst_rsp_o ( ), - .axi_ext_slv_req_o ( ), - .axi_ext_slv_rsp_i ( '0 ), + .axi_ext_mst_req_i ( axi_ext_mst_req ), + .axi_ext_mst_rsp_o ( axi_ext_mst_rsp ), + .axi_ext_slv_req_o ( axi_ext_slv_req ), + .axi_ext_slv_rsp_i ( axi_ext_slv_rsp ), .reg_ext_slv_req_o ( ), .reg_ext_slv_rsp_i ( '0 ), .intr_ext_i ( '0 ), @@ -131,6 +138,30 @@ module fixture_cheshire_soc; .vga_blue_o ( ) ); + // Playground module + cheshire_ext_playground #( + .Cfg ( DutCfg ), + .axi_ext_mst_req_t ( axi_mst_req_t ), + .axi_ext_mst_rsp_t ( axi_mst_rsp_t ), + .axi_ext_slv_req_t ( axi_slv_req_t ), + .axi_ext_slv_rsp_t ( axi_slv_rsp_t ), + .reg_ext_req_t ( reg_req_t ), + .reg_ext_rsp_t ( reg_rsp_t ) + ) i_chs_ext_playgnd ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_mode_i ( test_mode ), + .rtc_i ( rtc ), + // TODO: connect master ports + .axi_ext_mst_req_o ( axi_ext_mst_req ), + .axi_ext_mst_rsp_i ( axi_ext_mst_rsp ), + .axi_ext_slv_req_i ( axi_ext_slv_req ), + .axi_ext_slv_rsp_o ( axi_ext_slv_rsp ), + // Unused + .reg_ext_slv_req_i ( '0 ), + .reg_ext_slv_rsp_o ( ) + ); + //////////////////////// // Tristate Adapter // //////////////////////// diff --git a/target/sim/vsim/run_pg.tcl b/target/sim/vsim/run_pg.tcl new file mode 100644 index 000000000..73e3fbb6a --- /dev/null +++ b/target/sim/vsim/run_pg.tcl @@ -0,0 +1,9 @@ +source compile.cheshire_soc.tcl +set BOOTMODE 0 +set PRELMODE 0 +set BINARY ../../../sw/tests/2d_dma.spm.elf +set VOPTARGS "+acc" + +source start.cheshire_soc.tcl + +log -r /*