From 5bbf23206ec915d3c85315b686df1f7ed2074c2d Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Wed, 20 Nov 2024 18:08:35 +0100 Subject: [PATCH] sw/sw.mk: Make IP generation ordered prerequisite to headers --- sw/sw.mk | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sw/sw.mk b/sw/sw.mk index da5184427..9f599cf11 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -76,13 +76,13 @@ $$(CHS_SW_DIR)/include/regs/$(1).h: $(2) $$(REGTOOL) --cdefines $$< > $$@ endef -$(eval $(call chs_sw_gen_hdr_rule,clint,$(CLINTROOT)/src/clint.hjson $(CLINTROOT)/.generated)) -$(eval $(call chs_sw_gen_hdr_rule,serial_link,$(CHS_ROOT)/hw/serial_link.hjson $(CHS_SLINK_DIR)/.generated)) -$(eval $(call chs_sw_gen_hdr_rule,axi_vga,$(AXI_VGA_ROOT)/data/axi_vga.hjson $(AXI_VGA_ROOT)/.generated)) +$(eval $(call chs_sw_gen_hdr_rule,clint,$(CLINTROOT)/src/clint.hjson | $(CLINTROOT)/.generated)) +$(eval $(call chs_sw_gen_hdr_rule,serial_link,$(CHS_ROOT)/hw/serial_link.hjson | $(CHS_SLINK_DIR)/.generated)) +$(eval $(call chs_sw_gen_hdr_rule,axi_vga,$(AXI_VGA_ROOT)/data/axi_vga.hjson | $(AXI_VGA_ROOT)/.generated)) $(eval $(call chs_sw_gen_hdr_rule,idma,$(IDMA_ROOT)/target/rtl/idma_reg64_2d.hjson)) $(eval $(call chs_sw_gen_hdr_rule,axi_llc,$(CHS_LLC_DIR)/data/axi_llc_regs.hjson)) $(eval $(call chs_sw_gen_hdr_rule,cheshire,$(CHS_ROOT)/hw/regs/cheshire_regs.hjson)) -$(eval $(call chs_sw_gen_hdr_rule,axi_rt,$(AXIRTROOT)/src/regs/axi_rt.hjson $(AXIRTROOT)/.generated)) +$(eval $(call chs_sw_gen_hdr_rule,axi_rt,$(AXIRTROOT)/src/regs/axi_rt.hjson | $(AXIRTROOT)/.generated)) # Generate headers for OT peripherals in the bendered repo itself CHS_SW_GEN_HDRS += $(OTPROOT)/.generated