From 55938cf6cdb2c4baa3b45dc6ef5f21e6985b8252 Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Tue, 5 Mar 2024 16:51:38 +0100 Subject: [PATCH] target/xilinx: Some cleanup, fix VCU128 VIO defaults --- .gitignore | 3 +++ target/xilinx/scripts/common.tcl | 3 +-- target/xilinx/scripts/impl_ip.tcl | 14 ++++++++++++-- target/xilinx/scripts/impl_sys.tcl | 9 +++++---- target/xilinx/scripts/util/flash.tcl | 4 ++-- target/xilinx/xilinx.mk | 2 +- 6 files changed, 24 insertions(+), 11 deletions(-) diff --git a/.gitignore b/.gitignore index 9aa38dc3b..c5b11f409 100644 --- a/.gitignore +++ b/.gitignore @@ -23,6 +23,7 @@ site/ *.gpth *.o *.a +*.dtb sw/deps/.patched # Test models @@ -40,3 +41,5 @@ target/sim/vsim/work/ target/xilinx/build target/xilinx/out target/xilinx/scripts/add_sources.* +**/*.jou +**/*.log diff --git a/target/xilinx/scripts/common.tcl b/target/xilinx/scripts/common.tcl index dcac6b23d..32066b8a1 100644 --- a/target/xilinx/scripts/common.tcl +++ b/target/xilinx/scripts/common.tcl @@ -123,7 +123,7 @@ proc insert_ilas {clk_net_name} { # Create probe after all signals with the same name have been collected if {$net_name_last != $net_name} { if {$net_name_last != ""} { - puts "Creating probe $i of width [llength $sig_list] fors `$net_name_last`." + puts "Creating probe $i of width [llength $sig_list] for `$net_name_last`." # probe0 already exists, and does not need to be created if {$i != 0} {create_debug_port i_ila probe} set_property port_width [llength $sig_list] [get_debug_ports i_ila/probe$i] @@ -139,5 +139,4 @@ proc insert_ilas {clk_net_name} { # Save constraints, then implement the debug core save_constraints -force implement_debug_core - write_debug_probes -force ${project_root}/probes.ltx } diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl index 9b33d1d34..474787fe7 100644 --- a/target/xilinx/scripts/impl_ip.tcl +++ b/target/xilinx/scripts/impl_ip.tcl @@ -84,8 +84,7 @@ switch $proj { vio { create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $proj switch $board { - genesys2 - - vcu128 { + genesys2 { set_property -dict [list \ CONFIG.C_NUM_PROBE_OUT {3} \ CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ @@ -96,6 +95,17 @@ switch $proj { CONFIG.C_NUM_PROBE_IN {0} \ ] [get_ips $proj] } + vcu128 { + set_property -dict [list \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $proj] + } default {nocfgexit $proj $board} } } diff --git a/target/xilinx/scripts/impl_sys.tcl b/target/xilinx/scripts/impl_sys.tcl index 23d55f5a8..08e14a7f2 100644 --- a/target/xilinx/scripts/impl_sys.tcl +++ b/target/xilinx/scripts/impl_sys.tcl @@ -27,10 +27,9 @@ set_property top ${proj}_top_xilinx [current_fileset] update_compile_order -fileset sources_1 # Set synthesis properties -set_property XPM_LIBRARIES XPM_MEMORY [current_project] -set_property strategy Flow_PerfOptimized_high [get_runs synth_1] -# TODO: this makes Vivado run out of resources on VCU128... Can we do this locally? -#set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] +# TODO: investigate resource-affordable retiming +set_property XPM_LIBRARIES XPM_MEMORY [current_project] +set_property strategy Flow_PerfOptimized_high [get_runs synth_1] # Elaborate and open design to explore all clocks synth_design -rtl -name rtl_1 @@ -70,3 +69,5 @@ if {![string match -nocase {*timing constraints are met*} $trep]} { file mkdir ${xilinx_root}/out file copy -force ${project_root}/${proj}.runs/impl_1/cheshire_top_xilinx.bit \ ${xilinx_root}/out/${proj}.${board}.bit +file copy -force ${project_root}/${proj}.runs/impl_1/cheshire_top_xilinx.ltx \ + ${xilinx_root}/out/${proj}.${board}.ltx diff --git a/target/xilinx/scripts/util/flash.tcl b/target/xilinx/scripts/util/flash.tcl index c984101e3..bcf672c68 100644 --- a/target/xilinx/scripts/util/flash.tcl +++ b/target/xilinx/scripts/util/flash.tcl @@ -27,7 +27,7 @@ switch $board { write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ -loaddata "up $offs $file" -checksum -file $mcs set_property -dict [list \ - PROGRAM.ADDRESS_RANGE {use_file} \ + PROGRAM.ADDRESS_RANGE {use_file} \ PROGRAM.FILES [list $mcs] \ PROGRAM.PRM_FILE {} \ PROGRAM.UNUSED_PIN_TERMINATION {pull-none} \ @@ -36,7 +36,7 @@ switch $board { PROGRAM.CFG_PROGRAM {1} \ PROGRAM.VERIFY {1} \ PROGRAM.CHECKSUM {0} \ - ] [get_ips $hw_cfgmem] + ] $hw_cfgmem } default {nocfgexit flash_spi $board} } diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 8b4a95e0f..316fbee6f 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -85,6 +85,6 @@ $(eval $(call chs_xilinx_util_rule,program,$(CHS_XILINX_DIR)/out/cheshire.%.bit) # Flash onboard memory with the file `CHS_XILINX_FLASH_IMG` (only selected boards). # `%` is substituted with the board name. The default is the Linux disk image for that board. -CHS_XILINX_FLASH_IMG ?= $(CHS_SW_DIR)/out/linux.%.gpt.bin +CHS_XILINX_FLASH_IMG ?= $(CHS_SW_DIR)/boot/linux.%.gpt.bin .PHONY: chs-xilinx-flash-% $(eval $(call chs_xilinx_util_rule,flash,$(CHS_XILINX_FLASH_IMG)))