diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
index e12a0201..e9af360a 100644
--- a/target/sim/src/vip_cheshire_soc.sv
+++ b/target/sim/src/vip_cheshire_soc.sv
@@ -274,6 +274,38 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     jtag_elf_preload(binary, entry);
   endtask
 
+  task automatic jtag_write_reg32(input logic [31:0] start_addr, logic [63:0] value);
+    logic [31:0]      rdata;
+
+    automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
+
+    $display("[JTAG] Start writing at %x ", start_addr);
+    jtag_write(dm::SBCS, sbcs, 0, 1);
+
+    // Write address
+    $display("[JTAG] Start writing address");
+    jtag_write(dm::SBAddress1, 'h0);
+    jtag_write(dm::SBAddress0, start_addr);
+
+    // Write data
+    $display("[JTAG] Start writing data");
+    jtag_write(dm::SBData0, value[31:0]);
+
+  endtask
+
+  task automatic jtag_read_reg32(
+    input logic [31:0] addr,
+    output logic [31:0] data,
+    input int unsigned idle_cycles
+  );
+    automatic dm::sbcs_t sbcs = dm::sbcs_t'{sbreadonaddr: 1'b1, sbaccess: 2, default: '0};
+    jtag_write(dm::SBCS, sbcs, 0, 1);
+    jtag_write(dm::SBAddress1, 'h0);
+    jtag_write(dm::SBAddress0, addr[31:0]);
+    jtag_dbg.wait_idle(idle_cycles);
+    jtag_dbg.read_dmi_exp_backoff(dm::SBData0, data);
+  endtask
+
   task automatic jtag_write_reg(input logic [31:0] start_addr, input doub_bt value);
     logic [63:0]      rdata;