diff --git a/target/xilinx/flavor_bd/README.md b/target/xilinx/flavor_bd/README.md new file mode 100644 index 00000000..9066dd95 --- /dev/null +++ b/target/xilinx/flavor_bd/README.md @@ -0,0 +1,2 @@ +This folder is a placeholder for a block design based flow +See example in [Carfield](https://github.com/pulp-platform/carfield/tree/main/target/xilinx/flavor_bd) diff --git a/target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc b/target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc deleted file mode 100644 index 3a2446e3..00000000 --- a/target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc +++ /dev/null @@ -1,5 +0,0 @@ -create_clock -name carfield_ooc_synth_clk_100 -period 100 [get_ports clk_100] -create_clock -name carfield_ooc_synth_clk_50 -period 50 [get_ports clk_50] -create_clock -name carfield_ooc_synth_clk_20 -period 20 [get_ports clk_20] -create_clock -name carfield_ooc_synth_clk_10 -period 10 [get_ports clk_10] -set_case_analysis 0 [get_ports testmode_i] diff --git a/target/xilinx/flavor_bd/constraints/vcu128.xdc b/target/xilinx/flavor_bd/constraints/vcu128.xdc deleted file mode 100644 index 737a40d2..00000000 --- a/target/xilinx/flavor_bd/constraints/vcu128.xdc +++ /dev/null @@ -1,30 +0,0 @@ -# VIOs are asynchronous -set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}] - -# Create system clocks -create_clock -period 10 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT] -create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] -create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]] - -# Pin related - -set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]] -set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]] - -set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 -set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 -set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 -set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 - -set_property PACKAGE_PIN BM29 [get_ports cpu_reset] -set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] - -set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_clk_n[0]] -set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_n[0]] -set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_clk_p[0]] -set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_p[0]] -set_property PACKAGE_PIN BH51 [get_ports sys_clk_clk_p[0]] -set_property PACKAGE_PIN BJ51 [get_ports sys_clk_clk_n[0]] diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc deleted file mode 100644 index 38bb4b50..00000000 --- a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc +++ /dev/null @@ -1,17 +0,0 @@ -set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND -set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; - -set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD -set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; - -set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] - -set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; - -set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; - -set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI -set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] diff --git a/target/xilinx/flavor_bd/flavor_bd.mk b/target/xilinx/flavor_bd/flavor_bd.mk deleted file mode 100644 index 7cd607ae..00000000 --- a/target/xilinx/flavor_bd/flavor_bd.mk +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Cyril Koenig - -# Output bitstream -xilinx_bit_bd = $(CHS_XIL_DIR)/flavor_bd/out/design_1_wrapper.bit - -# Vivado variables -vivado_env_bd := \ - XILINX_PROJECT=$(XILINX_PROJECT) \ - XILINX_BOARD=$(XILINX_BOARD) \ - XILINX_PART=$(xilinx_part) \ - XILINX_BOARD_LONG=$(xilinx_board_long) \ - XILINX_PORT=$(XILINX_PORT) \ - XILINX_HOST=$(XILINX_HOST) \ - XILINX_FPGA_PATH=$(XILINX_FPGA_PATH) \ - XILINX_BIT=$(xilinx_bit) \ - GEN_NO_HYPERBUS=$(GEN_NO_HYPERBUS) \ - GEN_EXT_JTAG=$(GEN_EXT_JTAG) \ - XILINX_ROUTED_DCP=$(XILINX_ROUTED_DCP) \ - XILINX_CHECK_TIMING=$(XILINX_CHECK_TIMING) \ - XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY) - -# Flavor specific bender args -xilinx_targs_bd := -t xilinx_bd - -# Add source files for ip -$(CHS_XIL_DIR)/flavor_bd/scripts/add_sources_cheshire_ip.tcl: Bender.yml - $(BENDER) script vivado $(xilinx_targs) $(xilinx_targs_bd) > $@ - -# Build Cheshire IP -$(CHS_XIL_DIR)/flavor_bd/cheshire_ip/cheshire_ip.xpr: $(CHS_XIL_DIR)/flavor_bd/scripts/add_sources_cheshire_ip.tcl - cd $(CHS_XIL_DIR)/flavor_bd && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run_cheshire_ip.tcl - -# Add includes files for block design -$(CHS_XIL_DIR)/flavor_bd/scripts/add_includes.tcl: - $(BENDER) script vivado --only-defines --only-includes $(xilinx_targs) $(xilinx_targs_bd) > $@ - -# Build block design bitstream -$(CHS_XIL_DIR)/flavor_bd/out/%.bit: $(CHS_XIL_DIR)/flavor_bd/scripts/add_includes.tcl $(CHS_XIL_DIR)/flavor_bd/cheshire_ip/cheshire_ip.xpr - mkdir -p $(CHS_XIL_DIR)/flavor_bd/out - cd $(CHS_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl - find $(CHS_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CHS_XIL_DIR)/flavor_bd/out - -chs-xil-clean-bd: - cd $(CHS_XIL_DIR)/flavor_bd && rm -rf scripts/add_sources* scripts/add_includes* *.log *.jou *.str *.mif cheshire* .Xil/ - -.PHONY: chs-xil-clean-bd diff --git a/target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl b/target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl deleted file mode 100644 index f2499c60..00000000 --- a/target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Cyril Koenig - -set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ] -set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ] -set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ] -set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ] -set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ] -set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ] -connect_bd_net -net cheshire_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_gnd_o] -connect_bd_net -net cheshire_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_tdo_o] -connect_bd_net -net cheshire_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_vdd_o] -connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tck_i] -connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tdi_i] -connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tms_i] diff --git a/target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl b/target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl deleted file mode 100644 index 362c2f3f..00000000 --- a/target/xilinx/flavor_bd/scripts/cheshire_bd_vcu128.tcl +++ /dev/null @@ -1,526 +0,0 @@ - -################################################################ -# This is a generated script based on design: design_1 -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2020.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source design_1_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xcvu37p-fsvh2892-2L-e - set_property BOARD_PART xilinx.com:vcu128:part0:1.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name design_1 - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:axi_dma:7.1\ -xilinx.com:ip:axi_ethernet:7.2\ -ethz.ch:user:cheshire_xilinx_ip:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:ddr4:2.2\ -xilinx.com:ip:xlconstant:1.1\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:smartconnect:1.0\ -xilinx.com:ip:util_ds_buf:2.1\ -xilinx.com:ip:util_vector_logic:2.0\ -xilinx.com:ip:vio:3.0\ -xilinx.com:ip:xdma:4.1\ -" - - set list_ips_missing "" - common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -if { $bCheckIPsPassed != 1 } { - common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set ddr4_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram ] - - set mdio_mdc [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio_mdc ] - - set pci_express_x4 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pci_express_x4 ] - - set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {100000000} \ - ] $pcie_refclk - - set sgmii_lvds [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sgmii_rtl:1.0 sgmii_lvds ] - - set sgmii_phyclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sgmii_phyclk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {625000000} \ - ] $sgmii_phyclk - - set sys_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {100000000} \ - ] $sys_clk - - - # Create ports - set dummy_port_in [ create_bd_port -dir I -type rst dummy_port_in ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $dummy_port_in - set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_LOW} \ - ] $pcie_perstn - set reset [ create_bd_port -dir I -type rst reset ] - set_property -dict [ list \ - CONFIG.POLARITY {ACTIVE_HIGH} \ - ] $reset - set uart_rx_i [ create_bd_port -dir I uart_rx_i ] - set uart_tx_o [ create_bd_port -dir O uart_tx_o ] - - # Create instance: axi_dma_0, and set properties - set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ] - set_property -dict [ list \ - CONFIG.c_addr_width {64} \ - CONFIG.c_include_mm2s_dre {1} \ - CONFIG.c_include_s2mm_dre {1} \ - CONFIG.c_sg_length_width {16} \ - CONFIG.c_sg_use_stsapp_length {1} \ - ] $axi_dma_0 - - # Create instance: axi_ethernet_0, and set properties - set axi_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.2 axi_ethernet_0 ] - set_property -dict [ list \ - CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk} \ - CONFIG.ENABLE_LVDS {true} \ - CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds} \ - CONFIG.InstantiateBitslice0 {true} \ - CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc} \ - CONFIG.PHYADDR {0} \ - CONFIG.PHYRST_BOARD_INTERFACE {Custom} \ - CONFIG.PHYRST_BOARD_INTERFACE_DUMMY_PORT {dummy_port_in} \ - CONFIG.PHY_TYPE {SGMII} \ - CONFIG.RXCSUM {Full} \ - CONFIG.TXCSUM {Full} \ - CONFIG.lvdsclkrate {625} \ - CONFIG.rxlane0_placement {DIFF_PAIR_2} \ - CONFIG.rxnibblebitslice0used {false} \ - CONFIG.txlane0_placement {DIFF_PAIR_1} \ - ] $axi_ethernet_0 - - # Create instance: cheshire_xilinx_ip_0, and set properties - set cheshire_xilinx_ip_0 [ create_bd_cell -type ip -vlnv ethz.ch:user:cheshire_xilinx_ip:1.0 cheshire_xilinx_ip_0 ] - - # Create instance: clk_wiz_0, and set properties - set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {188.586} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10.000} \ - CONFIG.CLKOUT1_USED {true} \ - CONFIG.CLKOUT2_JITTER {162.167} \ - CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {20.000} \ - CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT3_JITTER {132.683} \ - CONFIG.CLKOUT3_PHASE_ERROR {87.180} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {50.000} \ - CONFIG.CLKOUT3_USED {true} \ - CONFIG.CLKOUT4_JITTER {115.831} \ - CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ - CONFIG.CLKOUT4_USED {true} \ - CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ - CONFIG.CLK_OUT1_PORT {clk_10} \ - CONFIG.CLK_OUT2_PORT {clk_20} \ - CONFIG.CLK_OUT3_PORT {clk_50} \ - CONFIG.CLK_OUT4_PORT {clk_100} \ - CONFIG.ENABLE_CLOCK_MONITOR {false} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {120.000} \ - CONFIG.MMCM_CLKOUT1_DIVIDE {60} \ - CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ - CONFIG.MMCM_CLKOUT3_DIVIDE {12} \ - CONFIG.NUM_OUT_CLKS {4} \ - CONFIG.PRIMITIVE {MMCM} \ - CONFIG.PRIM_SOURCE {No_buffer} \ - CONFIG.RESET_BOARD_INTERFACE {reset} \ - CONFIG.USE_BOARD_FLOW {true} \ - CONFIG.USE_LOCKED {true} \ - CONFIG.USE_RESET {false} \ - ] $clk_wiz_0 - - # Create instance: concat_irq, and set properties - set concat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_irq ] - set_property -dict [ list \ - CONFIG.NUM_PORTS {12} \ - ] $concat_irq - - # Create instance: ddr4_0, and set properties - set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] - set_property -dict [ list \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {None} \ - CONFIG.C0_CLOCK_BOARD_INTERFACE {Custom} \ - CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ - CONFIG.System_Clock {No_Buffer} \ - ] $ddr4_0 - - # Create instance: low, and set properties - set low [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 low ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - ] $low - - # Create instance: psr_10, and set properties - set psr_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_10 ] - set_property -dict [ list \ - CONFIG.C_AUX_RESET_HIGH {1} \ - CONFIG.RESET_BOARD_INTERFACE {reset} \ - CONFIG.USE_BOARD_FLOW {true} \ - ] $psr_10 - - # Create instance: psr_333, and set properties - set psr_333 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_333 ] - set_property -dict [ list \ - CONFIG.C_AUX_RESET_HIGH {1} \ - CONFIG.RESET_BOARD_INTERFACE {reset} \ - ] $psr_333 - - # Create instance: smartconnect_0, and set properties - set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] - set_property -dict [ list \ - CONFIG.NUM_CLKS {2} \ - ] $smartconnect_0 - - # Create instance: util_ds_buf_0, and set properties - set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ] - set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDS} \ - CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {Custom} \ - CONFIG.USE_BOARD_FLOW {true} \ - ] $util_ds_buf_0 - - # Create instance: util_ds_buf_1, and set properties - set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ] - set_property -dict [ list \ - CONFIG.C_BUF_TYPE {IBUFDSGTE} \ - CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \ - CONFIG.USE_BOARD_FLOW {true} \ - ] $util_ds_buf_1 - - # Create instance: util_vector_logic_0, and set properties - set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ] - set_property -dict [ list \ - CONFIG.C_OPERATION {or} \ - CONFIG.C_SIZE {1} \ - CONFIG.LOGO_FILE {data/sym_orgate.png} \ - ] $util_vector_logic_0 - - # Create instance: vio_0, and set properties - set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] - set_property -dict [ list \ - CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ - CONFIG.C_NUM_PROBE_IN {0} \ - CONFIG.C_NUM_PROBE_OUT {3} \ - CONFIG.C_PROBE_OUT0_INIT_VAL {0x2} \ - CONFIG.C_PROBE_OUT0_WIDTH {2} \ - CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ - CONFIG.C_PROBE_OUT1_WIDTH {2} \ - ] $vio_0 - - # Create instance: xbar_dram, and set properties - set xbar_dram [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_dram ] - set_property -dict [ list \ - CONFIG.HAS_ARESETN {1} \ - CONFIG.NUM_CLKS {2} \ - CONFIG.NUM_SI {1} \ - ] $xbar_dram - - # Create instance: xbar_periph_in, and set properties - set xbar_periph_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_in ] - set_property -dict [ list \ - CONFIG.NUM_CLKS {1} \ - CONFIG.NUM_SI {4} \ - ] $xbar_periph_in - - # Create instance: xbar_periph_out, and set properties - set xbar_periph_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 xbar_periph_out ] - set_property -dict [ list \ - CONFIG.NUM_CLKS {3} \ - CONFIG.NUM_MI {3} \ - CONFIG.NUM_SI {1} \ - ] $xbar_periph_out - - # Create instance: xdma_0, and set properties - set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ] - set_property -dict [ list \ - CONFIG.PCIE_BOARD_INTERFACE {pci_express_x4} \ - CONFIG.PF0_DEVICE_ID_mqdma {9014} \ - CONFIG.PF2_DEVICE_ID_mqdma {9014} \ - CONFIG.PF3_DEVICE_ID_mqdma {9014} \ - CONFIG.SYS_RST_N_BOARD_INTERFACE {pcie_perstn} \ - CONFIG.axi_addr_width {64} \ - CONFIG.axi_bypass_64bit_en {true} \ - CONFIG.axi_bypass_prefetchable {true} \ - CONFIG.axist_bypass_en {true} \ - CONFIG.axist_bypass_scale {Gigabytes} \ - CONFIG.axist_bypass_size {4} \ - CONFIG.axisten_freq {125} \ - CONFIG.functional_mode {DMA} \ - CONFIG.pf0_device_id {9014} \ - CONFIG.pl_link_cap_max_link_width {X4} \ - CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \ - CONFIG.xdma_axilite_slave {false} \ - ] $xdma_0 - - # Create interface connections - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_CNTRL [get_bd_intf_pins axi_dma_0/M_AXIS_CNTRL] [get_bd_intf_pins axi_ethernet_0/s_axis_txc] - connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins axi_ethernet_0/s_axis_txd] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_dma_0/M_AXI_MM2S] [get_bd_intf_pins xbar_periph_in/S01_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins xbar_periph_in/S02_AXI] - connect_bd_intf_net -intf_net axi_dma_0_M_AXI_SG [get_bd_intf_pins axi_dma_0/M_AXI_SG] [get_bd_intf_pins xbar_periph_in/S00_AXI] - connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxd [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins axi_ethernet_0/m_axis_rxd] - connect_bd_intf_net -intf_net axi_ethernet_0_m_axis_rxs [get_bd_intf_pins axi_dma_0/S_AXIS_STS] [get_bd_intf_pins axi_ethernet_0/m_axis_rxs] - connect_bd_intf_net -intf_net axi_ethernet_0_mdio [get_bd_intf_ports mdio_mdc] [get_bd_intf_pins axi_ethernet_0/mdio] - connect_bd_intf_net -intf_net axi_ethernet_0_sgmii [get_bd_intf_ports sgmii_lvds] [get_bd_intf_pins axi_ethernet_0/sgmii] - connect_bd_intf_net -intf_net cheshire_xilinx_ip_0_dram_axi [get_bd_intf_pins cheshire_xilinx_ip_0/dram_axi] [get_bd_intf_pins xbar_dram/S00_AXI] - connect_bd_intf_net -intf_net cheshire_xilinx_ip_0_periph_axi_m [get_bd_intf_pins cheshire_xilinx_ip_0/periph_axi_m] [get_bd_intf_pins xbar_periph_out/S00_AXI] - connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram] [get_bd_intf_pins ddr4_0/C0_DDR4] - connect_bd_intf_net -intf_net diff_clock_rtl_1 [get_bd_intf_ports sys_clk] [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] - connect_bd_intf_net -intf_net pcie_refclk_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins util_ds_buf_1/CLK_IN_D] - connect_bd_intf_net -intf_net sgmii_phyclk_1 [get_bd_intf_ports sgmii_phyclk] [get_bd_intf_pins axi_ethernet_0/lvds_clk] - connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins xbar_dram/M00_AXI] - connect_bd_intf_net -intf_net smartconnect_0_M00_AXI1 [get_bd_intf_pins smartconnect_0/M00_AXI] [get_bd_intf_pins xbar_periph_in/S03_AXI] - connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins axi_ethernet_0/s_axi] [get_bd_intf_pins xbar_periph_out/M00_AXI] - connect_bd_intf_net -intf_net xbar_periph_in_M00_AXI [get_bd_intf_pins cheshire_xilinx_ip_0/periph_axi_s] [get_bd_intf_pins xbar_periph_in/M00_AXI] - connect_bd_intf_net -intf_net xbar_periph_out_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins xbar_periph_out/M01_AXI] - connect_bd_intf_net -intf_net xbar_periph_out_M02_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins xbar_periph_out/M02_AXI] - connect_bd_intf_net -intf_net xdma_0_M_AXI [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI] - connect_bd_intf_net -intf_net xdma_0_M_AXI_BYPASS [get_bd_intf_pins smartconnect_0/S01_AXI] [get_bd_intf_pins xdma_0/M_AXI_BYPASS] - connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x4] [get_bd_intf_pins xdma_0/pcie_mgt] - - # Create port connections - connect_bd_net -net axi_dma_0_mm2s_cntrl_reset_out_n [get_bd_pins axi_dma_0/mm2s_cntrl_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txc_arstn] - connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins concat_irq/In2] - connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txd_arstn] - connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins concat_irq/In3] - connect_bd_net -net axi_dma_0_s2mm_prmry_reset_out_n [get_bd_pins axi_dma_0/s2mm_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxd_arstn] - connect_bd_net -net axi_dma_0_s2mm_sts_reset_out_n [get_bd_pins axi_dma_0/s2mm_sts_reset_out_n] [get_bd_pins axi_ethernet_0/axi_rxs_arstn] - connect_bd_net -net axi_ethernet_0_interrupt [get_bd_pins axi_ethernet_0/interrupt] [get_bd_pins concat_irq/In0] - connect_bd_net -net axi_ethernet_0_mac_irq [get_bd_pins axi_ethernet_0/mac_irq] [get_bd_pins concat_irq/In5] - connect_bd_net -net cheshire_xilinx_ip_0_dram_axi_m_aclk [get_bd_pins cheshire_xilinx_ip_0/dram_axi_m_aclk] [get_bd_pins xbar_dram/aclk] - connect_bd_net -net cheshire_xilinx_ip_0_periph_axi_m_aclk [get_bd_pins cheshire_xilinx_ip_0/periph_axi_m_aclk] [get_bd_pins xbar_periph_out/aclk] - connect_bd_net -net cheshire_xilinx_ip_0_uart_tx_o [get_bd_ports uart_tx_o] [get_bd_pins cheshire_xilinx_ip_0/uart_tx_o] - connect_bd_net -net clk_wiz_0_clk_10 [get_bd_pins cheshire_xilinx_ip_0/clk_10] [get_bd_pins clk_wiz_0/clk_10] [get_bd_pins psr_10/slowest_sync_clk] - connect_bd_net -net clk_wiz_0_clk_20 [get_bd_pins cheshire_xilinx_ip_0/clk_20] [get_bd_pins clk_wiz_0/clk_20] - connect_bd_net -net clk_wiz_0_clk_50 [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_ethernet_0/axis_clk] [get_bd_pins axi_ethernet_0/s_axi_lite_clk] [get_bd_pins cheshire_xilinx_ip_0/clk_50] [get_bd_pins clk_wiz_0/clk_50] [get_bd_pins smartconnect_0/aclk1] [get_bd_pins vio_0/clk] [get_bd_pins xbar_periph_in/aclk] [get_bd_pins xbar_periph_out/aclk1] - connect_bd_net -net clk_wiz_0_clk_100 [get_bd_pins cheshire_xilinx_ip_0/clk_100] [get_bd_pins clk_wiz_0/clk_100] - connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins psr_10/dcm_locked] - connect_bd_net -net concat_irq_dout [get_bd_pins cheshire_xilinx_ip_0/gpio_i] [get_bd_pins concat_irq/dout] - connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins psr_333/slowest_sync_clk] [get_bd_pins xbar_dram/aclk1] [get_bd_pins xbar_periph_out/aclk2] - connect_bd_net -net dummy_port_in_1 [get_bd_ports dummy_port_in] [get_bd_pins axi_ethernet_0/dummy_port_in] - connect_bd_net -net low_dout [get_bd_pins cheshire_xilinx_ip_0/testmode_i] [get_bd_pins low/dout] - connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins xdma_0/sys_rst_n] - connect_bd_net -net psr_10_interconnect_aresetn [get_bd_pins psr_10/interconnect_aresetn] [get_bd_pins xbar_dram/aresetn] [get_bd_pins xbar_periph_in/aresetn] [get_bd_pins xbar_periph_out/aresetn] - connect_bd_net -net psr_10_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_ethernet_0/s_axi_lite_resetn] [get_bd_pins psr_10/peripheral_aresetn] - connect_bd_net -net psr_333_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins psr_333/peripheral_aresetn] - connect_bd_net -net psr_333_peripheral_reset [get_bd_pins ddr4_0/sys_rst] [get_bd_pins psr_333/peripheral_reset] - connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins psr_10/ext_reset_in] [get_bd_pins psr_333/ext_reset_in] [get_bd_pins util_vector_logic_0/Op1] - connect_bd_net -net uart_rx_i_1 [get_bd_ports uart_rx_i] [get_bd_pins cheshire_xilinx_ip_0/uart_rx_i] - connect_bd_net -net util_ds_buf_0_IBUF_OUT [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_sys_clk_i] [get_bd_pins util_ds_buf_0/IBUF_OUT] - connect_bd_net -net util_ds_buf_1_IBUF_DS_ODIV2 [get_bd_pins util_ds_buf_1/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] - connect_bd_net -net util_ds_buf_1_IBUF_OUT [get_bd_pins util_ds_buf_1/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] - connect_bd_net -net util_vector_logic_0_Res [get_bd_pins cheshire_xilinx_ip_0/cpu_reset] [get_bd_pins util_vector_logic_0/Res] - connect_bd_net -net vio_0_probe_out0 [get_bd_pins cheshire_xilinx_ip_0/boot_mode_i] [get_bd_pins vio_0/probe_out0] - connect_bd_net -net vio_0_probe_out2 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out2] - connect_bd_net -net xdma_0_axi_aclk [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk] - - # Create address segments - assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force - assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force - assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force - assign_bd_address -offset 0x41E00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force - assign_bd_address -offset 0x40C00000 -range 0x00040000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs axi_ethernet_0/s_axi/Reg0] -force - assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/dram_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force - assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force - assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma_0/M_AXI_BYPASS] [get_bd_addr_segs cheshire_xilinx_ip_0/periph_axi_s/reg0] -force - - # Exclude Address Segments - exclude_bd_addr_seg -offset 0x80000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces cheshire_xilinx_ip_0/periph_axi_m] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] - - - # Restore current instance - current_bd_instance $oldCurInst - - validate_bd_design - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/target/xilinx/flavor_bd/scripts/run.tcl b/target/xilinx/flavor_bd/scripts/run.tcl deleted file mode 100644 index 16037468..00000000 --- a/target/xilinx/flavor_bd/scripts/run.tcl +++ /dev/null @@ -1,131 +0,0 @@ -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Cyril Koenig - -# Create project -set project $::env(XILINX_PROJECT) - -create_project $project ./$project -force -part $::env(XILINX_PART) -set_property board_part $::env(XILINX_BOARD_LONG) [current_project] -set_property XPM_LIBRARIES XPM_MEMORY [current_project] - -# set number of threads to 8 (maximum, unfortunately) -set_param general.maxThreads 8 - -# Define sources -set_property ip_repo_paths ./cheshire_ip [current_project] -update_ip_catalog - -import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc - -source scripts/cheshire_bd_$::env(XILINX_BOARD).tcl - -source scripts/add_includes.tcl - -# Add the ext_jtag pins to block design -if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} { - source scripts/cheshire_bd_ext_jtag.tcl - import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc -} - -make_wrapper -files [get_files $project/$project.srcs/sources_1/bd/design_1/design_1.bd] -top -add_files -norecurse $project/$project.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v - -# Create OOC runs -generate_target all [get_files *design_1.bd] -export_ip_user_files -of_objects [get_files *design_1.bd] -no_script -create_ip_run [get_files *design_1.bd] - -# Start OOC synthesis of changed IPs -set synth_runs [get_runs *synth*] -# Exclude the whole design (synth_1) and the cheshire IP (bug) -set all_ooc_synth [lsearch -regexp -all -inline -not $synth_runs {^synth_1$|cheshire}] -set runs_queued {} -foreach run $all_ooc_synth { - if {[get_property PROGRESS [get_run $run]] != "100%"} { - puts "Launching run $run" - lappend runs_queued $run - # Default synthesis strategy - set_property strategy Flow_RuntimeOptimized [get_runs $run] - } else { - puts "Skipping 100% complete run: $run" - } -} -if {[llength $runs_queued] != 0} { - reset_run $runs_queued - launch_runs $runs_queued -jobs 16 - puts "Waiting on $runs_queued" - foreach run $runs_queued { - wait_on_run $run - } - # reset main synthesis - reset_run synth_1 -} - -set_property strategy Flow_RuntimeOptimized [get_runs synth_1] -set_property strategy Flow_RuntimeOptimized [get_runs impl_1] - -set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] -# Enable sfcu due to package conflicts -set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-sfcu} -objects [get_runs synth_1] - -launch_runs synth_1 -wait_on_run synth_1 -open_run synth_1 -name synth_1 - -# Instantiate ILA -set DEBUG [llength [get_nets -hier -filter {MARK_DEBUG == 1}]] -if ($DEBUG) { - # Create core - puts "Creating debug core..." - create_debug_core u_ila_0 ila - set_property -dict "ALL_PROBE_SAME_MU true ALL_PROBE_SAME_MU_CNT 4 C_ADV_TRIGGER true C_DATA_DEPTH 16384 \ - C_EN_STRG_QUAL true C_INPUT_PIPE_STAGES 0 C_TRIGIN_EN false C_TRIGOUT_EN false" [get_debug_cores u_ila_0] - ## Clock - set_property port_width 1 [get_debug_ports u_ila_0/clk] - connect_debug_port u_ila_0/clk [get_nets design_1_i/clk_wiz_0_clk_50] - # Get nets to debug - set debugNets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]] - set netNameLast "" - set probe_i 0 - # Loop through all nets (add extra list element to ensure last net is processed) - foreach net [concat $debugNets {""}] { - # Remove trailing array index - regsub {\[[0-9]*\]$} $net {} netName - # Create probe after all signals with the same name have been collected - if {$netNameLast != $netName} { - if {$netNameLast != ""} { - puts "Creating probe $probe_i with width [llength $sigList] for signal '$netNameLast'" - # probe0 already exists, and does not need to be created - if {$probe_i != 0} { - create_debug_port u_ila_0 probe - } - set_property port_width [llength $sigList] [get_debug_ports u_ila_0/probe$probe_i] - set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe$probe_i] - connect_debug_port u_ila_0/probe$probe_i [get_nets $sigList] - incr probe_i - } - set sigList "" - } - lappend sigList $net - set netNameLast $netName - } - # Need to save save constraints before implementing the core - set_property target_constrs_file [get_files $::env(XILINX_BOARD).xdc] [current_fileset -constrset] - save_constraints -force - implement_debug_core - write_debug_probes -force probes.ltx -} - -# Incremental implementation -if {[info exists ::env(ROUTED_DCP)] && [file exists $::env(ROUTED_DCP)]} { - set_property incremental_checkpoint $::env(ROUTED_DCP) [get_runs impl_1] -} - -# Implementation -launch_runs impl_1 -wait_on_run impl_1 -launch_runs impl_1 -to_step write_bitstream -wait_on_run impl_1 diff --git a/target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl b/target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl deleted file mode 100644 index b71329f1..00000000 --- a/target/xilinx/flavor_bd/scripts/run_cheshire_ip.tcl +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright 2020 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Cyril Koenig - -# Create project -set project cheshire_ip - -create_project $project ./$project -force -part $::env(XILINX_PART) -set_property XPM_LIBRARIES XPM_MEMORY [current_project] - -# set number of threads to 8 (maximum, unfortunately) -set_param general.maxThreads 8 - -# Define sources -source scripts/add_sources_cheshire_ip.tcl - -# Add constraints -add_files -fileset constrs_1 constraints/ooc_cheshire_ip.xdc -set_property USED_IN {synthesis out_of_context} [get_files constraints/ooc_cheshire_ip.xdc] -add_files -fileset constrs_1 ../flavor_vanilla/constraints/cheshire.xdc - -# Package IP -set_property top cheshire_xilinx_ip [current_fileset] - -update_compile_order -fileset sources_1 -synth_design -rtl -name rtl_1 - -ipx::package_project -root_dir ./${project} -vendor ethz.ch -library user -taxonomy /UserIP -set_current true - -exit diff --git a/target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v b/target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v deleted file mode 100644 index 79bc1bca..00000000 --- a/target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v +++ /dev/null @@ -1,441 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Cyril Koenig -// Just a verilog wrapper to accomodate Vivado - -module cheshire_xilinx_ip -( -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH" *) - input wire cpu_reset , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_10" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 10000000" *) - input wire clk_10 , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_20" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 20000000" *) - input wire clk_20 , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_50" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000, ASSOCIATED_BUSIF periph_axi_s" *) - input wire clk_50 , -(* X_INTERFACE_INFO = "xilinx.com:signal:clock_rtl:1.0 clock clk_100" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *) - input wire clk_100 , - - input wire testmode_i , - input wire [1:0] boot_mode_i , - - input wire [31:0] gpio_i, - - input wire jtag_tck_i , - input wire jtag_tms_i , - input wire jtag_tdi_i , - output wire jtag_tdo_o , - input wire jtag_trst_ni , - output wire jtag_vdd_o , - output wire jtag_gnd_o , - - output wire uart_tx_o , - input wire uart_rx_i , - - // MASTER AXI DRAM - -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) - output wire [47:0] dram_axi_m_axi_araddr, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARBURST" *) - output wire [1:0] dram_axi_m_axi_arburst, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARCACHE" *) - output wire [3:0] dram_axi_m_axi_arcache, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARID" *) - output wire [6:0]dram_axi_m_axi_arid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARLEN" *) - output wire [7:0] dram_axi_m_axi_arlen, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARLOCK" *) - output wire dram_axi_m_axi_arlock, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARPROT" *) - output wire [2:0] dram_axi_m_axi_arprot, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARQOS" *) - output wire [3:0] dram_axi_m_axi_arqos, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARREADY" *) - input wire dram_axi_m_axi_arready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARSIZE" *) - output wire [2:0] dram_axi_m_axi_arsize, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi ARVALID" *) - output wire dram_axi_m_axi_arvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWADDR" *) - output wire [47:0] dram_axi_m_axi_awaddr, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWBURST" *) - output wire [1:0] dram_axi_m_axi_awburst, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWCACHE" *) - output wire [3:0] dram_axi_m_axi_awcache, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWID" *) - output wire [6:0] dram_axi_m_axi_awid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWLEN" *) - output wire [7:0] dram_axi_m_axi_awlen, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWLOCK" *) - output wire dram_axi_m_axi_awlock, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWPROT" *) - output wire [2:0] dram_axi_m_axi_awprot, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWQOS" *) - output wire [3:0] dram_axi_m_axi_awqos, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWREADY" *) - input wire dram_axi_m_axi_awready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWSIZE" *) - output wire [2:0] dram_axi_m_axi_awsize, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi AWVALID" *) - output wire dram_axi_m_axi_awvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BID" *) - input wire [6:0] dram_axi_m_axi_bid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BREADY" *) - output wire dram_axi_m_axi_bready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BRESP" *) - input wire [1:0] dram_axi_m_axi_bresp, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi BVALID" *) - input wire dram_axi_m_axi_bvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RDATA" *) - input wire [63:0] dram_axi_m_axi_rdata, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RID" *) - input wire [6:0] dram_axi_m_axi_rid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RLAST" *) - input wire dram_axi_m_axi_rlast, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RREADY" *) - output wire dram_axi_m_axi_rready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RRESP" *) - input wire [1:0] dram_axi_m_axi_rresp, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi RVALID" *) - input wire dram_axi_m_axi_rvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WDATA" *) - output wire [63:0] dram_axi_m_axi_wdata, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WLAST" *) - output wire dram_axi_m_axi_wlast, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WREADY" *) - input wire dram_axi_m_axi_wready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WSTRB" *) - output wire [7:0] dram_axi_m_axi_wstrb, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 dram_axi WVALID" *) - output wire dram_axi_m_axi_wvalid, -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 dram_axi CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dram_axi, ASSOCIATED_BUSIF dram_axi, FREQ_HZ 50000000" *) - output wire dram_axi_m_aclk, -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) - output wire dram_axi_m_aresetn, - -// MASTER AXI PERIPHERAL - -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) - output wire [47:0] periph_axi_m_axi_araddr, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARBURST" *) - output wire [1:0] periph_axi_m_axi_arburst, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARCACHE" *) - output wire [3:0] periph_axi_m_axi_arcache, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARID" *) - output wire [1:0]periph_axi_m_axi_arid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARLEN" *) - output wire [7:0] periph_axi_m_axi_arlen, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARLOCK" *) - output wire periph_axi_m_axi_arlock, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARPROT" *) - output wire [2:0] periph_axi_m_axi_arprot, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARQOS" *) - output wire [3:0] periph_axi_m_axi_arqos, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARREADY" *) - input wire periph_axi_m_axi_arready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARSIZE" *) - output wire [2:0] periph_axi_m_axi_arsize, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m ARVALID" *) - output wire periph_axi_m_axi_arvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWADDR" *) - output wire [47:0] periph_axi_m_axi_awaddr, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWBURST" *) - output wire [1:0] periph_axi_m_axi_awburst, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWCACHE" *) - output wire [3:0] periph_axi_m_axi_awcache, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWID" *) - output wire [1:0] periph_axi_m_axi_awid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWLEN" *) - output wire [7:0] periph_axi_m_axi_awlen, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWLOCK" *) - output wire periph_axi_m_axi_awlock, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWPROT" *) - output wire [2:0] periph_axi_m_axi_awprot, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWQOS" *) - output wire [3:0] periph_axi_m_axi_awqos, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWREADY" *) - input wire periph_axi_m_axi_awready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWSIZE" *) - output wire [2:0] periph_axi_m_axi_awsize, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m AWVALID" *) - output wire periph_axi_m_axi_awvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BID" *) - input wire [1:0] periph_axi_m_axi_bid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BREADY" *) - output wire periph_axi_m_axi_bready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BRESP" *) - input wire [1:0] periph_axi_m_axi_bresp, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m BVALID" *) - input wire periph_axi_m_axi_bvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RDATA" *) - input wire [63:0] periph_axi_m_axi_rdata, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RID" *) - input wire [1:0] periph_axi_m_axi_rid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RLAST" *) - input wire periph_axi_m_axi_rlast, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RREADY" *) - output wire periph_axi_m_axi_rready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RRESP" *) - input wire [1:0] periph_axi_m_axi_rresp, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m RVALID" *) - input wire periph_axi_m_axi_rvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WDATA" *) - output wire [63:0] periph_axi_m_axi_wdata, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WLAST" *) - output wire periph_axi_m_axi_wlast, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WREADY" *) - input wire periph_axi_m_axi_wready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WSTRB" *) - output wire [7:0] periph_axi_m_axi_wstrb, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_m WVALID" *) - output wire periph_axi_m_axi_wvalid, -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 periph_axi_m CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, ASSOCIATED_BUSIF periph_axi_m, FREQ_HZ 500000000" *) - output wire periph_axi_m_aclk, -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 periph_axi_m RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME periph_axi_m, POLARITY ACTIVE_LOW" *) - output wire periph_axi_m_aresetn, - -// SLAVE AXI PERIPHERAL - -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARADDR" *) (* X_INTERFACE_PARAMETER = "FREQ_HZ 50000000" *) - input wire [47:0] periph_axi_s_axi_araddr, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARBURST" *) - input wire [1:0] periph_axi_s_axi_arburst, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARCACHE" *) - input wire [3:0] periph_axi_s_axi_arcache, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARID" *) - input wire [1:0]periph_axi_s_axi_arid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARLEN" *) - input wire [7:0] periph_axi_s_axi_arlen, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARLOCK" *) - input wire periph_axi_s_axi_arlock, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARPROT" *) - input wire [2:0] periph_axi_s_axi_arprot, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARQOS" *) - input wire [3:0] periph_axi_s_axi_arqos, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARREADY" *) - output wire periph_axi_s_axi_arready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARSIZE" *) - input wire [2:0] periph_axi_s_axi_arsize, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s ARVALID" *) - input wire periph_axi_s_axi_arvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWADDR" *) - input wire [47:0] periph_axi_s_axi_awaddr, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWBURST" *) - input wire [1:0] periph_axi_s_axi_awburst, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWCACHE" *) - input wire [3:0] periph_axi_s_axi_awcache, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWID" *) - input wire [1:0] periph_axi_s_axi_awid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWLEN" *) - input wire [7:0] periph_axi_s_axi_awlen, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWLOCK" *) - input wire periph_axi_s_axi_awlock, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWPROT" *) - input wire [2:0] periph_axi_s_axi_awprot, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWQOS" *) - input wire [3:0] periph_axi_s_axi_awqos, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWREADY" *) - output wire periph_axi_s_axi_awready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWSIZE" *) - input wire [2:0] periph_axi_s_axi_awsize, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s AWVALID" *) - input wire periph_axi_s_axi_awvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BID" *) - output wire [1:0] periph_axi_s_axi_bid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BREADY" *) - input wire periph_axi_s_axi_bready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BRESP" *) - output wire [1:0] periph_axi_s_axi_bresp, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s BVALID" *) - output wire periph_axi_s_axi_bvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RDATA" *) - output wire [63:0] periph_axi_s_axi_rdata, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RID" *) - output wire [1:0] periph_axi_s_axi_rid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RLAST" *) - output wire periph_axi_s_axi_rlast, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RREADY" *) - input wire periph_axi_s_axi_rready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RRESP" *) - output wire [1:0] periph_axi_s_axi_rresp, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s RVALID" *) - output wire periph_axi_s_axi_rvalid, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WDATA" *) - input wire [63:0] periph_axi_s_axi_wdata, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WLAST" *) - input wire periph_axi_s_axi_wlast, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WREADY" *) - output wire periph_axi_s_axi_wready, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WSTRB" *) - input wire [7:0] periph_axi_s_axi_wstrb, -(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 periph_axi_s WVALID" *) - input wire periph_axi_s_axi_wvalid - -); - - cheshire_top_xilinx #( - ) i_cheshire_top_xilinx ( - .cpu_reset(cpu_reset), - .clk_10(clk_10), - .clk_20(clk_20), - .clk_50(clk_50), - .clk_100(clk_100), - - .testmode_i (testmode_i ) , - .boot_mode_i (boot_mode_i ) , - - .gpio_i (gpio_i), - - .jtag_tck_i (jtag_tck_i ), - .jtag_tms_i (jtag_tms_i ), - .jtag_tdi_i (jtag_tdi_i ), - .jtag_tdo_o (jtag_tdo_o ), - .jtag_trst_ni(jtag_trst_ni ), - .jtag_vdd_o (jtag_vdd_o ), - .jtag_gnd_o (jtag_gnd_o ), - - .uart_tx_o(uart_tx_o), - .uart_rx_i(uart_rx_i), - - .dram_axi_m_aclk (dram_axi_m_aclk ), - .dram_axi_m_aresetn(dram_axi_m_aresetn), - - // Dram axi - - .dram_axi_m_axi_awid (dram_axi_m_axi_awid ), - .dram_axi_m_axi_awaddr (dram_axi_m_axi_awaddr ), - .dram_axi_m_axi_awlen (dram_axi_m_axi_awlen ), - .dram_axi_m_axi_awsize (dram_axi_m_axi_awsize ), - .dram_axi_m_axi_awburst(dram_axi_m_axi_awburst), - .dram_axi_m_axi_awlock (dram_axi_m_axi_awlock ), - .dram_axi_m_axi_awcache(dram_axi_m_axi_awcache), - .dram_axi_m_axi_awprot (dram_axi_m_axi_awprot ), - .dram_axi_m_axi_awqos (dram_axi_m_axi_awqos ), - .dram_axi_m_axi_awvalid(dram_axi_m_axi_awvalid), - .dram_axi_m_axi_awready(dram_axi_m_axi_awready), - - .dram_axi_m_axi_wdata (dram_axi_m_axi_wdata ), - .dram_axi_m_axi_wstrb (dram_axi_m_axi_wstrb ), - .dram_axi_m_axi_wlast (dram_axi_m_axi_wlast ), - .dram_axi_m_axi_wvalid(dram_axi_m_axi_wvalid), - .dram_axi_m_axi_wready(dram_axi_m_axi_wready), - - .dram_axi_m_axi_bready(dram_axi_m_axi_bready), - .dram_axi_m_axi_bid (dram_axi_m_axi_bid ), - .dram_axi_m_axi_bresp (dram_axi_m_axi_bresp ), - .dram_axi_m_axi_bvalid(dram_axi_m_axi_bvalid), - - .dram_axi_m_axi_arid (dram_axi_m_axi_arid ), - .dram_axi_m_axi_araddr (dram_axi_m_axi_araddr ), - .dram_axi_m_axi_arlen (dram_axi_m_axi_arlen ), - .dram_axi_m_axi_arsize (dram_axi_m_axi_arsize ), - .dram_axi_m_axi_arburst(dram_axi_m_axi_arburst), - .dram_axi_m_axi_arlock (dram_axi_m_axi_arlock ), - .dram_axi_m_axi_arcache(dram_axi_m_axi_arcache), - .dram_axi_m_axi_arprot (dram_axi_m_axi_arprot ), - .dram_axi_m_axi_arqos (dram_axi_m_axi_arqos ), - .dram_axi_m_axi_arvalid(dram_axi_m_axi_arvalid), - .dram_axi_m_axi_arready(dram_axi_m_axi_arready), - - .dram_axi_m_axi_rready(dram_axi_m_axi_rready), - .dram_axi_m_axi_rid (dram_axi_m_axi_rid ), - .dram_axi_m_axi_rdata (dram_axi_m_axi_rdata ), - .dram_axi_m_axi_rresp (dram_axi_m_axi_rresp ), - .dram_axi_m_axi_rlast (dram_axi_m_axi_rlast ), - .dram_axi_m_axi_rvalid(dram_axi_m_axi_rvalid), - - // Peripheral axi - - .periph_axi_m_aclk (periph_axi_m_aclk ), - .periph_axi_m_aresetn(periph_axi_m_aresetn), - - .periph_axi_m_axi_awid (periph_axi_m_axi_awid ), - .periph_axi_m_axi_awaddr (periph_axi_m_axi_awaddr ), - .periph_axi_m_axi_awlen (periph_axi_m_axi_awlen ), - .periph_axi_m_axi_awsize (periph_axi_m_axi_awsize ), - .periph_axi_m_axi_awburst(periph_axi_m_axi_awburst), - .periph_axi_m_axi_awlock (periph_axi_m_axi_awlock ), - .periph_axi_m_axi_awcache(periph_axi_m_axi_awcache), - .periph_axi_m_axi_awprot (periph_axi_m_axi_awprot ), - .periph_axi_m_axi_awqos (periph_axi_m_axi_awqos ), - .periph_axi_m_axi_awvalid(periph_axi_m_axi_awvalid), - .periph_axi_m_axi_awready(periph_axi_m_axi_awready), - - .periph_axi_m_axi_wdata (periph_axi_m_axi_wdata ), - .periph_axi_m_axi_wstrb (periph_axi_m_axi_wstrb ), - .periph_axi_m_axi_wlast (periph_axi_m_axi_wlast ), - .periph_axi_m_axi_wvalid(periph_axi_m_axi_wvalid), - .periph_axi_m_axi_wready(periph_axi_m_axi_wready), - - .periph_axi_m_axi_bready(periph_axi_m_axi_bready), - .periph_axi_m_axi_bid (periph_axi_m_axi_bid ), - .periph_axi_m_axi_bresp (periph_axi_m_axi_bresp ), - .periph_axi_m_axi_bvalid(periph_axi_m_axi_bvalid), - - .periph_axi_m_axi_arid (periph_axi_m_axi_arid ), - .periph_axi_m_axi_araddr (periph_axi_m_axi_araddr ), - .periph_axi_m_axi_arlen (periph_axi_m_axi_arlen ), - .periph_axi_m_axi_arsize (periph_axi_m_axi_arsize ), - .periph_axi_m_axi_arburst(periph_axi_m_axi_arburst), - .periph_axi_m_axi_arlock (periph_axi_m_axi_arlock ), - .periph_axi_m_axi_arcache(periph_axi_m_axi_arcache), - .periph_axi_m_axi_arprot (periph_axi_m_axi_arprot ), - .periph_axi_m_axi_arqos (periph_axi_m_axi_arqos ), - .periph_axi_m_axi_arvalid(periph_axi_m_axi_arvalid), - .periph_axi_m_axi_arready(periph_axi_m_axi_arready), - - .periph_axi_m_axi_rready(periph_axi_m_axi_rready), - .periph_axi_m_axi_rid (periph_axi_m_axi_rid ), - .periph_axi_m_axi_rdata (periph_axi_m_axi_rdata ), - .periph_axi_m_axi_rresp (periph_axi_m_axi_rresp ), - .periph_axi_m_axi_rlast (periph_axi_m_axi_rlast ), - .periph_axi_m_axi_rvalid(periph_axi_m_axi_rvalid), - - // Peripheral axi - - .periph_axi_s_axi_awid (periph_axi_s_axi_awid ), - .periph_axi_s_axi_awaddr (periph_axi_s_axi_awaddr ), - .periph_axi_s_axi_awlen (periph_axi_s_axi_awlen ), - .periph_axi_s_axi_awsize (periph_axi_s_axi_awsize ), - .periph_axi_s_axi_awburst(periph_axi_s_axi_awburst), - .periph_axi_s_axi_awlock (periph_axi_s_axi_awlock ), - .periph_axi_s_axi_awcache(periph_axi_s_axi_awcache), - .periph_axi_s_axi_awprot (periph_axi_s_axi_awprot ), - .periph_axi_s_axi_awqos (periph_axi_s_axi_awqos ), - .periph_axi_s_axi_awvalid(periph_axi_s_axi_awvalid), - .periph_axi_s_axi_awready(periph_axi_s_axi_awready), - - .periph_axi_s_axi_wdata (periph_axi_s_axi_wdata ), - .periph_axi_s_axi_wstrb (periph_axi_s_axi_wstrb ), - .periph_axi_s_axi_wlast (periph_axi_s_axi_wlast ), - .periph_axi_s_axi_wvalid(periph_axi_s_axi_wvalid), - .periph_axi_s_axi_wready(periph_axi_s_axi_wready), - - .periph_axi_s_axi_bready(periph_axi_s_axi_bready), - .periph_axi_s_axi_bid (periph_axi_s_axi_bid ), - .periph_axi_s_axi_bresp (periph_axi_s_axi_bresp ), - .periph_axi_s_axi_bvalid(periph_axi_s_axi_bvalid), - - .periph_axi_s_axi_arid (periph_axi_s_axi_arid ), - .periph_axi_s_axi_araddr (periph_axi_s_axi_araddr ), - .periph_axi_s_axi_arlen (periph_axi_s_axi_arlen ), - .periph_axi_s_axi_arsize (periph_axi_s_axi_arsize ), - .periph_axi_s_axi_arburst(periph_axi_s_axi_arburst), - .periph_axi_s_axi_arlock (periph_axi_s_axi_arlock ), - .periph_axi_s_axi_arcache(periph_axi_s_axi_arcache), - .periph_axi_s_axi_arprot (periph_axi_s_axi_arprot ), - .periph_axi_s_axi_arqos (periph_axi_s_axi_arqos ), - .periph_axi_s_axi_arvalid(periph_axi_s_axi_arvalid), - .periph_axi_s_axi_arready(periph_axi_s_axi_arready), - - .periph_axi_s_axi_rready(periph_axi_s_axi_rready), - .periph_axi_s_axi_rid (periph_axi_s_axi_rid ), - .periph_axi_s_axi_rdata (periph_axi_s_axi_rdata ), - .periph_axi_s_axi_rresp (periph_axi_s_axi_rresp ), - .periph_axi_s_axi_rlast (periph_axi_s_axi_rlast ), - .periph_axi_s_axi_rvalid(periph_axi_s_axi_rvalid) - ); - -endmodule diff --git a/target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv b/target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv deleted file mode 100644 index 157bea4e..00000000 --- a/target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv +++ /dev/null @@ -1,676 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Nicole Narr -// Christopher Reinwardt -// Cyril Koenig - -`include "axi/typedef.svh" -`include "cheshire/typedef.svh" - -module cheshire_top_xilinx - import cheshire_pkg::*; -#( -) ( - input logic cpu_reset, - - input logic clk_10, - input logic clk_20, - input logic clk_50, - input logic clk_100, - - input logic testmode_i, - input logic [1:0] boot_mode_i, - - input logic jtag_tck_i, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - input logic jtag_trst_ni, - output logic jtag_vdd_o, - output logic jtag_gnd_o, - - output logic uart_tx_o, - input logic uart_rx_i, - - // GPIOs will be used as interrupts, - input logic [31:0] gpio_i, - - // Dram axi - - output wire dram_axi_m_aclk, - output wire dram_axi_m_aresetn, - - output wire [6:0] dram_axi_m_axi_awid, - output wire [47:0] dram_axi_m_axi_awaddr, - output wire [7:0] dram_axi_m_axi_awlen, - output wire [2:0] dram_axi_m_axi_awsize, - output wire [1:0] dram_axi_m_axi_awburst, - output wire dram_axi_m_axi_awlock, - output wire [3:0] dram_axi_m_axi_awcache, - output wire [2:0] dram_axi_m_axi_awprot, - output wire [3:0] dram_axi_m_axi_awqos, - output wire dram_axi_m_axi_awvalid, - input wire dram_axi_m_axi_awready, - - output wire [63:0] dram_axi_m_axi_wdata, - output wire [7:0] dram_axi_m_axi_wstrb, - output wire dram_axi_m_axi_wlast, - output wire dram_axi_m_axi_wvalid, - input wire dram_axi_m_axi_wready, - - output wire dram_axi_m_axi_bready, - input wire [6:0] dram_axi_m_axi_bid, - input wire [1:0] dram_axi_m_axi_bresp, - input wire dram_axi_m_axi_bvalid, - - output wire [6:0]dram_axi_m_axi_arid, - output wire [47:0] dram_axi_m_axi_araddr, - output wire [7:0] dram_axi_m_axi_arlen, - output wire [2:0] dram_axi_m_axi_arsize, - output wire [1:0] dram_axi_m_axi_arburst, - output wire dram_axi_m_axi_arlock, - output wire [3:0] dram_axi_m_axi_arcache, - output wire [2:0] dram_axi_m_axi_arprot, - output wire [3:0] dram_axi_m_axi_arqos, - output wire dram_axi_m_axi_arvalid, - input wire dram_axi_m_axi_arready, - - output wire dram_axi_m_axi_rready, - input wire [6:0] dram_axi_m_axi_rid, - input wire [63:0] dram_axi_m_axi_rdata, - input wire [1:0] dram_axi_m_axi_rresp, - input wire dram_axi_m_axi_rlast, - input wire dram_axi_m_axi_rvalid, - - // Periph axi out - - output wire periph_axi_m_aclk, - output wire periph_axi_m_aresetn, - - output wire [1:0] periph_axi_m_axi_awid, - output wire [47:0] periph_axi_m_axi_awaddr, - output wire [7:0] periph_axi_m_axi_awlen, - output wire [2:0] periph_axi_m_axi_awsize, - output wire [1:0] periph_axi_m_axi_awburst, - output wire periph_axi_m_axi_awlock, - output wire [3:0] periph_axi_m_axi_awcache, - output wire [2:0] periph_axi_m_axi_awprot, - output wire [3:0] periph_axi_m_axi_awqos, - output wire periph_axi_m_axi_awvalid, - input wire periph_axi_m_axi_awready, - - output wire [63:0] periph_axi_m_axi_wdata, - output wire [7:0] periph_axi_m_axi_wstrb, - output wire periph_axi_m_axi_wlast, - output wire periph_axi_m_axi_wvalid, - input wire periph_axi_m_axi_wready, - - output wire periph_axi_m_axi_bready, - input wire [1:0] periph_axi_m_axi_bid, - input wire [1:0] periph_axi_m_axi_bresp, - input wire periph_axi_m_axi_bvalid, - - output wire [1:0]periph_axi_m_axi_arid, - output wire [47:0] periph_axi_m_axi_araddr, - output wire [7:0] periph_axi_m_axi_arlen, - output wire [2:0] periph_axi_m_axi_arsize, - output wire [1:0] periph_axi_m_axi_arburst, - output wire periph_axi_m_axi_arlock, - output wire [3:0] periph_axi_m_axi_arcache, - output wire [2:0] periph_axi_m_axi_arprot, - output wire [3:0] periph_axi_m_axi_arqos, - output wire periph_axi_m_axi_arvalid, - input wire periph_axi_m_axi_arready, - - output wire periph_axi_m_axi_rready, - input wire [1:0] periph_axi_m_axi_rid, - input wire [63:0] periph_axi_m_axi_rdata, - input wire [1:0] periph_axi_m_axi_rresp, - input wire periph_axi_m_axi_rlast, - input wire periph_axi_m_axi_rvalid, - - // Periph axi in - - input wire [1:0] periph_axi_s_axi_awid, - input wire [47:0] periph_axi_s_axi_awaddr, - input wire [7:0] periph_axi_s_axi_awlen, - input wire [2:0] periph_axi_s_axi_awsize, - input wire [1:0] periph_axi_s_axi_awburst, - input wire periph_axi_s_axi_awlock, - input wire [3:0] periph_axi_s_axi_awcache, - input wire [2:0] periph_axi_s_axi_awprot, - input wire [3:0] periph_axi_s_axi_awqos, - input wire periph_axi_s_axi_awvalid, - output wire periph_axi_s_axi_awready, - - input wire [63:0] periph_axi_s_axi_wdata, - input wire [7:0] periph_axi_s_axi_wstrb, - input wire periph_axi_s_axi_wlast, - input wire periph_axi_s_axi_wvalid, - output wire periph_axi_s_axi_wready, - - input wire periph_axi_s_axi_bready, - output wire [1:0] periph_axi_s_axi_bid, - output wire [1:0] periph_axi_s_axi_bresp, - output wire periph_axi_s_axi_bvalid, - - input wire [1:0]periph_axi_s_axi_arid, - input wire [47:0] periph_axi_s_axi_araddr, - input wire [7:0] periph_axi_s_axi_arlen, - input wire [2:0] periph_axi_s_axi_arsize, - input wire [1:0] periph_axi_s_axi_arburst, - input wire periph_axi_s_axi_arlock, - input wire [3:0] periph_axi_s_axi_arcache, - input wire [2:0] periph_axi_s_axi_arprot, - input wire [3:0] periph_axi_s_axi_arqos, - input wire periph_axi_s_axi_arvalid, - output wire periph_axi_s_axi_arready, - - input wire periph_axi_s_axi_rready, - output wire [1:0] periph_axi_s_axi_rid, - output wire [63:0] periph_axi_s_axi_rdata, - output wire [1:0] periph_axi_s_axi_rresp, - output wire periph_axi_s_axi_rlast, - output wire periph_axi_s_axi_rvalid - -); - - - // Configure cheshire for FPGA mapping - localparam cheshire_cfg_t FPGACfg = '{ - // CVA6 parameters - Cva6RASDepth : ariane_pkg::ArianeDefaultConfig.RASDepth, - Cva6BTBEntries : ariane_pkg::ArianeDefaultConfig.BTBEntries, - Cva6BHTEntries : ariane_pkg::ArianeDefaultConfig.BHTEntries, - Cva6NrPMPEntries : 0, - Cva6ExtCieLength : 'h2000_0000, - // Harts - NumCores : 1, - CoreMaxTxns : 8, - CoreMaxTxnsPerId : 4, - // Interrupts - NumExtIntrSyncs : 2, - // Interconnect - AddrWidth : 48, - AxiDataWidth : 64, - AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link - AxiMstIdWidth : 2, - AxiMaxMstTrans : 8, - AxiMaxSlvTrans : 8, - AxiUserAmoMsb : 1, - AxiUserAmoLsb : 0, - RegMaxReadTxns : 8, - RegMaxWriteTxns : 8, - RegAmoNumCuts : 1, - RegAmoPostCut : 1, - // RTC - RtcFreq : 1000000, - // Features - Bootrom : 1, - Uart : 1, - I2c : 1, - SpiHost : 1, - Gpio : 1, - Dma : 1, - SerialLink : 0, - Vga : 1, - // Debug - DbgIdCode : CheshireIdCode, - DbgMaxReqs : 4, - DbgMaxReadTxns : 4, - DbgMaxWriteTxns : 4, - DbgAmoNumCuts : 1, - DbgAmoPostCut : 1, - // LLC: 128 KiB, up to 2 GiB DRAM - LlcNotBypass : 1, - LlcSetAssoc : 8, - LlcNumLines : 256, - LlcNumBlocks : 8, - LlcMaxReadTxns : 8, - LlcMaxWriteTxns : 8, - LlcAmoNumCuts : 1, - LlcAmoPostCut : 1, - LlcOutConnect : 1, - LlcOutRegionStart : 'h8000_0000, - LlcOutRegionEnd : 'h1_0000_0000, - // VGA: RGB332 - VgaRedWidth : 5, - VgaGreenWidth : 6, - VgaBlueWidth : 5, - VgaHCountWidth : 24, // TODO: Default is 32; is this needed? - VgaVCountWidth : 24, // TODO: See above - // Serial Link: map other chip's lower 32bit to 'h1_000_0000 - SlinkMaxTxnsPerId : 4, - SlinkMaxUniqIds : 4, - SlinkMaxClkDiv : 1024, - SlinkRegionStart : 'h1_0000_0000, - SlinkRegionEnd : 'h2_0000_0000, - SlinkTxAddrMask : 'hFFFF_FFFF, - SlinkTxAddrDomain : 'h0000_0000, - SlinkUserAmoBit : 1, // Upper atomics bit for serial link - // DMA config - DmaConfMaxReadTxns : 4, - DmaConfMaxWriteTxns : 4, - DmaConfAmoNumCuts : 1, - DmaConfAmoPostCut : 1, - DmaConfEnableTwoD : 1, - DmaNumAxInFlight : 16, - DmaMemSysDepth : 8, - DmaJobFifoDepth : 2, - DmaRAWCouplingAvail : 1, - // GPIOs - GpioInputSyncs : 1, - // All non-set values should be zero - default: '0 - }; - - localparam cheshire_cfg_t CheshireFPGACfg = FPGACfg; - `CHESHIRE_TYPEDEF_ALL(, CheshireFPGACfg) - - /////////////////////////// - // Clk reset definitions // - /////////////////////////// - - logic cpu_resetn; - assign cpu_resetn = ~cpu_reset; - logic sys_rst; - - wire soc_clk; - wire rst_n; - - /////////////////// - // GPIOs // - /////////////////// - - // Give VDD and GND to JTAG - assign jtag_vdd_o = '1; - assign jtag_gnd_o = '0; - - ////////////////// - // Clock Wizard // - ////////////////// - - localparam rtc_clk_divider = 4; - assign soc_clk = clk_50; - - ///////////////////// - // Reset Generator // - ///////////////////// - - rstgen i_rstgen_main ( - .clk_i ( soc_clk ), - .rst_ni ( ~sys_rst ), - .test_mode_i ( testmode_i ), - .rst_no ( rst_n ), - .init_no ( ) // keep open - ); - - /////////////////// - // VIOs // - /////////////////// - - logic [1:0] boot_mode; - - assign sys_rst = cpu_reset; - assign boot_mode = boot_mode_i; - - ///////////////////////// - // "RTC" Clock Divider // - ///////////////////////// - - (* dont_touch = "yes" *) logic rtc_clk_d, rtc_clk_q; - logic [4:0] counter_d, counter_q; - - // Divide clk_10 => 1 MHz RTC Clock - always_comb begin - counter_d = counter_q + 1; - rtc_clk_d = rtc_clk_q; - - if(counter_q == rtc_clk_divider) begin - counter_d = 5'b0; - rtc_clk_d = ~rtc_clk_q; - end - end - - always_ff @(posedge clk_10, negedge rst_n) begin - if(~rst_n) begin - counter_q <= 5'b0; - rtc_clk_q <= 0; - end else begin - counter_q <= counter_d; - rtc_clk_q <= rtc_clk_d; - end - end - - /////////////////// - // LLC interface // - /////////////////// - - // Axi interface - axi_llc_req_t llc_req; - axi_llc_rsp_t llc_rsp; - - assign dram_axi_m_aclk = soc_clk; - assign dram_axi_m_aresetn = rst_n; - - assign dram_axi_m_axi_awid = llc_req.aw.id; - assign dram_axi_m_axi_awaddr = llc_req.aw.addr; - assign dram_axi_m_axi_awlen = llc_req.aw.len; - assign dram_axi_m_axi_awsize = llc_req.aw.size; - assign dram_axi_m_axi_awburst = llc_req.aw.burst; - assign dram_axi_m_axi_awlock = llc_req.aw.lock; - assign dram_axi_m_axi_awcache = llc_req.aw.cache; - assign dram_axi_m_axi_awprot = llc_req.aw.prot; - assign dram_axi_m_axi_awqos = llc_req.aw.qos; - assign dram_axi_m_axi_awvalid = llc_req.aw_valid; - assign llc_rsp.aw_ready = dram_axi_m_axi_awready; - - assign dram_axi_m_axi_wdata = llc_req.w.data; - assign dram_axi_m_axi_wstrb = llc_req.w.strb; - assign dram_axi_m_axi_wlast = llc_req.w.last; - assign dram_axi_m_axi_wvalid = llc_req.w_valid; - assign llc_rsp.w_ready = dram_axi_m_axi_wready; - - assign dram_axi_m_axi_bready = llc_req.b_ready; - assign llc_rsp.b.id = dram_axi_m_axi_bid; - assign llc_rsp.b.resp = dram_axi_m_axi_bresp; - assign llc_rsp.b_valid = dram_axi_m_axi_bvalid; - - assign dram_axi_m_axi_arid = llc_req.ar.id; - assign dram_axi_m_axi_araddr = llc_req.ar.addr; - assign dram_axi_m_axi_arlen = llc_req.ar.len; - assign dram_axi_m_axi_arsize = llc_req.ar.size; - assign dram_axi_m_axi_arburst = llc_req.ar.burst; - assign dram_axi_m_axi_arlock = llc_req.ar.lock; - assign dram_axi_m_axi_arcache = llc_req.ar.cache; - assign dram_axi_m_axi_arprot = llc_req.ar.prot; - assign dram_axi_m_axi_arqos = llc_req.ar.qos; - assign dram_axi_m_axi_arvalid = llc_req.ar_valid; - assign llc_rsp.ar_ready = dram_axi_m_axi_arready; - - assign dram_axi_m_axi_rready = llc_req.r_ready; - assign llc_rsp.r.id = dram_axi_m_axi_rid; - assign llc_rsp.r.data = dram_axi_m_axi_rdata; - assign llc_rsp.r.resp = dram_axi_m_axi_rresp; - assign llc_rsp.r.last = dram_axi_m_axi_rlast; - assign llc_rsp.r_valid = dram_axi_m_axi_rvalid; - - ///////////////////////////////// - // Serial Link to block design // - ///////////////////////////////// - - // Serial link interface - logic [SlinkNumChan-1:0] slink_clk_soc_periph; - logic [SlinkNumChan-1:0] slink_clk_periph_soc; - logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_soc_periph; - logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_periph_soc; - - axi_mst_req_t periph_soc_bd_req, periph_bd_soc_req; - axi_mst_rsp_t periph_soc_bd_rsp, periph_bd_soc_rsp; - - serial_link #( - .axi_req_t ( axi_mst_req_t ), - .axi_rsp_t ( axi_mst_rsp_t ), - .cfg_req_t ( reg_req_t ), - .cfg_rsp_t ( reg_rsp_t ), - .aw_chan_t ( axi_mst_aw_chan_t ), - .ar_chan_t ( axi_mst_ar_chan_t ), - .r_chan_t ( axi_mst_r_chan_t ), - .w_chan_t ( axi_mst_w_chan_t ), - .b_chan_t ( axi_mst_b_chan_t ), - .hw2reg_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t ), - .reg2hw_t ( serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t ), - .NumChannels ( SlinkNumChan ), - .NumLanes ( SlinkNumLanes ), - .MaxClkDiv ( SlinkMaxClkDiv ) - ) i_serial_link ( - .clk_i ( host_clk ), - .rst_ni ( rst_n ), - .clk_sl_i ( host_clk ), - .rst_sl_ni ( rst_n ), - .clk_reg_i ( host_clk ), - .rst_reg_ni ( rst_n ), - .testmode_i ( testmode_i ), - .axi_in_req_i ( periph_bd_soc_req ), - .axi_in_rsp_o ( periph_bd_soc_rsp ), - .axi_out_req_o ( periph_soc_bd_req ), - .axi_out_rsp_i ( periph_soc_bd_rsp ), - .cfg_req_i ( '0 ), - .cfg_rsp_o ( ), - .ddr_rcv_clk_i ( slink_clk_soc_periph ), - .ddr_rcv_clk_o ( slink_clk_periph_soc ), - .ddr_i ( slink_soc_periph ), - .ddr_o ( slink_periph_soc ), - .isolated_i ( '0 ), - .isolate_o ( ), - .clk_ena_o ( ), - .reset_no ( ) - ); - - // AXI periph soc to block design - - assign periph_axi_m_aclk = soc_clk; - assign periph_axi_m_aresetn = rst_n; - - assign periph_axi_m_axi_awid = periph_soc_bd_req.aw.id; - assign periph_axi_m_axi_awaddr = periph_soc_bd_req.aw.addr; - assign periph_axi_m_axi_awlen = periph_soc_bd_req.aw.len; - assign periph_axi_m_axi_awsize = periph_soc_bd_req.aw.size; - assign periph_axi_m_axi_awburst = periph_soc_bd_req.aw.burst; - assign periph_axi_m_axi_awlock = periph_soc_bd_req.aw.lock; - assign periph_axi_m_axi_awcache = periph_soc_bd_req.aw.cache; - assign periph_axi_m_axi_awprot = periph_soc_bd_req.aw.prot; - assign periph_axi_m_axi_awqos = periph_soc_bd_req.aw.qos; - assign periph_axi_m_axi_awvalid = periph_soc_bd_req.aw_valid; - assign periph_soc_bd_rsp.aw_ready = periph_axi_m_axi_awready; - - assign periph_axi_m_axi_wdata = periph_soc_bd_req.w.data; - assign periph_axi_m_axi_wstrb = periph_soc_bd_req.w.strb; - assign periph_axi_m_axi_wlast = periph_soc_bd_req.w.last; - assign periph_axi_m_axi_wvalid = periph_soc_bd_req.w_valid; - assign periph_soc_bd_rsp.w_ready = periph_axi_m_axi_wready; - - assign periph_axi_m_axi_bready = periph_soc_bd_req.b_ready; - assign periph_soc_bd_rsp.b.id = periph_axi_m_axi_bid; - assign periph_soc_bd_rsp.b.resp = periph_axi_m_axi_bresp; - assign periph_soc_bd_rsp.b_valid = periph_axi_m_axi_bvalid; - - assign periph_axi_m_axi_arid = periph_soc_bd_req.ar.id; - assign periph_axi_m_axi_araddr = periph_soc_bd_req.ar.addr; - assign periph_axi_m_axi_arlen = periph_soc_bd_req.ar.len; - assign periph_axi_m_axi_arsize = periph_soc_bd_req.ar.size; - assign periph_axi_m_axi_arburst = periph_soc_bd_req.ar.burst; - assign periph_axi_m_axi_arlock = periph_soc_bd_req.ar.lock; - assign periph_axi_m_axi_arcache = periph_soc_bd_req.ar.cache; - assign periph_axi_m_axi_arprot = periph_soc_bd_req.ar.prot; - assign periph_axi_m_axi_arqos = periph_soc_bd_req.ar.qos; - assign periph_axi_m_axi_arvalid = periph_soc_bd_req.ar_valid; - assign periph_soc_bd_rsp.ar_ready = periph_axi_m_axi_arready; - - assign periph_axi_m_axi_rready = periph_soc_bd_req.r_ready; - assign periph_soc_bd_rsp.r.id = periph_axi_m_axi_rid; - assign periph_soc_bd_rsp.r.data = periph_axi_m_axi_rdata; - assign periph_soc_bd_rsp.r.resp = periph_axi_m_axi_rresp; - assign periph_soc_bd_rsp.r.last = periph_axi_m_axi_rlast; - assign periph_soc_bd_rsp.r_valid = periph_axi_m_axi_rvalid; - - // AXI periph block design to soc - - // periph_axi_s_aclk unused (assumed already synch with soc_clk) - // periph_axi_s_aresetn ubused (assumed already synch with reset) - - assign periph_bd_soc_req.aw.id = periph_axi_s_axi_awid ; - assign periph_bd_soc_req.aw.addr = periph_axi_s_axi_awaddr ; - assign periph_bd_soc_req.aw.len = periph_axi_s_axi_awlen ; - assign periph_bd_soc_req.aw.size = periph_axi_s_axi_awsize ; - - assign periph_bd_soc_req.aw.burst = periph_axi_s_axi_awburst ; - assign periph_bd_soc_req.aw.lock = periph_axi_s_axi_awlock ; - assign periph_bd_soc_req.aw.cache = periph_axi_s_axi_awcache ; - assign periph_bd_soc_req.aw.prot = periph_axi_s_axi_awprot ; - assign periph_bd_soc_req.aw.qos = periph_axi_s_axi_awqos ; - assign periph_bd_soc_req.aw_valid = periph_axi_s_axi_awvalid ; - assign periph_axi_s_axi_awready = periph_bd_soc_rsp.aw_ready; - - assign periph_bd_soc_req.w.data = periph_axi_s_axi_wdata ; - assign periph_bd_soc_req.w.strb = periph_axi_s_axi_wstrb ; - assign periph_bd_soc_req.w.last = periph_axi_s_axi_wlast ; - assign periph_bd_soc_req.w_valid = periph_axi_s_axi_wvalid ; - assign periph_axi_s_axi_wready = periph_bd_soc_rsp.w_ready ; - - assign periph_bd_soc_req.b_ready = periph_axi_s_axi_bready ; - assign periph_axi_s_axi_bid = periph_bd_soc_rsp.b.id ; - assign periph_axi_s_axi_bresp = periph_bd_soc_rsp.b.resp ; - assign periph_axi_s_axi_bvalid = periph_bd_soc_rsp.b_valid ; - - assign periph_bd_soc_req.ar.id = periph_axi_s_axi_arid ; - assign periph_bd_soc_req.ar.addr = periph_axi_s_axi_araddr ; - assign periph_bd_soc_req.ar.len = periph_axi_s_axi_arlen ; - assign periph_bd_soc_req.ar.size = periph_axi_s_axi_arsize ; - assign periph_bd_soc_req.ar.burst = periph_axi_s_axi_arburst ; - assign periph_bd_soc_req.ar.lock = periph_axi_s_axi_arlock ; - assign periph_bd_soc_req.ar.cache = periph_axi_s_axi_arcache ; - assign periph_bd_soc_req.ar.prot = periph_axi_s_axi_arprot ; - assign periph_bd_soc_req.ar.qos = periph_axi_s_axi_arqos ; - assign periph_bd_soc_req.ar_valid = periph_axi_s_axi_arvalid ; - assign periph_axi_s_axi_arready = periph_bd_soc_rsp.ar_ready ; - - assign periph_bd_soc_req.r_ready = periph_axi_s_axi_rready ; - assign periph_axi_s_axi_rid = periph_bd_soc_rsp.r.id ; - assign periph_axi_s_axi_rdata = periph_bd_soc_rsp.r.data ; - assign periph_axi_s_axi_rresp = periph_bd_soc_rsp.r.resp ; - assign periph_axi_s_axi_rlast = periph_bd_soc_rsp.r.last ; - assign periph_axi_s_axi_rvalid = periph_bd_soc_rsp.r_valid ; - - ////////////////// - // SPI Adaption // - ////////////////// - - logic spi_sck_soc; - logic [1:0] spi_cs_soc; - logic [3:0] spi_sd_soc_out; - logic [3:0] spi_sd_soc_in; - - logic spi_sck_en; - logic [1:0] spi_cs_en; - logic [3:0] spi_sd_en; - - ////////////////// - // QSPI // - ////////////////// - - logic qspi_clk; - logic qspi_clk_ts; - logic [3:0] qspi_dqi; - logic [3:0] qspi_dqo_ts; - logic [3:0] qspi_dqo; - logic [SpihNumCs-1:0] qspi_cs_b; - logic [SpihNumCs-1:0] qspi_cs_b_ts; - - assign qspi_clk = spi_sck_soc; - assign qspi_cs_b = spi_cs_soc; - assign qspi_dqo = spi_sd_soc_out; - assign spi_sd_soc_in = qspi_dqi; - // Tristate - Enable - assign qspi_clk_ts = ~spi_sck_en; - assign qspi_cs_b_ts = ~spi_cs_en; - assign qspi_dqo_ts = ~spi_sd_en; - - // On VCU128/ZCU102, SPI ports are not directly available - STARTUPE3 #( - .PROG_USR("FALSE"), - .SIM_CCLK_FREQ(0.0) - ) - STARTUPE3_inst ( - .CFGCLK (), - .CFGMCLK (), - .DI (qspi_dqi), - .EOS (), - .PREQ (), - .DO (qspi_dqo), - .DTS (qspi_dqo_ts), - .FCSBO (qspi_cs_b[1]), - .FCSBTS (qspi_cs_b_ts[1]), - .GSR (1'b0), - .GTS (1'b0), - .KEYCLEARB (1'b1), - .PACK (1'b0), - .USRCCLKO (qspi_clk), - .USRCCLKTS (qspi_clk_ts), - .USRDONEO (1'b1), - .USRDONETS (1'b1) - ); - - ////////////////// - // Cheshire SoC // - ////////////////// - - cheshire_soc #( - .Cfg ( FPGACfg ), - .ExtHartinfo ( '0 ), - .axi_ext_llc_req_t ( axi_llc_req_t ), - .axi_ext_llc_rsp_t ( axi_llc_rsp_t ), - .axi_ext_mst_req_t ( axi_mst_req_t ), - .axi_ext_mst_rsp_t ( axi_mst_rsp_t ), - .axi_ext_slv_req_t ( axi_slv_req_t ), - .axi_ext_slv_rsp_t ( axi_slv_rsp_t ), - .reg_ext_req_t ( reg_req_t ), - .reg_ext_rsp_t ( reg_req_t ) - ) i_cheshire_soc ( - .clk_i ( soc_clk ), - .rst_ni ( rst_n ), - .test_mode_i ( testmode_i ), - .boot_mode_i ( boot_mode ), - .rtc_i ( rtc_clk_q ), - .axi_llc_mst_req_o ( llc_req ), - .axi_llc_mst_rsp_i ( llc_rsp ), - .axi_ext_mst_req_i ( '0 ), - .axi_ext_mst_rsp_o ( ), - .axi_ext_slv_req_o ( ), - .axi_ext_slv_rsp_i ( '0 ), - .reg_ext_slv_req_o ( ), - .reg_ext_slv_rsp_i ( '0 ), - .intr_ext_i ( '0 ), - .intr_ext_o ( ), - .xeip_ext_o ( ), - .mtip_ext_o ( ), - .msip_ext_o ( ), - .dbg_active_o ( ), - .dbg_ext_req_o ( ), - .dbg_ext_unavail_i ( '0 ), - .slink_i ( slink_periph_soc ), - .slink_o ( slink_soc_periph ), - .slink_rcv_clk_i ( slink_clk_periph_soc ), - .slink_rcv_clk_o ( slink_clk_soc_periph ), - .jtag_tck_i, - .jtag_trst_ni, - .jtag_tms_i, - .jtag_tdi_i, - .jtag_tdo_o, - // TODO: connect to the tdo pad - .jtag_tdo_oe_o ( ), - .i2c_sda_o ( ), - .i2c_sda_i ( '0 ), - .i2c_sda_en_o ( ), - .i2c_scl_o ( ), - .i2c_scl_i ( '0 ), - .i2c_scl_en_o ( ), - .spih_sck_o ( spi_sck_soc ), - .spih_sck_en_o ( spi_sck_en ), - .spih_csb_o ( spi_cs_soc ), - .spih_csb_en_o ( spi_cs_en ), - .spih_sd_o ( spi_sd_soc_out ), - .spih_sd_en_o ( spi_sd_en ), - .spih_sd_i ( spi_sd_soc_in ), - .vga_hsync_o ( ), - .vga_vsync_o ( ), - .vga_red_o ( ), - .vga_green_o ( ), - .vga_blue_o ( ), - .uart_tx_o, - .uart_rx_i - ); - -endmodule diff --git a/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc b/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc deleted file mode 100644 index ae035065..00000000 --- a/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/cheshire.xdc +++ /dev/null @@ -1,93 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Nicole Narr -# Christopher Reinwardt -# Cyril Koenig - -##################### -# Timing Parameters # -##################### - -# 10 MHz (max) JTAG clock -set JTAG_TCK 100.0 - -# UART speed is at most 5 Mb/s -set UART_IO_SPEED 200.0 - -########## -# Clocks # -########## - -# Clk_wiz clocks are named clk_(100,50,20,10)_xlnx_clk_wiz -# They are on pins : i_xlnx_clk_wiz/inst/mmcme4_adv_inst/CLKOUT(0,1,2,3) - -# System Clock -# [see in board.xdc] - -# JTAG Clock -create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] -set_input_jitter clk_jtag 1.000 - -########## -# BUFG # -########## - -# JTAG are on non clock capable GPIOs (if not using BSCANE) -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] - -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset*]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset*]] - -# Remove avoid tc_clk_mux2 to use global clock routing -set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] -set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux -set_property CLOCK_BUFFER_TYPE NONE $all_in_mux - -################ -# Clock Groups # -################ - -# JTAG Clock is asynchronous to all other clocks -set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} - -######## -# JTAG # -######## - -set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] -set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] - -set_output_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports jtag_tdo_o] -set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_tdo_o] - -set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK -set_false_path -hold -from [get_ports jtag_trst_ni] - -######## -# UART # -######## - -set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] -set_false_path -hold -from [get_ports uart_rx_i] - -set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] -set_false_path -hold -to [get_ports uart_tx_o] - -######## -# CDCs # -######## - -# Disable hold checks -set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}] - -# src false path -set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] -# dst false path -set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] - -# Limit datapath delay -# [see in board.xdc] diff --git a/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/genesys2.xdc b/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/genesys2.xdc deleted file mode 100644 index ef635363..00000000 --- a/target/xilinx/flavor_vanilla/cheshire.srcs/constrs_1/imports/constraints/genesys2.xdc +++ /dev/null @@ -1,540 +0,0 @@ -############################## -# BOARD SPECIFIC CONSTRAINTS # -############################## - -##################### -# Timing Parameters # -##################### - -# 50 MHz SoC clock -create_generated_clock -name soc_clk -divide_by 1 -source [get_pins i_xlnx_clk_wiz/inst/mmcm_adv_inst/CLKOUT1] [get_nets soc_clk] -set soc_clk soc_clk -set SOC_TCK 20.0 - -# I2C High-speed mode is 3.2 Mb/s -set I2C_IO_SPEED 312.5 - -########## -# Basics # -########## - -# Testmode is set to 0 during normal use -set_case_analysis 0 [get_ports testmode_i] - -############# -# Sys clock # -############# - -# 200 MHz ref clock -set SYS_TCK 5 -create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] - -############# -# Mig clock # -############# - -# Dram axi clock : 200 MHz -set MIG_TCK 5 -create_generated_clock -source [get_pins i_dram_wrapper/i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT] \ - -divide_by 1 -add -master_clock clk_pll_i -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk] -# Aynch reset in -set MIG_RST_I [get_pin i_dram_wrapper/i_dram/aresetn] -set_false_path -hold -setup -through $MIG_RST_I -# Synch reset out -set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk] -set_false_path -hold -through $MIG_RST_O -set_max_delay -through $MIG_RST_O $MIG_TCK - -######## -# CDCs # -######## - -set_max_delay -datapath \ - -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK - -set_max_delay -datapath \ - -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ - -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK - - -####### -# VGA # -####### - -set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports vga*] -set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*] - -############ -# Switches # -############ - -set_input_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* testmode_i}] -set_input_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* testmode_i}] - -set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports fan_pwm] -set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports fan_pwm] - -set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* testmode_i}] -set_false_path -hold -from [get_ports {boot_mode* fan_sw* testmode_i}] - -set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] -set_false_path -hold -to [get_ports fan_pwm] - -######## -# SPIM # -######## - -set_input_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_input_delay -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_output_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] -set_output_delay -max -clock $soc_clk [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] - -####### -# I2C # -####### - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] - -################################################################################# - -############### -# ASSIGN PINS # -############### - -## Clock Signal -set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n -set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p - -## Buttons -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc -#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd -#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl -#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr -#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu -set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn - -## LEDs -#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0] -#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1] -#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2] -#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7] - -## Switches -set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] -set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[1] }]; #IO_25_16 Sch=sw[1] -set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[0] }]; #IO_L19P_T3_16 Sch=sw[2] -set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] -set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] -set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] -#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { testmode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] - -## USB HIDs For Both Mouse and Keyboard -#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0] -#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0] - -## UART -set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L1P_T0_12 Sch=uart_rx_out -set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_0_12 Sch=uart_tx_in - -## SD Card -set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd_i }]; #IO_L8N_T1_D12_14 Sch=sd_cd -set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd_o }]; #IO_L7N_T1_D10_14 Sch=sd_cmd -set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0] -set_property -dict { PACKAGE_PIN R30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[1] }]; #IO_L9P_T1_DQS_14 Sch=sd_dat[1] -set_property -dict { PACKAGE_PIN P29 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[2] }]; #IO_L7P_T1_D09_14 Sch=sd_dat[2] -set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[3] }]; #IO_L9N_T1_DQS_D13_14 Sch=sd_dat[3] -set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset -set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk - -## Audio Codec -#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata -#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0] -#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1] -#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk -#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata -#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk -#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk -#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl -#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda - -## Ethernet -#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb -#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n -#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb -#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk -#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl -#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0] -#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1] -#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2] -#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3] -#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk -#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0] -#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1] -#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2] -#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3] -#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en - -## VGA Connector -set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] -set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] -set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] -set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] -set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] - -set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] -set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] -set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] -set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] -set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] - -set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] -set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] -set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] -set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] -set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] - -set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs -set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs - -## HDMI in -#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec -#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_clk_n -#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L14P_T2_SRCC_13 Sch=hdmi_rx_clk_p -#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_hpa -#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17P_T2_13 Sch=hdmi_rx_scl -#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_13 Sch=hdmi_rx_sda -#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0] -#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0] -#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L21N_T3_DQS_13 Sch=hdmi_rx_n[1] -#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L21P_T3_DQS_13 Sch=hdmi_rx_p[1] -#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[2] -#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[2] - -## HDMI out -#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L1N_T0_12 Sch=hdmi_tx_cec -#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L6N_T0_VREF_12 Sch=hdmi_tx_clk_n -#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L6P_T0_12 Sch=hdmi_tx_clk_p -#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_tx_hpd -#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L23N_T3_13 Sch=hdmi_tx_scl -#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L23P_T3_13 Sch=hdmi_tx_sda -#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_12 Sch=hdmi_tx_n[0] -#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_12 Sch=hdmi_tx_p[0] -#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L4N_T0_12 Sch=hdmi_tx_n[1] -#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L4P_T0_12 Sch=hdmi_tx_p[1] -#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L7N_T1_12 Sch=hdmi_tx_n[2] -#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L7P_T1_12 Sch=hdmi_tx_p[2] - -## OLED Display -#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { oled_dc }]; #IO_L18N_T2_32 Sch=oled_dc -#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { oled_res }]; #IO_L18P_T2_32 Sch=oled_res -#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { oled_sclk }]; #IO_L12P_T1_MRCC_32 Sch=oled_sclk -#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { oled_sdin }]; #IO_L24N_T3_32 Sch=oled_sdin -#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_L3P_T0_DQS_12 Sch=oled_vbat -#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { oled_vdd }]; #IO_L12N_T1_MRCC_32 Sch=oled_vdd - -## PMOD Header JA -#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1] -#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1] -#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2] -#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2] -#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3] -#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] -#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] -#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] - -## PMOD Header JB -#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1] -#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1] -#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2] -#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2] -#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3] -#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3] -#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4] -#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4] - -## PMOD Header JC -#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L19P_T3_13 Sch=jc[1] -#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20P_T3_13 Sch=jc[2] -#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L18N_T2_13 Sch=jc[3] -#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15P_T2_DQS_13 Sch=jc[4] -#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L19N_T3_VREF_13 Sch=jc[7] -#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L18P_T2_13 Sch=jc[8] -#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L15N_T2_DQS_13 Sch=jc[9] -#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_13 Sch=jc[10] - -## PMOD Header JD -#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1] -#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2] -#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3] -#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4] -#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { spi_sck_o }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7] -#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { spi_cs_o }]; #IO_L1P_T0_13 Sch=jd[8] -#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { spi_mosi_o }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9] -#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { spi_miso_i }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10] - -## XADC Header -#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xadc0r_n -#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xadc0r_p -#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xadc1r_n -#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xadc1r_p -#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xadc8r_n -#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xadc8r_p -#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L4N_T0_AD9N_15 Sch=xadc9r_n -#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L4P_T0_AD9P_15 Sch=xadc9r_p - -## FMC -#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { FMC_CLK_DIR }]; #IO_L10N_T1_13 Sch=fmc_clk_dir -#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_17 Sch=fmc_clk0_m2c_n -#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_17 Sch=fmc_clk0_m2c_p -#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L14N_T2_SRCC_16 Sch=fmc_clk1_m2c_n -#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L14P_T2_SRCC_16 Sch=fmc_clk1_m2c_p -#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_N[2] }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2] -#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_P[2] }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2] -#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[00] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_ha_n[00] -#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[00] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_ha_p[00] -#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[01] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_ha_n[01] -#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[01] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_ha_p[01] -#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[02] }]; #IO_L22N_T3_A16_15 Sch=fmc_ha_n[02] -#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[02] }]; #IO_L22P_T3_A17_15 Sch=fmc_ha_p[02] -#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[03] }]; #IO_L18N_T2_A23_15 Sch=fmc_ha_n[03] -#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[03] }]; #IO_L18P_T2_A24_15 Sch=fmc_ha_p[03] -#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[04] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_ha_n[04] -#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[04] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_ha_p[04] -#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[05] }]; #IO_L7N_T1_AD10N_15 Sch=fmc_ha_n[05] -#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[05] }]; #IO_L7P_T1_AD10P_15 Sch=fmc_ha_p[05] -#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[06] }]; #IO_L17N_T2_A25_15 Sch=fmc_ha_n[06] -#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[06] }]; #IO_L17P_T2_A26_15 Sch=fmc_ha_p[06] -#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[07] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_ha_n[07] -#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[07] }]; #IO_L15P_T2_DQS_15 Sch=fmc_ha_p[07] -#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[08] }]; #IO_L8N_T1_AD3N_15 Sch=fmc_ha_n[08] -#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[08] }]; #IO_L8P_T1_AD3P_15 Sch=fmc_ha_p[08] -#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[09] }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fmc_ha_n[09] -#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[09] }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fmc_ha_p[09] -#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[10] }]; #IO_L20N_T3_A19_15 Sch=fmc_ha_n[10] -#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[10] }]; #IO_L20P_T3_A20_15 Sch=fmc_ha_p[10] -#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[11] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_ha_n[11] -#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[11] }]; #IO_L21P_T3_DQS_15 Sch=fmc_ha_p[11] -#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[12] }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=fmc_ha_n[12] -#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[12] }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=fmc_ha_p[12] -#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[13] }]; #IO_L10N_T1_AD4N_15 Sch=fmc_ha_n[13] -#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[13] }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] -#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[14] }]; #IO_L16N_T2_A27_15 Sch=fmc_ha_n[14] -#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[14] }]; #IO_L16P_T2_A28_15 Sch=fmc_ha_p[14] -#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[15] }]; #IO_L5N_T0_AD2N_15 Sch=fmc_ha_n[15] -#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[15] }]; #IO_L5P_T0_AD2P_15 Sch=fmc_ha_p[15] -#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[16] }]; #IO_L24N_T3_RS0_15 Sch=fmc_ha_n[16] -#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[16] }]; #IO_L24P_T3_RS1_15 Sch=fmc_ha_p[16] -#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[17] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_ha_n[17] -#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[17] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_ha_p[17] -#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[18] }]; #IO_L14N_T2_SRCC_17 Sch=fmc_ha_n[18] -#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[18] }]; #IO_L14P_T2_SRCC_17 Sch=fmc_ha_p[18] -#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[19] }]; #IO_L22N_T3_16 Sch=fmc_ha_n[19] -#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[19] }]; #IO_L22P_T3_16 Sch=fmc_ha_p[19] -#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[20] }]; #IO_L21N_T3_DQS_16 Sch=fmc_ha_n[20] -#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[20] }]; #IO_L21P_T3_DQS_16 Sch=fmc_ha_p[20] -#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[21] }]; #IO_L20N_T3_16 Sch=fmc_ha_n[21] -#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[21] }]; #IO_L20P_T3_16 Sch=fmc_ha_p[21] -#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[22] }]; #IO_L8N_T1_17 Sch=fmc_ha_n[22] -#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[22] }]; #IO_L8P_T1_17 Sch=fmc_ha_p[22] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[23] }]; #IO_L16N_T2_17 Sch=fmc_ha_n[23] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[23] }]; #IO_L16P_T2_17 Sch=fmc_ha_p[23] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[00] }]; #IO_L12N_T1_MRCC_18 Sch=fmc_hb_n[00] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[00] }]; #IO_L12P_T1_MRCC_18 Sch=fmc_hb_p[00] -#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[01] }]; #IO_L7N_T1_18 Sch=fmc_hb_n[01] -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[01] }]; #IO_L7P_T1_18 Sch=fmc_hb_p[01] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[02] }]; #IO_L2N_T0_18 Sch=fmc_hb_n[02] -#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[02] }]; #IO_L2P_T0_18 Sch=fmc_hb_p[02] -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[03] }]; #IO_L11N_T1_SRCC_18 Sch=fmc_hb_n[03] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[03] }]; #IO_L11P_T1_SRCC_18 Sch=fmc_hb_p[03] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[04] }]; #IO_L9N_T1_DQS_18 Sch=fmc_hb_n[04] -#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[04] }]; #IO_L9P_T1_DQS_18 Sch=fmc_hb_p[04] -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[05] }]; #IO_L1N_T0_18 Sch=fmc_hb_n[05] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[05] }]; #IO_L1P_T0_18 Sch=fmc_hb_p[05] -#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[06] }]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06] -#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[06] }]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[07] }]; #IO_L22N_T3_18 Sch=fmc_hb_n[07] -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[07] }]; #IO_L22P_T3_18 Sch=fmc_hb_p[07] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[08] }]; #IO_L5N_T0_18 Sch=fmc_hb_n[08] -#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[08] }]; #IO_L5P_T0_18 Sch=fmc_hb_p[08] -#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[09] }]; #IO_L23N_T3_18 Sch=fmc_hb_n[09] -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[09] }]; #IO_L23P_T3_18 Sch=fmc_hb_p[09] -#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[10] }]; #IO_L8N_T1_18 Sch=fmc_hb_n[10] -#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[10] }]; #IO_L8P_T1_18 Sch=fmc_hb_p[10] -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[11] }]; #IO_L18N_T2_18 Sch=fmc_hb_n[11] -#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[11] }]; #IO_L18P_T2_18 Sch=fmc_hb_p[11] -#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[12] }]; #IO_L17N_T2_18 Sch=fmc_hb_n[12] -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[12] }]; #IO_L17P_T2_18 Sch=fmc_hb_p[12] -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[13] }]; #IO_L15N_T2_DQS_18 Sch=fmc_hb_n[13] -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[13] }]; #IO_L15P_T2_DQS_18 Sch=fmc_hb_p[13] -#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[14] }]; #IO_L10N_T1_18 Sch=fmc_hb_n[14] -#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[14] }]; #IO_L10P_T1_18 Sch=fmc_hb_p[14] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[15] }]; #IO_L3N_T0_DQS_18 Sch=fmc_hb_n[15] -#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[15] }]; #IO_L3P_T0_DQS_18 Sch=fmc_hb_p[15] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[16] }]; #IO_L4N_T0_18 Sch=fmc_hb_n[16] -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[16] }]; #IO_L4P_T0_18 Sch=fmc_hb_p[16] -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[17] }]; #IO_L13N_T2_MRCC_18 Sch=fmc_hb_n[17] -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[17] }]; #IO_L13P_T2_MRCC_18 Sch=fmc_hb_p[17] -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[18] }]; #IO_L20N_T3_18 Sch=fmc_hb_n[18] -#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[18] }]; #IO_L20P_T3_18 Sch=fmc_hb_p[18] -#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[19] }]; #IO_L16N_T2_18 Sch=fmc_hb_n[19] -#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[19] }]; #IO_L16P_T2_18 Sch=fmc_hb_p[19] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[20] }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[20] }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[21] }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[21] }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] -#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[00] }]; #IO_L13N_T2_MRCC_16 Sch=fmc_la_n[00] -#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[00] }]; #IO_L13P_T2_MRCC_16 Sch=fmc_la_p[00] -#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[01] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la_n[01] -#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[01] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la_p[01] -#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L24N_T3_16 Sch=fmc_la_n[02] -#set_property -dict { PACKAGE_PIN H30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L24P_T3_16 Sch=fmc_la_p[02] -#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L18N_T2_16 Sch=fmc_la_n[03] -#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L18P_T2_16 Sch=fmc_la_p[03] -#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] -#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] -#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L17N_T2_16 Sch=fmc_la_n[05] -#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L17P_T2_16 Sch=fmc_la_p[05] -#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] -#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] -#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[07] -#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[07] -#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[08] -#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[08] -#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[09] -#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[09] -#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L7N_T1_16 Sch=fmc_la_n[10] -#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L7P_T1_16 Sch=fmc_la_p[10] -#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L10N_T1_16 Sch=fmc_la_n[11] -#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L10P_T1_16 Sch=fmc_la_p[11] -#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L5N_T0_16 Sch=fmc_la_n[12] -#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L5P_T0_16 Sch=fmc_la_p[12] -#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L4N_T0_16 Sch=fmc_la_n[13] -#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L4P_T0_16 Sch=fmc_la_p[13] -#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[14] -#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[14] -#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L1N_T0_16 Sch=fmc_la_n[15] -#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L1P_T0_16 Sch=fmc_la_p[15] -#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L2N_T0_16 Sch=fmc_la_n[16] -#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L2P_T0_16 Sch=fmc_la_p[16] -#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[17] }]; #IO_L11N_T1_SRCC_17 Sch=fmc_la_n[17] -#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[17] }]; #IO_L11P_T1_SRCC_17 Sch=fmc_la_p[17] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[18] }]; #IO_L13N_T2_MRCC_17 Sch=fmc_la_n[18] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[18] }]; #IO_L13P_T2_MRCC_17 Sch=fmc_la_p[18] -#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L7N_T1_17 Sch=fmc_la_n[19] -#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L7P_T1_17 Sch=fmc_la_p[19] -#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L9N_T1_DQS_17 Sch=fmc_la_n[20] -#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L9P_T1_DQS_17 Sch=fmc_la_p[20] -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L5N_T0_17 Sch=fmc_la_n[21] -#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L5P_T0_17 Sch=fmc_la_p[21] -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0_DQS_17 Sch=fmc_la_n[22] -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0_DQS_17 Sch=fmc_la_p[22] -#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L18N_T2_17 Sch=fmc_la_n[23] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L18P_T2_17 Sch=fmc_la_p[23] -#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L2N_T0_17 Sch=fmc_la_n[24] -#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L2P_T0_17 Sch=fmc_la_p[24] -#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L10N_T1_17 Sch=fmc_la_n[25] -#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L10P_T1_17 Sch=fmc_la_p[25] -#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L23N_T3_17 Sch=fmc_la_n[26] -#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L23P_T3_17 Sch=fmc_la_p[26] -#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L21N_T3_DQS_17 Sch=fmc_la_n[27] -#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L21P_T3_DQS_17 Sch=fmc_la_p[27] -#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L4N_T0_17 Sch=fmc_la_n[28] -#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L4P_T0_17 Sch=fmc_la_p[28] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L22N_T3_17 Sch=fmc_la_n[29] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L22P_T3_17 Sch=fmc_la_p[29] -#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L20N_T3_17 Sch=fmc_la_n[30] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L20P_T3_17 Sch=fmc_la_p[30] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L17N_T2_17 Sch=fmc_la_n[31] -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L17P_T2_17 Sch=fmc_la_p[31] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L1N_T0_17 Sch=fmc_la_n[32] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L1P_T0_17 Sch=fmc_la_p[32] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L15N_T2_DQS_17 Sch=fmc_la_n[33] -#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L15P_T2_DQS_17 Sch=fmc_la_p[33] -#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SCL }]; #IO_L9P_T1_DQS_12 Sch=fmc_scl -#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SDA }]; #IO_L9N_T1_DQS_12 Sch=fmc_sda - -## Fan Control -set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_25_14 Sch=fan_pwm -#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tach - -## DPTI -## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. -#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { PROG_CLKO }]; #IO_L12P_T1_MRCC_13 Sch=prog_clko -set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck -set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; #IO_L2P_T0_13 Sch=prog_d1/mosi -set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; #IO_L2N_T0_13 Sch=prog_d2/miso -set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; #IO_L4P_T0_13 Sch=prog_d3/ss -set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { jtag_trst_ni }]; #IO_L4N_T0_13 Sch=prog_d[4] -#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[5] }]; #IO_L3P_T0_DQS_13 Sch=prog_d[5] -#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[6] }]; #IO_L3N_T0_DQS_13 Sch=prog_d[6] -#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[7] }]; #IO_L1N_T0_13 Sch=prog_d[7] -#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { PROG_OEN }]; #IO_L7N_T1_13 Sch=prog_oen -#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { PROG_RDN }]; #IO_L6N_T0_VREF_13 Sch=prog_rdn -#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { PROG_RXFN }]; #IO_L10P_T1_13 Sch=prog_rxfn -#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { PROG_SIWUN }]; #IO_L5N_T0_13 Sch=prog_siwun -#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien -#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { PROG_TXEN }]; #IO_L6P_T0_13 Sch=prog_txen -#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { PROG_WRN }]; #IO_L12N_T1_MRCC_13 Sch=prog_wrn - -## DSPI -## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. -#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien -#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_SCK }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck -#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_MOSI }]; #IO_L2P_T0_13 Sch=prog_d1/mosi -#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_MISO }]; #IO_L2N_T0_13 Sch=prog_d2/miso -#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SS }]; #IO_L4P_T0_13 Sch=prog_d3/ss - -## QSPI -#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn -#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0] -#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1] -#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2] -#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3] - -## IIC Bus -set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl -set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda - -## Display Port IN -#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n -#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_N }]; #IO_L15N_T2_DQS_32 Sch=rx_aux_ch_n -#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_P }]; #IO_L17P_T2_32 Sch=rx_aux_ch_p -#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_P }]; #IO_L15P_T2_DQS_32 Sch=rx_aux_ch_p -#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { RX_HPD }]; #IO_L10N_T1_12 Sch=rx_hpd - -## Display Port OUT -#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_N }]; #IO_L14N_T2_SRCC_32 Sch=tx_aux_ch_n -#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_N }]; #IO_L16N_T2_32 Sch=tx_aux_ch_n -#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_P }]; #IO_L16P_T2_32 Sch=tx_aux_ch_p -#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_P }]; #IO_L14P_T2_SRCC_32 Sch=tx_aux_ch_p -#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { TX_HPD }]; #IO_L10P_T1_12 Sch=tx_hpd - -## USB -#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_CLK }]; #IO_L13P_T2_MRCC_32 Sch=usb_otg_clk -#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[0] }]; #IO_L19N_T3_VREF_32 Sch=usb_otg_d[0] -#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[1] }]; #IO_L19P_T3_32 Sch=usb_otg_d[1] -#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[2] }]; #IO_L21N_T3_DQS_32 Sch=usb_otg_d[2] -#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[3] }]; #IO_L21P_T3_DQS_32 Sch=usb_otg_d[3] -#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[4] }]; #IO_L20N_T3_32 Sch=usb_otg_d[4] -#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[5] }]; #IO_L20P_T3_32 Sch=usb_otg_d[5] -#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[6] }]; #IO_L22N_T3_32 Sch=usb_otg_d[6] -#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[7] }]; #IO_L22P_T3_32 Sch=usb_otg_d[7] -#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_DIR }]; #IO_L24P_T3_32 Sch=usb_otg_dir -#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_NXT }]; #IO_L23N_T3_32 Sch=usb_otg_nxt -#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_RESETB }]; #IO_25_VRP_32 Sch=usb_otg_resetb -#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_STP }]; #IO_L23P_T3_32 Sch=usb_otg_stp -#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_VBUSOC }]; #IO_L6N_T0_VREF_32 Sch=usb_otg_vbusoc diff --git a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc index a55db78d..ca309916 100644 --- a/target/xilinx/flavor_vanilla/constraints/vcu128.xdc +++ b/target/xilinx/flavor_vanilla/constraints/vcu128.xdc @@ -6,7 +6,7 @@ # Sys clock # ############# -# 100 MHz ref clock +# 100 MHz ref clock single ended out of the diff buffer (cheshire_top_xilinx.sv) set SYS_TCK 10 create_clock -period $SYS_TCK -name sys_clk [get_pins u_ibufg_sys_clk/O] set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] @@ -31,6 +31,7 @@ set_max_delay -through $MIG_RST_O $MIG_TCK # CDCs # ######## +# The only CDC of the design is before in the dram wrapper (xilinx_dram_wrapper.sv) set_max_delay -datapath \ -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK @@ -48,1755 +49,26 @@ set_max_delay -datapath \ # VCU128 Rev1.0 XDC # Date: 01/24/2018 -#### This file is a general .xdc for the VCU128 1 Rev. -#### To use it in a project: -#### - uncomment the lines corresponding to used pins -#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - - -#set_property PACKAGE_PIN BF21 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 -#set_property PACKAGE_PIN BF22 [get_ports "ENET_PDWN_B_I_INT_B_O"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_PDWN_B_I_INT_B_O"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 -#set_property PACKAGE_PIN BH22 [get_ports "ENET_SGMII_IN_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 -#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_IN_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 -#set_property PACKAGE_PIN BG22 [get_ports "ENET_SGMII_IN_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 -#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_IN_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 -#set_property PACKAGE_PIN BJ21 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 -#set_property PACKAGE_PIN BH21 [get_ports "QSFP4_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 -#set_property PACKAGE_PIN BK21 [get_ports "ENET_SGMII_OUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 -#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_OUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 -#set_property PACKAGE_PIN BJ22 [get_ports "ENET_SGMII_OUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 -#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_OUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 -#set_property PACKAGE_PIN BK23 [get_ports "QSFP4_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 -#set_property PACKAGE_PIN BK24 [get_ports "QSFP4_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 -#set_property PACKAGE_PIN BL22 [get_ports "QSFP4_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 -#set_property PACKAGE_PIN BL23 [get_ports "DUMMY_NC"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "DUMMY_NC"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 -#set_property PACKAGE_PIN BG23 [get_ports "ENET_MDIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_MDIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 -#set_property PACKAGE_PIN BF23 [get_ports "QSFP4_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP4_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 -#set_property PACKAGE_PIN BH24 [get_ports "GPIO_LED_0_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_0_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 -#set_property PACKAGE_PIN BG24 [get_ports "GPIO_LED_1_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_1_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 -#set_property PACKAGE_PIN BG25 [get_ports "GPIO_LED_2_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_2_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 -#set_property PACKAGE_PIN BF25 [get_ports "GPIO_LED_3_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_3_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 -#set_property PACKAGE_PIN BF26 [get_ports "GPIO_LED_4_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_4_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 -#set_property PACKAGE_PIN BF27 [get_ports "GPIO_LED_5_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_5_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 -#set_property PACKAGE_PIN BG27 [get_ports "GPIO_LED_6_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_6_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 -#set_property PACKAGE_PIN BG28 [get_ports "GPIO_LED_7_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_LED_7_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 -#set_property PACKAGE_PIN BJ23 [get_ports "ENET_CLKOUT"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_CLKOUT"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 -#set_property PACKAGE_PIN BJ24 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 -#set_property PACKAGE_PIN BH25 [get_ports "QSFP1_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 -#set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 -#set_property PACKAGE_PIN BH26 [get_ports "QSFP1_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 -#set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 -#set_property PACKAGE_PIN BJ27 [get_ports "ENET_SGMII_CLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 -#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_CLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 -#set_property PACKAGE_PIN BH27 [get_ports "ENET_SGMII_CLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 -#set_property IOSTANDARD LVDS [get_ports "ENET_SGMII_CLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 -#set_property PACKAGE_PIN BK25 [get_ports "QSFP2_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 -#set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 -#set_property PACKAGE_PIN BJ26 [get_ports "QSFP2_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 -#set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 -#set_property PACKAGE_PIN BL25 [get_ports "SMA_CLK_OUTPUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 -#set_property IOSTANDARD LVDS [get_ports "SMA_CLK_OUTPUT_N"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 -#set_property PACKAGE_PIN BK26 [get_ports "SMA_CLK_OUTPUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 -#set_property IOSTANDARD LVDS [get_ports "SMA_CLK_OUTPUT_P"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 -#set_property PACKAGE_PIN BK28 [get_ports "UART1_RXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_RXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 -#set_property PACKAGE_PIN BJ28 [get_ports "UART1_TXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_TXD"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 -#set_property PACKAGE_PIN BL26 [get_ports "UART1_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 -#set_property PACKAGE_PIN BL27 [get_ports "UART1_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "UART1_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 -#set_property PACKAGE_PIN BM27 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 -#set_property PACKAGE_PIN BL28 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 -#set_property PACKAGE_PIN BN27 [get_ports "ENET_MDC"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_MDC"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 -#set_property PACKAGE_PIN BP27 [get_ports "ENET_COL_GPIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "ENET_COL_GPIO"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 -#set_property PACKAGE_PIN BN22 [get_ports "SYSCTLR_UCA1_TX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_UCA1_TX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 -#set_property PACKAGE_PIN BM22 [get_ports "SYSCTLR_UCA1_RX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "SYSCTLR_UCA1_RX"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 -#set_property PACKAGE_PIN BM23 [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 -#set_property PACKAGE_PIN BM24 [get_ports "QSFP1_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODSKLL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 -#set_property PACKAGE_PIN BN25 [get_ports "QSFP1_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_RE#setL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 -#set_property PACKAGE_PIN BM25 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_MODPRSL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 -#set_property PACKAGE_PIN BP24 [get_ports "QSFP1_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_INTL_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 -#set_property PACKAGE_PIN BN24 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_LPMODE_LS"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 -#set_property PACKAGE_PIN BP22 [get_ports "UART0_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "UART0_RTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 -#set_property PACKAGE_PIN BP23 [get_ports "UART0_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 -#set_property IOSTANDARD LVCMOS18 [get_ports "UART0_CTS_B"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 -#set_property PACKAGE_PIN BE51 [get_ports "PL_DDR4_A5"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A5"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_66 -#set_property PACKAGE_PIN BD51 [get_ports "PL_DDR4_A1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_66 -#set_property PACKAGE_PIN BE50 [get_ports "PL_DDR4_A3"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A3"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_66 -#set_property PACKAGE_PIN BE49 [get_ports "PL_DDR4_A4"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A4"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_66 -#set_property PACKAGE_PIN BF48 [get_ports "PL_DDR4_A12"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A12"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_66 -#set_property PACKAGE_PIN BF47 [get_ports "PL_DDR4_A10"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A10"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_66 -#set_property PACKAGE_PIN BF52 [get_ports "PL_DDR4_A13"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A13"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_66 -#set_property PACKAGE_PIN BF51 [get_ports "PL_DDR4_A8"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A8"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_66 -#set_property PACKAGE_PIN BG50 [get_ports "PL_DDR4_A7"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A7"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_66 -#set_property PACKAGE_PIN BF50 [get_ports "PL_DDR4_A0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_66 -#set_property PACKAGE_PIN BG49 [get_ports "PL_DDR4_A11"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A11"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_66 -#set_property PACKAGE_PIN BG48 [get_ports "PL_DDR4_A2"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A2"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_66 -#set_property PACKAGE_PIN BG47 [get_ports "PL_DDR4_A9"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A9"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_66 -#set_property PACKAGE_PIN BF53 [get_ports "PL_DDR4_A6"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_A6"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_66 -#set_property PACKAGE_PIN BE54 [get_ports "PL_DDR4_BA0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BA0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_66 -#set_property PACKAGE_PIN BE53 [get_ports "PL_DDR4_BA1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BA1"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_66 -#set_property PACKAGE_PIN BG54 [get_ports "PL_DDR4_BG0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BG0"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_66 -#set_property PACKAGE_PIN BG53 [get_ports "PL_DDR4_WE_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_WE_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_66 -#set_property PACKAGE_PIN BJ54 [get_ports "PL_DDR4_RAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_RAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_66 -#set_property PACKAGE_PIN BH54 [get_ports "PL_DDR4_CAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_CAS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_66 -#set_property PACKAGE_PIN BK54 [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_66 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_sys_clk_p"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_66 -#set_property PACKAGE_PIN BK53 [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_66 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "c0_sys_clk_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_66 -#set_property PACKAGE_PIN BH52 [get_ports "PL_DDR4_CKE"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_CKE"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_66 -#set_property PACKAGE_PIN BG52 [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_act_n"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_66 -#set_property PACKAGE_PIN BJ53 [get_ports "PL_DDR4_TEN"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_TEN"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_66 -#set_property PACKAGE_PIN BJ52 [get_ports "PL_DDR4_ALERT_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_ALERT_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_66 -#set_property PACKAGE_PIN BH50 [get_ports "PL_DDR4_RE#set_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_66 -#set_property IOSTANDARD LVCMOS12 [get_ports "PL_DDR4_RE#set_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_66 -#set_property PACKAGE_PIN BH49 [get_ports "PL_DDR4_ODT"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_ODT"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_66 -#set_property PACKAGE_PIN BJ51 [get_ports "DDR4_CLK_100MHZ_N"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_66 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CLK_100MHZ_N"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_66 -#set_property PACKAGE_PIN BH51 [get_ports "DDR4_CLK_100MHZ_P"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_66 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CLK_100MHZ_P"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_66 -#set_property PACKAGE_PIN BJ47 [get_ports "SYSCTLR_GPIO_0_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_66 -#set_property IOSTANDARD LVCMOS12 [get_ports "SYSCTLR_GPIO_0_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_66 -#set_property PACKAGE_PIN BH47 [get_ports "SYSCTLR_GPIO_1_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_66 -#set_property IOSTANDARD LVCMOS12 [get_ports "SYSCTLR_GPIO_1_LS"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_66 -#set_property PACKAGE_PIN BJ49 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_66 -#set_property PACKAGE_PIN BJ48 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_66 -#set_property PACKAGE_PIN BK51 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_66 -#set_property PACKAGE_PIN BK50 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_66 -#set_property PACKAGE_PIN BK49 [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_66 -#set_property PACKAGE_PIN BK48 [get_ports "PL_DDR4_BOT_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_BOT_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_66 -#set_property PACKAGE_PIN BL48 [get_ports "PL_DDR4_PARITY"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_66 -#set_property IOSTANDARD SSTL12_DCI [get_ports "PL_DDR4_PARITY"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_66 -#set_property PACKAGE_PIN BL50 [get_ports "VRP_66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_66 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_66 -#set_property PACKAGE_PIN BL53 [get_ports "PL_DDR4_DQ69"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ69"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_66 -#set_property PACKAGE_PIN BL52 [get_ports "PL_DDR4_DQ67"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ67"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_66 -#set_property PACKAGE_PIN BM52 [get_ports "PL_DDR4_DQ65"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ65"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_66 -#set_property PACKAGE_PIN BL51 [get_ports "PL_DDR4_DQ71"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ71"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_66 -#set_property PACKAGE_PIN BM50 [get_ports "PL_DDR4_DQS8_C"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_66 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS8_C"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_66 -#set_property PACKAGE_PIN BM49 [get_ports "PL_DDR4_DQS8_T"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_66 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS8_T"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_66 -#set_property PACKAGE_PIN BN49 [get_ports "PL_DDR4_DQ70"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ70"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_66 -#set_property PACKAGE_PIN BM48 [get_ports "PL_DDR4_DQ68"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ68"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_66 -#set_property PACKAGE_PIN BN51 [get_ports "PL_DDR4_DQ64"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ64"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_66 -#set_property PACKAGE_PIN BN50 [get_ports "PL_DDR4_DQ66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ66"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_66 -#set_property PACKAGE_PIN BP49 [get_ports "PL_DDR4_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_66 -#set_property IOSTANDARD SSTL12 [get_ports "PL_DDR4_CS_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_66 -#set_property PACKAGE_PIN BP48 [get_ports "PL_DDR4_DM8_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_66 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM8_B"] ;# Bank 66 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_66 -#set_property PACKAGE_PIN BE44 [get_ports "PL_DDR4_DQ30"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_DOUT_CSO_B_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ30"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_DOUT_CSO_B_65 -#set_property PACKAGE_PIN BE43 [get_ports "PL_DDR4_DQ24"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_EMCCLK_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ24"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_EMCCLK_65 -#set_property PACKAGE_PIN BD42 [get_ports "PL_DDR4_DQ28"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ28"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 -#set_property PACKAGE_PIN BC42 [get_ports "PL_DDR4_DQ26"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_I2C_SCLK_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ26"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_I2C_SCLK_65 -#set_property PACKAGE_PIN BE46 [get_ports "PL_DDR4_DQS3_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS3_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_D05_65 -#set_property PACKAGE_PIN BE45 [get_ports "PL_DDR4_DQS3_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS3_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_D04_65 -#set_property PACKAGE_PIN BF43 [get_ports "PL_DDR4_DQ27"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_D07_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ27"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_D07_65 -#set_property PACKAGE_PIN BF42 [get_ports "PL_DDR4_DQ25"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_D06_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ25"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_D06_65 -#set_property PACKAGE_PIN BF46 [get_ports "PL_DDR4_DQ31"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_D09_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ31"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_D09_65 -#set_property PACKAGE_PIN BF45 [get_ports "PL_DDR4_DQ29"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_D08_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ29"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_D08_65 -#set_property PACKAGE_PIN BE41 [get_ports "SYSMON_SDA_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 -#set_property IOSTANDARD LVCMOS12 [get_ports "SYSMON_SDA_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_D11_65 -#set_property PACKAGE_PIN BD41 [get_ports "PL_DDR4_DM3_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM3_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_D10_65 -#set_property PACKAGE_PIN BF41 [get_ports "PCIE_EP_PERST_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_PERSTN0_65 -#set_property IOSTANDARD LVCMOS12 [get_ports "PCIE_EP_PERST_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_PERSTN0_65 -#set_property PACKAGE_PIN BH41 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_CSI_ADV_B_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_CSI_ADV_B_65 -#set_property PACKAGE_PIN BG45 [get_ports "PL_DDR4_DQ21"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_D13_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ21"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_D13_65 -#set_property PACKAGE_PIN BG44 [get_ports "PL_DDR4_DQ17"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_D12_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ17"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_D12_65 -#set_property PACKAGE_PIN BG43 [get_ports "PL_DDR4_DQ22"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_D15_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ22"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_D15_65 -#set_property PACKAGE_PIN BG42 [get_ports "PL_DDR4_DQ18"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_D14_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ18"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_D14_65 -#set_property PACKAGE_PIN BJ46 [get_ports "PL_DDR4_DQS2_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS2_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 -#set_property PACKAGE_PIN BH46 [get_ports "PL_DDR4_DQS2_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS2_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 -#set_property PACKAGE_PIN BK41 [get_ports "PL_DDR4_DQ16"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_A03_D19_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ16"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_A03_D19_65 -#set_property PACKAGE_PIN BJ41 [get_ports "PL_DDR4_DQ23"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_A02_D18_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ23"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_A02_D18_65 -#set_property PACKAGE_PIN BH45 [get_ports "PL_DDR4_DQ20"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_A05_D21_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ20"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_A05_D21_65 -#set_property PACKAGE_PIN BH44 [get_ports "PL_DDR4_DQ19"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_A04_D20_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ19"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_A04_D20_65 -#set_property PACKAGE_PIN BJ42 [get_ports "PCIE_EP_WAKE_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 -#set_property IOSTANDARD LVCMOS12 [get_ports "PCIE_EP_WAKE_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 -#set_property PACKAGE_PIN BH42 [get_ports "PL_DDR4_DM2_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM2_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 -#set_property PACKAGE_PIN BJ44 [get_ports "PL_DDR4_DQ13"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_A09_D25_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ13"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_A09_D25_65 -#set_property PACKAGE_PIN BJ43 [get_ports "PL_DDR4_DQ15"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_A08_D24_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ15"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_A08_D24_65 -#set_property PACKAGE_PIN BK44 [get_ports "PL_DDR4_DQ9"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_A11_D27_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ9"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_A11_D27_65 -#set_property PACKAGE_PIN BK43 [get_ports "PL_DDR4_DQ11"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_A10_D26_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ11"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_A10_D26_65 -#set_property PACKAGE_PIN BK46 [get_ports "PL_DDR4_DQS1_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS1_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 -#set_property PACKAGE_PIN BK45 [get_ports "PL_DDR4_DQS1_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS1_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 -#set_property PACKAGE_PIN BL43 [get_ports "PL_DDR4_DQ12"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_A15_D31_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ12"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_A15_D31_65 -#set_property PACKAGE_PIN BL42 [get_ports "PL_DDR4_DQ14"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_A14_D30_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ14"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_A14_D30_65 -#set_property PACKAGE_PIN BL46 [get_ports "PL_DDR4_DQ10"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_A17_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ10"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_A17_65 -#set_property PACKAGE_PIN BL45 [get_ports "PL_DDR4_DQ8"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_A16_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ8"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_A16_65 -#set_property PACKAGE_PIN BM47 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_A19_65 -#set_property PACKAGE_PIN BL47 [get_ports "PL_DDR4_DM1_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM1_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_A18_65 -#set_property PACKAGE_PIN BM42 [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_SMBALERT_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_SMBALERT_65 -#set_property PACKAGE_PIN BM43 [get_ports "VRP_65"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_A28_65 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_A28_65 -#set_property PACKAGE_PIN BN45 [get_ports "PL_DDR4_DQ3"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_A21_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ3"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_A21_65 -#set_property PACKAGE_PIN BM45 [get_ports "PL_DDR4_DQ0"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_A20_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ0"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_A20_65 -#set_property PACKAGE_PIN BN44 [get_ports "PL_DDR4_DQ5"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_A23_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ5"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_A23_65 -#set_property PACKAGE_PIN BM44 [get_ports "PL_DDR4_DQ4"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_A22_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ4"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_A22_65 -#set_property PACKAGE_PIN BP46 [get_ports "PL_DDR4_DQS0_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS0_C"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_A25_65 -#set_property PACKAGE_PIN BN46 [get_ports "PL_DDR4_DQS0_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS0_T"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_A24_65 -#set_property PACKAGE_PIN BP44 [get_ports "PL_DDR4_DQ1"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_A27_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ1"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_A27_65 -#set_property PACKAGE_PIN BP43 [get_ports "PL_DDR4_DQ7"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_A26_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ7"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_A26_65 -#set_property PACKAGE_PIN BP47 [get_ports "PL_DDR4_DQ2"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_FWE_FCS2_B_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ2"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_FWE_FCS2_B_65 -#set_property PACKAGE_PIN BN47 [get_ports "PL_DDR4_DQ6"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_FOE_B_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ6"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_FOE_B_65 -#set_property PACKAGE_PIN BP42 [get_ports "SYSMON_SCL_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_RS1_65 -#set_property IOSTANDARD LVCMOS12 [get_ports "SYSMON_SCL_LS"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_RS1_65 -#set_property PACKAGE_PIN BN42 [get_ports "PL_DDR4_DM0_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_RS0_65 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM0_B"] ;# Bank 65 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_RS0_65 -#set_property PACKAGE_PIN BJ31 [get_ports "PL_DDR4_DQ58"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ58"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24N_T3U_N11_64 -#set_property PACKAGE_PIN BH31 [get_ports "PL_DDR4_DQ60"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ60"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L24P_T3U_N10_64 -#set_property PACKAGE_PIN BF33 [get_ports "PL_DDR4_DQ63"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ63"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23N_T3U_N9_64 -#set_property PACKAGE_PIN BF32 [get_ports "PL_DDR4_DQ61"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ61"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L23P_T3U_N8_64 -#set_property PACKAGE_PIN BK30 [get_ports "PL_DDR4_DQS7_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS7_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_64 -#set_property PACKAGE_PIN BJ29 [get_ports "PL_DDR4_DQS7_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS7_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_64 -#set_property PACKAGE_PIN BG32 [get_ports "PL_DDR4_DQ59"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ59"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_64 -#set_property PACKAGE_PIN BF31 [get_ports "PL_DDR4_DQ56"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ56"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_64 -#set_property PACKAGE_PIN BH30 [get_ports "PL_DDR4_DQ57"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ57"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_64 -#set_property PACKAGE_PIN BH29 [get_ports "PL_DDR4_DQ62"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ62"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_64 -#set_property PACKAGE_PIN BG30 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_64 -#set_property PACKAGE_PIN BG29 [get_ports "PL_DDR4_DM7_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM7_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_64 -#set_property PACKAGE_PIN BK29 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T3U_N12_64 -#set_property PACKAGE_PIN BG33 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T2U_N12_64 -#set_property PACKAGE_PIN BH35 [get_ports "PL_DDR4_DQ51"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ51"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_64 -#set_property PACKAGE_PIN BH34 [get_ports "PL_DDR4_DQ50"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ50"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_64 -#set_property PACKAGE_PIN BF36 [get_ports "PL_DDR4_DQ55"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ55"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_64 -#set_property PACKAGE_PIN BF35 [get_ports "PL_DDR4_DQ53"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ53"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_64 -#set_property PACKAGE_PIN BK35 [get_ports "PL_DDR4_DQS6_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS6_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_64 -#set_property PACKAGE_PIN BK34 [get_ports "PL_DDR4_DQS6_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS6_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_64 -#set_property PACKAGE_PIN BG35 [get_ports "PL_DDR4_DQ49"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ49"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_64 -#set_property PACKAGE_PIN BG34 [get_ports "PL_DDR4_DQ54"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ54"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_64 -#set_property PACKAGE_PIN BJ34 [get_ports "PL_DDR4_DQ48"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ48"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_64 -#set_property PACKAGE_PIN BJ33 [get_ports "PL_DDR4_DQ52"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ52"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_64 -#set_property PACKAGE_PIN BJ32 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_64 -#set_property PACKAGE_PIN BH32 [get_ports "PL_DDR4_DM6_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM6_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property PACKAGE_PIN BL33 [get_ports "PL_DDR4_DQ45"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ45"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_64 -#set_property PACKAGE_PIN BK33 [get_ports "PL_DDR4_DQ43"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ43"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_64 -#set_property PACKAGE_PIN BL31 [get_ports "PL_DDR4_DQ44"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ44"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_64 -#set_property PACKAGE_PIN BK31 [get_ports "PL_DDR4_DQ47"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ47"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_64 -#set_property PACKAGE_PIN BM35 [get_ports "PL_DDR4_DQS5_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS5_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_64 -#set_property PACKAGE_PIN BL35 [get_ports "PL_DDR4_DQS5_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS5_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 -#set_property PACKAGE_PIN BM33 [get_ports "PL_DDR4_DQ46"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ46"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_64 -#set_property PACKAGE_PIN BL32 [get_ports "PL_DDR4_DQ40"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ40"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_64 -#set_property PACKAGE_PIN BP34 [get_ports "PL_DDR4_DQ41"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ41"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_64 -#set_property PACKAGE_PIN BN34 [get_ports "PL_DDR4_DQ42"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ42"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_64 -#set_property PACKAGE_PIN BN35 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_64 -#set_property PACKAGE_PIN BM34 [get_ports "PL_DDR4_DM5_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM5_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_64 -#set_property PACKAGE_PIN BP33 [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T1U_N12_64 -#set_property PACKAGE_PIN BM32 [get_ports "VRP_64"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_64 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_64"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_T0U_N12_VRP_64 -#set_property PACKAGE_PIN BP32 [get_ports "PL_DDR4_DQ32"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ32"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_64 -#set_property PACKAGE_PIN BN32 [get_ports "PL_DDR4_DQ36"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ36"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_64 -#set_property PACKAGE_PIN BM30 [get_ports "PL_DDR4_DQ37"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ37"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_64 -#set_property PACKAGE_PIN BL30 [get_ports "PL_DDR4_DQ39"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ39"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_64 -#set_property PACKAGE_PIN BN30 [get_ports "PL_DDR4_DQS4_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS4_C"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_64 -#set_property PACKAGE_PIN BN29 [get_ports "PL_DDR4_DQS4_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "PL_DDR4_DQS4_T"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_64 -#set_property PACKAGE_PIN BP31 [get_ports "PL_DDR4_DQ34"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ34"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_64 -#set_property PACKAGE_PIN BN31 [get_ports "PL_DDR4_DQ38"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ38"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_64 -#set_property PACKAGE_PIN BP29 [get_ports "PL_DDR4_DQ33"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ33"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2N_T0L_N3_64 -#set_property PACKAGE_PIN BP28 [get_ports "PL_DDR4_DQ35"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DQ35"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L2P_T0L_N2_64 -set_property PACKAGE_PIN BM29 [get_ports cpu_reset] -set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] -#set_property PACKAGE_PIN BM28 [get_ports "PL_DDR4_DM4_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_64 -#set_property IOSTANDARD POD12_DCI [get_ports "PL_DDR4_DM4_B"] ;# Bank 64 VCCO - DDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_64 -#set_property PACKAGE_PIN A16 [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_N"] ;# Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71 -#set_property PACKAGE_PIN B16 [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 71 VCCO - VADJ - IO_L24P_T3U_N10_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA22_P"] ;# Bank 71 VCCO - VADJ - IO_L24P_T3U_N10_71 -#set_property PACKAGE_PIN A18 [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 71 VCCO - VADJ - IO_L23N_T3U_N9_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_N"] ;# Bank 71 VCCO - VADJ - IO_L23N_T3U_N9_71 -#set_property PACKAGE_PIN A19 [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 71 VCCO - VADJ - IO_L23P_T3U_N8_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA21_P"] ;# Bank 71 VCCO - VADJ - IO_L23P_T3U_N8_71 -#set_property PACKAGE_PIN A20 [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_N"] ;# Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71 -#set_property PACKAGE_PIN A21 [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA20_P"] ;# Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71 -#set_property PACKAGE_PIN B17 [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 71 VCCO - VADJ - IO_L21N_T3L_N5_AD8N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_N"] ;# Bank 71 VCCO - VADJ - IO_L21N_T3L_N5_AD8N_71 -#set_property PACKAGE_PIN B18 [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 71 VCCO - VADJ - IO_L21P_T3L_N4_AD8P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA19_P"] ;# Bank 71 VCCO - VADJ - IO_L21P_T3L_N4_AD8P_71 -#set_property PACKAGE_PIN B20 [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 71 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_N"] ;# Bank 71 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_71 -#set_property PACKAGE_PIN B21 [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 71 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA23_P"] ;# Bank 71 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_71 -#set_property PACKAGE_PIN C17 [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 71 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_N"] ;# Bank 71 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_71 -#set_property PACKAGE_PIN C18 [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 71 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA24_P"] ;# Bank 71 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_71 -#set_property PACKAGE_PIN C19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T3U_N12_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T3U_N12_71 -#set_property PACKAGE_PIN C20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T2U_N12_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T2U_N12_71 -#set_property PACKAGE_PIN D19 [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 71 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_N"] ;# Bank 71 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_71 -#set_property PACKAGE_PIN D20 [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA25_P"] ;# Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71 -#set_property PACKAGE_PIN D16 [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 71 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_N"] ;# Bank 71 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_71 -#set_property PACKAGE_PIN D17 [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 71 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA26_P"] ;# Bank 71 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_71 -#set_property PACKAGE_PIN D21 [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 71 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_N"] ;# Bank 71 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_71 -#set_property PACKAGE_PIN E21 [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 71 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA27_P"] ;# Bank 71 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_71 -#set_property PACKAGE_PIN E16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_71 -#set_property PACKAGE_PIN F16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_71 -#set_property PACKAGE_PIN E18 [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L14N_T2L_N3_GC_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L14N_T2L_N3_GC_71 -#set_property PACKAGE_PIN E19 [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L14P_T2L_N2_GC_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA18_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L14P_T2L_N2_GC_71 -#set_property PACKAGE_PIN E17 [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_N"] ;# Bank 71 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_71 -#set_property PACKAGE_PIN F18 [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA17_CC_P"] ;# Bank 71 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_71 -#set_property PACKAGE_PIN F19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12N_T1U_N11_GC_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12N_T1U_N11_GC_71 -#set_property PACKAGE_PIN F20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12P_T1U_N10_GC_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L12P_T1U_N10_GC_71 -#set_property PACKAGE_PIN G17 [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 71 VCCO - VADJ - IO_L11N_T1U_N9_GC_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_N"] ;# Bank 71 VCCO - VADJ - IO_L11N_T1U_N9_GC_71 -#set_property PACKAGE_PIN G18 [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 71 VCCO - VADJ - IO_L11P_T1U_N8_GC_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK1_M2C_P"] ;# Bank 71 VCCO - VADJ - IO_L11P_T1U_N8_GC_71 -#set_property PACKAGE_PIN F21 [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 71 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_N"] ;# Bank 71 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_71 -#set_property PACKAGE_PIN G21 [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 71 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA28_P"] ;# Bank 71 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_71 -#set_property PACKAGE_PIN H18 [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 71 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_N"] ;# Bank 71 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_71 -#set_property PACKAGE_PIN H19 [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 71 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA29_P"] ;# Bank 71 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_71 -#set_property PACKAGE_PIN G20 [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 71 VCCO - VADJ - IO_L8N_T1L_N3_AD5N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_N"] ;# Bank 71 VCCO - VADJ - IO_L8N_T1L_N3_AD5N_71 -#set_property PACKAGE_PIN H20 [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 71 VCCO - VADJ - IO_L8P_T1L_N2_AD5P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA32_P"] ;# Bank 71 VCCO - VADJ - IO_L8P_T1L_N2_AD5P_71 -#set_property PACKAGE_PIN G16 [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 71 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_N"] ;# Bank 71 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_71 -#set_property PACKAGE_PIN H17 [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 71 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA31_P"] ;# Bank 71 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_71 -#set_property PACKAGE_PIN J16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T1U_N12_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_T1U_N12_71 -#set_property PACKAGE_PIN J17 [get_ports "VRP_71"] ;# Bank 71 VCCO - VADJ - IO_T0U_N12_VRP_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_71"] ;# Bank 71 VCCO - VADJ - IO_T0U_N12_VRP_71 -#set_property PACKAGE_PIN J19 [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 71 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_N"] ;# Bank 71 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_71 -#set_property PACKAGE_PIN J20 [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 71 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA30_P"] ;# Bank 71 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_71 -#set_property PACKAGE_PIN J21 [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 71 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_N"] ;# Bank 71 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_71 -#set_property PACKAGE_PIN K21 [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 71 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_71 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA33_P"] ;# Bank 71 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_71 -#set_property PACKAGE_PIN K18 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_71 -#set_property PACKAGE_PIN K19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_71 -#set_property PACKAGE_PIN L20 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_71 -#set_property PACKAGE_PIN L21 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_71 -#set_property PACKAGE_PIN L18 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2N_T0L_N3_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2N_T0L_N3_71 -#set_property PACKAGE_PIN L19 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2P_T0L_N2_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L2P_T0L_N2_71 -#set_property PACKAGE_PIN K16 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1N_T0L_N1_DBC_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1N_T0L_N1_DBC_71 -#set_property PACKAGE_PIN K17 [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1P_T0L_N0_DBC_71 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 71 VCCO - VADJ - IO_L1P_T0L_N0_DBC_71 -#set_property PACKAGE_PIN A8 [get_ports "QDR4_DQB31"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB31"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_70 -#set_property PACKAGE_PIN A9 [get_ports "QDR4_DQB32"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB32"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_70 -#set_property PACKAGE_PIN A10 [get_ports "QDR4_DQB35"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB35"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_70 -#set_property PACKAGE_PIN A11 [get_ports "QDR4_DQB28"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB28"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_70 -#set_property PACKAGE_PIN A13 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_70 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_70 -#set_property PACKAGE_PIN B13 [get_ports "QDR4_DQB29"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB29"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_70 -#set_property PACKAGE_PIN B12 [get_ports "QDR4_DQB30"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB30"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_70 -#set_property PACKAGE_PIN C12 [get_ports "QDR4_DQB27"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB27"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_70 -#set_property PACKAGE_PIN B10 [get_ports "QDR4_DQB34"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB34"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_70 -#set_property PACKAGE_PIN B11 [get_ports "QDR4_DQB33"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB33"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_70 -#set_property PACKAGE_PIN C9 [get_ports "QDR4_DKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_70 -#set_property PACKAGE_PIN C10 [get_ports "QDR4_DKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_70 -#set_property PACKAGE_PIN C13 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_70 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_70 -#set_property PACKAGE_PIN C14 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_70 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_70 -#set_property PACKAGE_PIN A14 [get_ports "QDR4_DQB19"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB19"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_70 -#set_property PACKAGE_PIN A15 [get_ports "QDR4_DQB25"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB25"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_70 -#set_property PACKAGE_PIN B15 [get_ports "QDR4_DQB21"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB21"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_70 -#set_property PACKAGE_PIN C15 [get_ports "QDR4_DQB23"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB23"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_70 -#set_property PACKAGE_PIN D14 [get_ports "QDR4_QVLDB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_70 -#set_property PACKAGE_PIN D15 [get_ports "QDR4_DQB20"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB20"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_70 -#set_property PACKAGE_PIN E14 [get_ports "QDR4_DQB18"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB18"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_70 -#set_property PACKAGE_PIN F15 [get_ports "QDR4_DQB24"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB24"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_70 -#set_property PACKAGE_PIN F13 [get_ports "QDR4_DQB22"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB22"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_70 -#set_property PACKAGE_PIN F14 [get_ports "QDR4_DQB26"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB26"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_70 -#set_property PACKAGE_PIN D12 [get_ports "QDR4_QKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB1_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_70 -#set_property PACKAGE_PIN E13 [get_ports "QDR4_QKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB1_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_70 -#set_property PACKAGE_PIN E11 [get_ports "QDR4_DQB12"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB12"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_70 -#set_property PACKAGE_PIN F11 [get_ports "QDR4_DQB16"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB16"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_70 -#set_property PACKAGE_PIN D11 [get_ports "QDR4_DQB17"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB17"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_70 -#set_property PACKAGE_PIN E12 [get_ports "QDR4_DQB10"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB10"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_70 -#set_property PACKAGE_PIN D9 [get_ports "QDR4_QVLDB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_70 -#set_property PACKAGE_PIN D10 [get_ports "QDR4_DQB13"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB13"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_70 -#set_property PACKAGE_PIN E9 [get_ports "QDR4_DQB14"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB14"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_70 -#set_property PACKAGE_PIN F9 [get_ports "QDR4_DQB15"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB15"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_70 -#set_property PACKAGE_PIN F10 [get_ports "QDR4_DQB11"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB11"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_70 -#set_property PACKAGE_PIN G11 [get_ports "QDR4_DQB9"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB9"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_70 -#set_property PACKAGE_PIN G10 [get_ports "QDR4_QKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_70 -#set_property PACKAGE_PIN H10 [get_ports "QDR4_QKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_70 -#set_property PACKAGE_PIN H9 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_70 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_70 -#set_property PACKAGE_PIN G12 [get_ports "VRP_70"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_70 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_70"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_70 -#set_property PACKAGE_PIN G13 [get_ports "QDR4_DQB5"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB5"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_70 -#set_property PACKAGE_PIN H14 [get_ports "QDR4_DQB4"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB4"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_70 -#set_property PACKAGE_PIN H12 [get_ports "QDR4_DQB7"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB7"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_70 -#set_property PACKAGE_PIN H13 [get_ports "QDR4_DQB8"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB8"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_70 -#set_property PACKAGE_PIN G15 [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_70 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_70 -#set_property PACKAGE_PIN H15 [get_ports "QDR4_DQB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB0"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_70 -#set_property PACKAGE_PIN J11 [get_ports "QDR4_DQB3"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB3"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_70 -#set_property PACKAGE_PIN J12 [get_ports "QDR4_DQB2"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB2"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_70 -#set_property PACKAGE_PIN J14 [get_ports "QDR4_DQB6"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB6"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_70 -#set_property PACKAGE_PIN J15 [get_ports "QDR4_DQB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_70 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQB1"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_70 -#set_property PACKAGE_PIN K13 [get_ports "QDR4_DKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB0_N"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_70 -#set_property PACKAGE_PIN K14 [get_ports "QDR4_DKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_70 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKB0_P"] ;# Bank 70 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_70 -#set_property PACKAGE_PIN BF1 [get_ports "QDR4_A1"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A1"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_69 -#set_property PACKAGE_PIN BE1 [get_ports "QDR4_A2"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A2"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_69 -#set_property PACKAGE_PIN BE3 [get_ports "QDR4_A3"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A3"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_69 -#set_property PACKAGE_PIN BE4 [get_ports "QDR4_A4"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A4"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_69 -#set_property PACKAGE_PIN BE5 [get_ports "QDR4_A5"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A5"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_69 -#set_property PACKAGE_PIN BE6 [get_ports "QDR4_A6"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A6"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_69 -#set_property PACKAGE_PIN BF2 [get_ports "QDR4_A7"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A7"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_69 -#set_property PACKAGE_PIN BF3 [get_ports "QDR4_A8"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A8"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_69 -#set_property PACKAGE_PIN BG2 [get_ports "QDR4_A9"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A9"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_69 -#set_property PACKAGE_PIN BG3 [get_ports "QDR4_A10"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A10"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_69 -#set_property PACKAGE_PIN BG4 [get_ports "QDR4_A11"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A11"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_69 -#set_property PACKAGE_PIN BG5 [get_ports "QDR4_A12"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A12"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_69 -#set_property PACKAGE_PIN BF5 [get_ports "QDR4_A0"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A0"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_69 -#set_property PACKAGE_PIN BF6 [get_ports "No Connect"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_69 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_69 -#set_property PACKAGE_PIN BF7 [get_ports "QDR4_A13"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A13"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_69 -#set_property PACKAGE_PIN BF8 [get_ports "QDR4_A14"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A14"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_69 -#set_property PACKAGE_PIN BG7 [get_ports "QDR4_A15"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A15"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_69 -#set_property PACKAGE_PIN BG8 [get_ports "QDR4_A16"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A16"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_69 -#set_property PACKAGE_PIN BJ7 [get_ports "QDR4_A17"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A17"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_69 -#set_property PACKAGE_PIN BH7 [get_ports "QDR4_A18"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A18"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_69 -#set_property PACKAGE_PIN BK8 [get_ports "QDR4_A19"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A19"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_69 -#set_property PACKAGE_PIN BJ8 [get_ports "QDR4_A20"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A20"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_69 -#set_property PACKAGE_PIN BH4 [get_ports "QDR4_CK_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_69 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_CK_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_69 -#set_property PACKAGE_PIN BH5 [get_ports "QDR4_CK_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_69 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_CK_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_69 -#set_property PACKAGE_PIN BJ6 [get_ports "QDR4_A21"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A21"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_69 -#set_property PACKAGE_PIN BH6 [get_ports "QDR4_A23"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A23"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_69 -#set_property PACKAGE_PIN BK4 [get_ports "QDR4_A24"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A24"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_69 -#set_property PACKAGE_PIN BK5 [get_ports "QDR4_A22"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_A22"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_69 -#set_property PACKAGE_PIN BK3 [get_ports "QDR4_CLK_100MHZ_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_69 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_69 -#set_property PACKAGE_PIN BJ4 [get_ports "QDR4_CLK_100MHZ_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_69 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "QDR4_CLK_100MHZ_P"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_69 -#set_property PACKAGE_PIN BJ2 [get_ports "QDR4_PE_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_PE_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_69 -#set_property PACKAGE_PIN BJ3 [get_ports "QDR4_LBK0_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LBK0_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_69 -#set_property PACKAGE_PIN BH1 [get_ports "QDR4_LBK1_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LBK1_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_69 -#set_property PACKAGE_PIN BH2 [get_ports "QDR4_CFG_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_CFG_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_69 -#set_property PACKAGE_PIN BK1 [get_ports "QDR4_RST_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QDR4_RST_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_69 -#set_property PACKAGE_PIN BJ1 [get_ports "QDR4_AINV"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_AINV"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_69 -#set_property PACKAGE_PIN BL2 [get_ports "QDR4_LDB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LDB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_69 -#set_property PACKAGE_PIN BL3 [get_ports "QDR4_RWB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_RWB_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_69 -#set_property PACKAGE_PIN BK6 [get_ports "QDR4_AP"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_AP"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_69 -#set_property PACKAGE_PIN BL5 [get_ports "VRP_69"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_69 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_69"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_69 -#set_property PACKAGE_PIN BM3 [get_ports "QDR4_LDA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_LDA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_69 -#set_property PACKAGE_PIN BM4 [get_ports "QDR4_RWA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_69 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_RWA_N"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_69 -#set_property PACKAGE_PIN BM5 [get_ports "QSFP3_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_69 -#set_property PACKAGE_PIN BL6 [get_ports "QSFP3_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_69 -#set_property PACKAGE_PIN BM7 [get_ports "QSFP3_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_69 -#set_property PACKAGE_PIN BL7 [get_ports "QSFP3_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_69 -#set_property PACKAGE_PIN BN4 [get_ports "QSFP3_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP3_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_69 -#set_property PACKAGE_PIN BN5 [get_ports "QSFP2_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_MODSKLL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_69 -#set_property PACKAGE_PIN BN6 [get_ports "QSFP2_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_RE#setL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_69 -#set_property PACKAGE_PIN BN7 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_MODPRSL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_69 -#set_property PACKAGE_PIN BP6 [get_ports "QSFP2_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_INTL_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_69 -#set_property PACKAGE_PIN BP7 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_69 -#set_property IOSTANDARD LVCMOS12 [get_ports "QSFP2_LPMODE_LS"] ;# Bank 69 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_69 -#set_property PACKAGE_PIN BE9 [get_ports "QDR4_DQA27"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA27"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24N_T3U_N11_68 -#set_property PACKAGE_PIN BE10 [get_ports "QDR4_DQA28"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA28"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L24P_T3U_N10_68 -#set_property PACKAGE_PIN BF10 [get_ports "QDR4_DQA31"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA31"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23N_T3U_N9_68 -#set_property PACKAGE_PIN BE11 [get_ports "QDR4_DQA30"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA30"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L23P_T3U_N8_68 -#set_property PACKAGE_PIN BF11 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_68 -#set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_68 -#set_property PACKAGE_PIN BF12 [get_ports "QDR4_DQA35"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA35"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_68 -#set_property PACKAGE_PIN BG9 [get_ports "QDR4_DQA33"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA33"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_68 -#set_property PACKAGE_PIN BG10 [get_ports "QDR4_DQA34"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA34"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_68 -#set_property PACKAGE_PIN BG12 [get_ports "QDR4_DQA32"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA32"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_68 -#set_property PACKAGE_PIN BG13 [get_ports "QDR4_DQA29"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA29"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_68 -#set_property PACKAGE_PIN BH9 [get_ports "QDR4_DKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_68 -#set_property PACKAGE_PIN BH10 [get_ports "QDR4_DKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_68 -#set_property PACKAGE_PIN BH11 [get_ports "PMBUS_ALERT_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_68 -#set_property IOSTANDARD LVCMOS12 [get_ports "PMBUS_ALERT_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T3U_N12_68 -#set_property PACKAGE_PIN BH12 [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_68 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T2U_N12_68 -#set_property PACKAGE_PIN BH14 [get_ports "QDR4_DQA23"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA23"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_68 -#set_property PACKAGE_PIN BH15 [get_ports "QDR4_DQA24"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA24"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_68 -#set_property PACKAGE_PIN BJ12 [get_ports "QDR4_DQA20"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA20"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_68 -#set_property PACKAGE_PIN BJ13 [get_ports "QDR4_DQA26"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA26"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_68 -#set_property PACKAGE_PIN BK13 [get_ports "QDR4_QVLDA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_68 -#set_property PACKAGE_PIN BJ14 [get_ports "QDR4_DQA25"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA25"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_68 -#set_property PACKAGE_PIN BK14 [get_ports "QDR4_DQA19"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA19"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_68 -#set_property PACKAGE_PIN BK15 [get_ports "QDR4_DQA21"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA21"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_68 -#set_property PACKAGE_PIN BL12 [get_ports "QDR4_DQA18"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA18"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14N_T2L_N3_GC_68 -#set_property PACKAGE_PIN BL13 [get_ports "QDR4_DQA22"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA22"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L14P_T2L_N2_GC_68 -#set_property PACKAGE_PIN BK11 [get_ports "QDR4_QKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA1_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_68 -#set_property PACKAGE_PIN BJ11 [get_ports "QDR4_QKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA1_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_68 -#set_property PACKAGE_PIN BK9 [get_ports "QDR4_DQA10"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA10"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12N_T1U_N11_GC_68 -#set_property PACKAGE_PIN BJ9 [get_ports "QDR4_DQA17"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA17"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L12P_T1U_N10_GC_68 -#set_property PACKAGE_PIN BL10 [get_ports "QDR4_DQA11"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA11"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11N_T1U_N9_GC_68 -#set_property PACKAGE_PIN BK10 [get_ports "QDR4_DQA12"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA12"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L11P_T1U_N8_GC_68 -#set_property PACKAGE_PIN BM8 [get_ports "QDR4_QVLDA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_QVLDA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_68 -#set_property PACKAGE_PIN BL8 [get_ports "QDR4_DQA13"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA13"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_68 -#set_property PACKAGE_PIN BN9 [get_ports "QDR4_DQA16"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA16"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_68 -#set_property PACKAGE_PIN BM9 [get_ports "QDR4_DQA9"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA9"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_68 -#set_property PACKAGE_PIN BN10 [get_ports "QDR4_DQA14"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA14"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_68 -#set_property PACKAGE_PIN BM10 [get_ports "QDR4_DQA15"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA15"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_68 -#set_property PACKAGE_PIN BP8 [get_ports "QDR4_QKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_68 -#set_property PACKAGE_PIN BP9 [get_ports "QDR4_QKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_QKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_68 -#set_property PACKAGE_PIN BL11 [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_68 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T1U_N12_68 -#set_property PACKAGE_PIN BN11 [get_ports "VRP_68"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_68 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_68"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_T0U_N12_VRP_68 -#set_property PACKAGE_PIN BM15 [get_ports "QDR4_DQA4"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA4"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_68 -#set_property PACKAGE_PIN BL15 [get_ports "QDR4_DQA8"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA8"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_68 -#set_property PACKAGE_PIN BM13 [get_ports "QDR4_DQA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA1"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_68 -#set_property PACKAGE_PIN BM14 [get_ports "QDR4_DQA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA0"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_68 -#set_property PACKAGE_PIN BN14 [get_ports "SI5328_RST_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_68 -#set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_RST_B_LS"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_68 -#set_property PACKAGE_PIN BN15 [get_ports "QDR4_DQA2"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA2"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_68 -#set_property PACKAGE_PIN BN12 [get_ports "QDR4_DQA3"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA3"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_68 -#set_property PACKAGE_PIN BM12 [get_ports "QDR4_DQA7"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA7"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_68 -#set_property PACKAGE_PIN BP13 [get_ports "QDR4_DQA5"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA5"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2N_T0L_N3_68 -#set_property PACKAGE_PIN BP14 [get_ports "QDR4_DQA6"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_68 -#set_property IOSTANDARD POD12_DCI [get_ports "QDR4_DQA6"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L2P_T0L_N2_68 -#set_property PACKAGE_PIN BP11 [get_ports "QDR4_DKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA0_N"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_68 -#set_property PACKAGE_PIN BP12 [get_ports "QDR4_DKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_68 -#set_property IOSTANDARD DIFF_POD12_DCI [get_ports "QDR4_DKA0_P"] ;# Bank 68 VCCO - QDR4_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_68 -#set_property PACKAGE_PIN A28 [get_ports "RLD3_72B_DM1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_75 -#set_property PACKAGE_PIN B28 [get_ports "RLD3_72B_DQ35"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ35"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_75 -#set_property PACKAGE_PIN A30 [get_ports "RLD3_72B_DQ31"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ31"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_75 -#set_property PACKAGE_PIN A29 [get_ports "RLD3_72B_DQ34"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ34"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_75 -#set_property PACKAGE_PIN A31 [get_ports "RLD3_72B_DQ27"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ27"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_75 -#set_property PACKAGE_PIN B30 [get_ports "RLD3_72B_DQ30"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ30"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_75 -#set_property PACKAGE_PIN A33 [get_ports "RLD3_72B_DQ29"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ29"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_75 -#set_property PACKAGE_PIN B32 [get_ports "RLD3_72B_DQ28"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ28"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_75 -#set_property PACKAGE_PIN C29 [get_ports "RLD3_72B_DQ33"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ33"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_75 -#set_property PACKAGE_PIN C28 [get_ports "RLD3_72B_DQ32"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ32"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_75 -#set_property PACKAGE_PIN B31 [get_ports "RLD3_72B_QK3_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_75 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK3_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_75 -#set_property PACKAGE_PIN C30 [get_ports "RLD3_72B_QK3_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_75 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK3_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_75 -#set_property PACKAGE_PIN B33 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_75 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_75 -#set_property PACKAGE_PIN C33 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_75 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_75 -#set_property PACKAGE_PIN D29 [get_ports "RLD3_72B_DQ25"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ25"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_75 -#set_property PACKAGE_PIN E28 [get_ports "RLD3_72B_QVLD1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_75 -#set_property PACKAGE_PIN C32 [get_ports "RLD3_72B_DQ21"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ21"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_75 -#set_property PACKAGE_PIN D32 [get_ports "RLD3_72B_DQ24"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ24"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_75 -#set_property PACKAGE_PIN D31 [get_ports "RLD3_72B_DQ26"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ26"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_75 -#set_property PACKAGE_PIN D30 [get_ports "RLD3_72B_DQ23"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ23"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_75 -#set_property PACKAGE_PIN E33 [get_ports "RLD3_72B_DQ18"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ18"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_75 -#set_property PACKAGE_PIN F33 [get_ports "RLD3_72B_DQ22"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ22"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_75 -#set_property PACKAGE_PIN E29 [get_ports "RLD3_72B_DQ20"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ20"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_75 -#set_property PACKAGE_PIN F29 [get_ports "RLD3_72B_DQ19"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ19"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_75 -#set_property PACKAGE_PIN E32 [get_ports "RLD3_72B_QK2_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QK2_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_75 -#set_property PACKAGE_PIN E31 [get_ports "RLD3_72B_QK2_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QK2_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_75 -#set_property PACKAGE_PIN F30 [get_ports "RLD3_72B_QVLD0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_75 -#set_property PACKAGE_PIN G30 [get_ports "RLD3_72B_DQ9"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ9"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_75 -#set_property PACKAGE_PIN F31 [get_ports "RLD3_72B_DQ11"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ11"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_75 -#set_property PACKAGE_PIN G31 [get_ports "RLD3_72B_DQ14"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ14"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_75 -#set_property PACKAGE_PIN F28 [get_ports "RLD3_72B_DQ17"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ17"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_75 -#set_property PACKAGE_PIN G28 [get_ports "RLD3_72B_DQ12"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ12"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_75 -#set_property PACKAGE_PIN G32 [get_ports "RLD3_72B_DQ15"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ15"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_75 -#set_property PACKAGE_PIN H32 [get_ports "RLD3_72B_DQ16"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ16"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_75 -#set_property PACKAGE_PIN H30 [get_ports "RLD3_72B_DQ10"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ10"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_75 -#set_property PACKAGE_PIN H29 [get_ports "RLD3_72B_DQ13"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ13"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_75 -#set_property PACKAGE_PIN G33 [get_ports "RLD3_72B_QK1_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_75 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK1_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_75 -#set_property PACKAGE_PIN H33 [get_ports "RLD3_72B_QK1_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_75 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK1_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_75 -#set_property PACKAGE_PIN H28 [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_75 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_75 -#set_property PACKAGE_PIN K28 [get_ports "VRP_75"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_75 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_75"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_75 -#set_property PACKAGE_PIN J29 [get_ports "RLD3_72B_DM0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_75 -#set_property PACKAGE_PIN K29 [get_ports "RLD3_72B_DQ0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ0"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_75 -#set_property PACKAGE_PIN J31 [get_ports "RLD3_72B_DQ3"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ3"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_75 -#set_property PACKAGE_PIN J30 [get_ports "RLD3_72B_DQ1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ1"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_75 -#set_property PACKAGE_PIN J32 [get_ports "RLD3_72B_DQ7"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ7"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_75 -#set_property PACKAGE_PIN K32 [get_ports "RLD3_72B_DQ2"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ2"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_75 -#set_property PACKAGE_PIN K31 [get_ports "RLD3_72B_DQ8"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ8"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_75 -#set_property PACKAGE_PIN L31 [get_ports "RLD3_72B_DQ5"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ5"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_75 -#set_property PACKAGE_PIN L30 [get_ports "RLD3_72B_DQ6"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ6"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_75 -#set_property PACKAGE_PIN L29 [get_ports "RLD3_72B_DQ4"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_75 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ4"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_75 -#set_property PACKAGE_PIN K33 [get_ports "RLD3_72B_QK0_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_75 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK0_N"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_75 -#set_property PACKAGE_PIN L33 [get_ports "RLD3_72B_QK0_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_75 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK0_P"] ;# Bank 75 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_75 -#set_property PACKAGE_PIN A35 [get_ports "RLD3_72B_A12"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A12"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_74 -#set_property PACKAGE_PIN A34 [get_ports "RLD3_72B_CS_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_CS_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_74 -#set_property PACKAGE_PIN A36 [get_ports "RLD3_72B_BA2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_74 -#set_property PACKAGE_PIN B35 [get_ports "RLD3_72B_A8"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A8"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_74 -#set_property PACKAGE_PIN A38 [get_ports "RLD3_72B_A1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_74 -#set_property PACKAGE_PIN B37 [get_ports "RLD3_72B_BA1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA1"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_74 -#set_property PACKAGE_PIN B36 [get_ports "RLD3_72B_A17"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A17"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_74 -#set_property PACKAGE_PIN C35 [get_ports "RLD3_72B_A13"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A13"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_74 -#set_property PACKAGE_PIN B38 [get_ports "RLD3_72B_A2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A2"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_74 -#set_property PACKAGE_PIN C37 [get_ports "RLD3_72B_A16"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A16"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_74 -#set_property PACKAGE_PIN C34 [get_ports "RLD3_72B_BA0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_74 -#set_property PACKAGE_PIN D34 [get_ports "RLD3_72B_A10"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A10"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_74 -#set_property PACKAGE_PIN C38 [get_ports "RLD3_72B_A6"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A6"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_74 -#set_property PACKAGE_PIN C39 [get_ports "RLD3_72B_A20"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A20"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_74 -#set_property PACKAGE_PIN D37 [get_ports "RLD3_72B_WE_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_WE_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_74 -#set_property PACKAGE_PIN E36 [get_ports "RLD3_72B_A7"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A7"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_74 -#set_property PACKAGE_PIN E34 [get_ports "RLD3_72B_REF_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_REF_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_74 -#set_property PACKAGE_PIN F34 [get_ports "RLD3_72B_A18"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A18"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_74 -#set_property PACKAGE_PIN D39 [get_ports "RLD3_72B_A0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A0"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_74 -#set_property PACKAGE_PIN E39 [get_ports "RLD3_72B_A11"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A11"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_74 -#set_property PACKAGE_PIN D36 [get_ports "RLD3_72B_BA3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_BA3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_74 -#set_property PACKAGE_PIN D35 [get_ports "RLD3_72B_RE#set_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_RE#set_B"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_74 -#set_property PACKAGE_PIN E38 [get_ports "RLD3_72B_A15"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A15"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_74 -#set_property PACKAGE_PIN E37 [get_ports "RLD3_72B_A14"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A14"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_74 -#set_property PACKAGE_PIN F36 [get_ports "RLD3_CLK_100MHZ_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_74 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_CLK_100MHZ_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_74 -#set_property PACKAGE_PIN F35 [get_ports "RLD3_CLK_100MHZ_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_74 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_CLK_100MHZ_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_74 -#set_property PACKAGE_PIN F38 [get_ports "RLD3_72B_CK_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_CK_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_74 -#set_property PACKAGE_PIN G37 [get_ports "RLD3_72B_CK_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_CK_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_74 -#set_property PACKAGE_PIN G36 [get_ports "RLD3_72B_DK3_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK3_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_74 -#set_property PACKAGE_PIN G35 [get_ports "RLD3_72B_DK3_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK3_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_74 -#set_property PACKAGE_PIN F39 [get_ports "RLD3_72B_DK2_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK2_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_74 -#set_property PACKAGE_PIN G38 [get_ports "RLD3_72B_DK2_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK2_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_74 -#set_property PACKAGE_PIN H35 [get_ports "RLD3_72B_DK1_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK1_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_74 -#set_property PACKAGE_PIN H34 [get_ports "RLD3_72B_DK1_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK1_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_74 -#set_property PACKAGE_PIN H38 [get_ports "RLD3_72B_DK0_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK0_N"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_74 -#set_property PACKAGE_PIN H37 [get_ports "RLD3_72B_DK0_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_74 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_DK0_P"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_74 -#set_property PACKAGE_PIN H39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_74 -#set_property PACKAGE_PIN J39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_74 -#set_property PACKAGE_PIN J34 [get_ports "RLD3_72B_A3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A3"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_74 -#set_property PACKAGE_PIN J35 [get_ports "VRP_74"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_74 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "VRP_74"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_74 -#set_property PACKAGE_PIN J37 [get_ports "RLD3_72B_A19"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A19"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_74 -#set_property PACKAGE_PIN K37 [get_ports "RLD3_72B_A5"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A5"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_74 -#set_property PACKAGE_PIN K34 [get_ports "RLD3_72B_A4"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A4"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_74 -#set_property PACKAGE_PIN L34 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_74 -#set_property PACKAGE_PIN K38 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_74 -#set_property PACKAGE_PIN L38 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_74 -#set_property PACKAGE_PIN J36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_74 -#set_property PACKAGE_PIN K36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_74 -#set_property PACKAGE_PIN K39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_74 -#set_property PACKAGE_PIN L39 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_74 -#set_property PACKAGE_PIN L36 [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_74 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_74 -#set_property PACKAGE_PIN L35 [get_ports "RLD3_72B_A9"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_74 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_A9"] ;# Bank 74 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_74 -#set_property PACKAGE_PIN A40 [get_ports "RLD3_72B_DM3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24N_T3U_N11_73 -#set_property PACKAGE_PIN A39 [get_ports "RLD3_72B_DQ65"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ65"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L24P_T3U_N10_73 -#set_property PACKAGE_PIN B42 [get_ports "RLD3_72B_DQ70"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ70"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23N_T3U_N9_73 -#set_property PACKAGE_PIN B41 [get_ports "RLD3_72B_DQ67"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ67"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L23P_T3U_N8_73 -#set_property PACKAGE_PIN A41 [get_ports "RLD3_72B_DQ66"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ66"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22N_T3U_N7_DBC_AD0N_73 -#set_property PACKAGE_PIN B40 [get_ports "RLD3_72B_DQ68"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ68"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L22P_T3U_N6_DBC_AD0P_73 -#set_property PACKAGE_PIN D41 [get_ports "RLD3_72B_DQ69"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ69"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21N_T3L_N5_AD8N_73 -#set_property PACKAGE_PIN E41 [get_ports "RLD3_72B_DQ71"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ71"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L21P_T3L_N4_AD8P_73 -#set_property PACKAGE_PIN C40 [get_ports "RLD3_72B_DQ64"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ64"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20N_T3L_N3_AD1N_73 -#set_property PACKAGE_PIN D40 [get_ports "RLD3_72B_DQ63"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ63"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L20P_T3L_N2_AD1P_73 -#set_property PACKAGE_PIN F41 [get_ports "RLD3_72B_QK7_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK7_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19N_T3L_N1_DBC_AD9N_73 -#set_property PACKAGE_PIN F40 [get_ports "RLD3_72B_QK7_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK7_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L19P_T3L_N0_DBC_AD9P_73 -#set_property PACKAGE_PIN C42 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_73 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T3U_N12_73 -#set_property PACKAGE_PIN B43 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_73 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T2U_N12_73 -#set_property PACKAGE_PIN A44 [get_ports "RLD3_72B_QVLD3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD3"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18N_T2U_N11_AD2N_73 -#set_property PACKAGE_PIN A43 [get_ports "RLD3_72B_DQ62"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ62"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L18P_T2U_N10_AD2P_73 -#set_property PACKAGE_PIN B45 [get_ports "RLD3_72B_DQ57"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ57"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17N_T2U_N9_AD10N_73 -#set_property PACKAGE_PIN C44 [get_ports "RLD3_72B_DQ60"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ60"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L17P_T2U_N8_AD10P_73 -#set_property PACKAGE_PIN A46 [get_ports "RLD3_72B_DQ55"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ55"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16N_T2U_N7_QBC_AD3N_73 -#set_property PACKAGE_PIN A45 [get_ports "RLD3_72B_DQ58"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ58"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L16P_T2U_N6_QBC_AD3P_73 -#set_property PACKAGE_PIN B46 [get_ports "RLD3_72B_DQ54"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ54"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15N_T2L_N5_AD11N_73 -#set_property PACKAGE_PIN C45 [get_ports "RLD3_72B_DQ59"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ59"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L15P_T2L_N4_AD11P_73 -#set_property PACKAGE_PIN C43 [get_ports "RLD3_72B_DQ56"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ56"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14N_T2L_N3_GC_73 -#set_property PACKAGE_PIN D42 [get_ports "RLD3_72B_DQ61"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ61"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L14P_T2L_N2_GC_73 -#set_property PACKAGE_PIN E43 [get_ports "RLD3_72B_QK6_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK6_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13N_T2L_N1_GC_QBC_73 -#set_property PACKAGE_PIN E42 [get_ports "RLD3_72B_QK6_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK6_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L13P_T2L_N0_GC_QBC_73 -#set_property PACKAGE_PIN D45 [get_ports "RLD3_72B_QVLD2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_QVLD2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12N_T1U_N11_GC_73 -#set_property PACKAGE_PIN D44 [get_ports "RLD3_72B_DQ45"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ45"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L12P_T1U_N10_GC_73 -#set_property PACKAGE_PIN E44 [get_ports "RLD3_72B_DQ50"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ50"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11N_T1U_N9_GC_73 -#set_property PACKAGE_PIN F44 [get_ports "RLD3_72B_DQ47"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ47"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L11P_T1U_N8_GC_73 -#set_property PACKAGE_PIN D46 [get_ports "RLD3_72B_DQ48"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ48"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10N_T1U_N7_QBC_AD4N_73 -#set_property PACKAGE_PIN E46 [get_ports "RLD3_72B_DQ51"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ51"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L10P_T1U_N6_QBC_AD4P_73 -#set_property PACKAGE_PIN G45 [get_ports "RLD3_72B_DQ52"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ52"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9N_T1L_N5_AD12N_73 -#set_property PACKAGE_PIN H45 [get_ports "RLD3_72B_DQ53"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ53"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L9P_T1L_N4_AD12P_73 -#set_property PACKAGE_PIN F46 [get_ports "RLD3_72B_DQ49"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ49"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8N_T1L_N3_AD5N_73 -#set_property PACKAGE_PIN F45 [get_ports "RLD3_72B_DQ46"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ46"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L8P_T1L_N2_AD5P_73 -#set_property PACKAGE_PIN H44 [get_ports "RLD3_72B_QK5_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK5_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7N_T1L_N1_QBC_AD13N_73 -#set_property PACKAGE_PIN J44 [get_ports "RLD3_72B_QK5_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK5_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L7P_T1L_N0_QBC_AD13P_73 -#set_property PACKAGE_PIN G46 [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_73 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T1U_N12_73 -#set_property PACKAGE_PIN F43 [get_ports "VRP_73"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_73 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_73"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_T0U_N12_VRP_73 -#set_property PACKAGE_PIN G43 [get_ports "RLD3_72B_DM2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DM2"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6N_T0U_N11_AD6N_73 -#set_property PACKAGE_PIN H43 [get_ports "RLD3_72B_DQ40"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ40"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L6P_T0U_N10_AD6P_73 -#set_property PACKAGE_PIN G42 [get_ports "RLD3_72B_DQ36"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ36"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5N_T0U_N9_AD14N_73 -#set_property PACKAGE_PIN G41 [get_ports "RLD3_72B_DQ37"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ37"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L5P_T0U_N8_AD14P_73 -#set_property PACKAGE_PIN G40 [get_ports "RLD3_72B_DQ39"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ39"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4N_T0U_N7_DBC_AD7N_73 -#set_property PACKAGE_PIN H40 [get_ports "RLD3_72B_DQ42"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ42"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L4P_T0U_N6_DBC_AD7P_73 -#set_property PACKAGE_PIN J41 [get_ports "RLD3_72B_DQ44"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ44"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3N_T0L_N5_AD15N_73 -#set_property PACKAGE_PIN J40 [get_ports "RLD3_72B_DQ43"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ43"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L3P_T0L_N4_AD15P_73 -#set_property PACKAGE_PIN H42 [get_ports "RLD3_72B_DQ38"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ38"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2N_T0L_N3_73 -#set_property PACKAGE_PIN J42 [get_ports "RLD3_72B_DQ41"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_73 -#set_property IOSTANDARD SSTL12_DCI [get_ports "RLD3_72B_DQ41"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L2P_T0L_N2_73 -#set_property PACKAGE_PIN K42 [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_N"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1N_T0L_N1_DBC_73 -#set_property PACKAGE_PIN K41 [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 -#set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "RLD3_72B_QK4_P"] ;# Bank 73 VCCO - RLD3_VDDQ_1V2 - IO_L1P_T0L_N0_DBC_73 -#set_property PACKAGE_PIN A24 [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_N"] ;# Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72 -#set_property PACKAGE_PIN A25 [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA13_P"] ;# Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72 -#set_property PACKAGE_PIN A26 [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_N"] ;# Bank 72 VCCO - VADJ - IO_L23N_T3U_N9_72 -#set_property PACKAGE_PIN B27 [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA03_P"] ;# Bank 72 VCCO - VADJ - IO_L23P_T3U_N8_72 +# Jtag GPIOs goes to the FMC XM105 where the debug cable is connected (example Digilent HS2) set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; - set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; - set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] - set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; - -#set_property PACKAGE_PIN C24 [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_N"] ;# Bank 72 VCCO - VADJ - IO_L20N_T3L_N3_AD1N_72 -#set_property PACKAGE_PIN C25 [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA04_P"] ;# Bank 72 VCCO - VADJ - IO_L20P_T3L_N2_AD1P_72 -#set_property PACKAGE_PIN B22 [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_N"] ;# Bank 72 VCCO - VADJ - IO_L19N_T3L_N1_DBC_AD9N_72 -#set_property PACKAGE_PIN C23 [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA14_P"] ;# Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72 -#set_property PACKAGE_PIN C22 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T3U_N12_72 -#set_property PACKAGE_PIN C27 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T2U_N12_72 -#set_property PACKAGE_PIN D27 [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_N"] ;# Bank 72 VCCO - VADJ - IO_L18N_T2U_N11_AD2N_72 -#set_property PACKAGE_PIN E27 [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA08_P"] ;# Bank 72 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_72 -#set_property PACKAGE_PIN D26 [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_N"] ;# Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72 -#set_property PACKAGE_PIN E26 [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA09_P"] ;# Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72 -#set_property PACKAGE_PIN D24 [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L16N_T2U_N7_QBC_AD3N_72 -#set_property PACKAGE_PIN D25 [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L16P_T2U_N6_QBC_AD3P_72 -#set_property PACKAGE_PIN D22 [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_N"] ;# Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72 -#set_property PACKAGE_PIN E22 [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA06_P"] ;# Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72 -#set_property PACKAGE_PIN F25 [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72 -#set_property PACKAGE_PIN F26 [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA01_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72 -#set_property PACKAGE_PIN E23 [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_N"] ;# Bank 72 VCCO - VADJ - IO_L13N_T2L_N1_GC_QBC_72 -#set_property PACKAGE_PIN E24 [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank 72 VCCO - VADJ - IO_L13P_T2L_N0_GC_QBC_72 -#set_property PACKAGE_PIN G25 [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L12N_T1U_N11_GC_72 -#set_property PACKAGE_PIN G26 [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L12P_T1U_N10_GC_72 -#set_property PACKAGE_PIN F23 [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L11N_T1U_N9_GC_72 -#set_property PACKAGE_PIN F24 [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_CLK0_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L11P_T1U_N8_GC_72 -#set_property PACKAGE_PIN G22 [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_N"] ;# Bank 72 VCCO - VADJ - IO_L10N_T1U_N7_QBC_AD4N_72 -#set_property PACKAGE_PIN G23 [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_SYNC_M2C_P"] ;# Bank 72 VCCO - VADJ - IO_L10P_T1U_N6_QBC_AD4P_72 -#set_property PACKAGE_PIN G27 [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_N"] ;# Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72 -#set_property PACKAGE_PIN H27 [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA05_P"] ;# Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72 - set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; - set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] -#set_property PACKAGE_PIN H23 [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_N"] ;# Bank 72 VCCO - VADJ - IO_L7N_T1L_N1_QBC_AD13N_72 -#set_property PACKAGE_PIN H24 [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_REFCLK_C2M_P"] ;# Bank 72 VCCO - VADJ - IO_L7P_T1L_N0_QBC_AD13P_72 -#set_property PACKAGE_PIN H25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_T1U_N12_72 -#set_property PACKAGE_PIN J24 [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_72"] ;# Bank 72 VCCO - VADJ - IO_T0U_N12_VRP_72 -#set_property PACKAGE_PIN J25 [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_N"] ;# Bank 72 VCCO - VADJ - IO_L6N_T0U_N11_AD6N_72 -#set_property PACKAGE_PIN J26 [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA15_P"] ;# Bank 72 VCCO - VADJ - IO_L6P_T0U_N10_AD6P_72 -#set_property PACKAGE_PIN J27 [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_N"] ;# Bank 72 VCCO - VADJ - IO_L5N_T0U_N9_AD14N_72 -#set_property PACKAGE_PIN K27 [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA07_P"] ;# Bank 72 VCCO - VADJ - IO_L5P_T0U_N8_AD14P_72 -#set_property PACKAGE_PIN K22 [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_N"] ;# Bank 72 VCCO - VADJ - IO_L4N_T0U_N7_DBC_AD7N_72 -#set_property PACKAGE_PIN L23 [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA02_P"] ;# Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72 -#set_property PACKAGE_PIN K23 [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_N"] ;# Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72 -#set_property PACKAGE_PIN K24 [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 -#set_property IOSTANDARD LVDS [get_ports "FMCP_HSPC_LA16_P"] ;# Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72 -#set_property PACKAGE_PIN K26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2N_T0L_N3_72 -#set_property PACKAGE_PIN L26 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L2P_T0L_N2_72 -#set_property PACKAGE_PIN L24 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1N_T0L_N1_DBC_72 -#set_property PACKAGE_PIN L25 [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 -#set_property IOSTANDARD LVCMOSxx [get_ports "No Connect"] ;# Bank 72 VCCO - VADJ - IO_L1P_T0L_N0_DBC_72 -#set_property PACKAGE_PIN AV43 [get_ports "FMCP_HSPC_GBTCLK0_M2C_N"] ;# Bank 124 - MGTREFCLK0N_124 -#set_property PACKAGE_PIN AV42 [get_ports "FMCP_HSPC_GBTCLK0_M2C_P"] ;# Bank 124 - MGTREFCLK0P_124 -#set_property PACKAGE_PIN AT43 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1N_124 -#set_property PACKAGE_PIN AT42 [get_ports "No Connect"] ;# Bank 124 - MGTREFCLK1P_124 -#set_property PACKAGE_PIN BC54 [get_ports "FMCP_HSPC_DP0_M2C_N"] ;# Bank 124 - MGTYRXN0_124 -#set_property PACKAGE_PIN BB52 [get_ports "FMCP_HSPC_DP1_M2C_N"] ;# Bank 124 - MGTYRXN1_124 -#set_property PACKAGE_PIN BA54 [get_ports "FMCP_HSPC_DP2_M2C_N"] ;# Bank 124 - MGTYRXN2_124 -#set_property PACKAGE_PIN BA50 [get_ports "FMCP_HSPC_DP3_M2C_N"] ;# Bank 124 - MGTYRXN3_124 -#set_property PACKAGE_PIN BC53 [get_ports "FMCP_HSPC_DP0_M2C_P"] ;# Bank 124 - MGTYRXP0_124 -#set_property PACKAGE_PIN BB51 [get_ports "FMCP_HSPC_DP1_M2C_P"] ;# Bank 124 - MGTYRXP1_124 -#set_property PACKAGE_PIN BA53 [get_ports "FMCP_HSPC_DP2_M2C_P"] ;# Bank 124 - MGTYRXP2_124 -#set_property PACKAGE_PIN BA49 [get_ports "FMCP_HSPC_DP3_M2C_P"] ;# Bank 124 - MGTYRXP3_124 -#set_property PACKAGE_PIN BC49 [get_ports "FMCP_HSPC_DP0_C2M_N"] ;# Bank 124 - MGTYTXN0_124 -#set_property PACKAGE_PIN BC45 [get_ports "FMCP_HSPC_DP1_C2M_N"] ;# Bank 124 - MGTYTXN1_124 -#set_property PACKAGE_PIN BB47 [get_ports "FMCP_HSPC_DP2_C2M_N"] ;# Bank 124 - MGTYTXN2_124 -#set_property PACKAGE_PIN BA45 [get_ports "FMCP_HSPC_DP3_C2M_N"] ;# Bank 124 - MGTYTXN3_124 -#set_property PACKAGE_PIN BC48 [get_ports "FMCP_HSPC_DP0_C2M_P"] ;# Bank 124 - MGTYTXP0_124 -#set_property PACKAGE_PIN BC44 [get_ports "FMCP_HSPC_DP1_C2M_P"] ;# Bank 124 - MGTYTXP1_124 -#set_property PACKAGE_PIN BB46 [get_ports "FMCP_HSPC_DP2_C2M_P"] ;# Bank 124 - MGTYTXP2_124 -#set_property PACKAGE_PIN BA44 [get_ports "FMCP_HSPC_DP3_C2M_P"] ;# Bank 124 - MGTYTXP3_124 -#set_property PACKAGE_PIN AR41 [get_ports "FMCP_HSPC_GBTCLK1_M2C_N"] ;# Bank 125 - MGTREFCLK0N_125 -#set_property PACKAGE_PIN AR40 [get_ports "FMCP_HSPC_GBTCLK1_M2C_P"] ;# Bank 125 - MGTREFCLK0P_125 -#set_property PACKAGE_PIN AP43 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1N_125 -#set_property PACKAGE_PIN AP42 [get_ports "No Connect"] ;# Bank 125 - MGTREFCLK1P_125 -#set_property PACKAGE_PIN AU41 [get_ports "N22117206"] ;# Bank 125 - MGTRREF_LS -#set_property PACKAGE_PIN AY52 [get_ports "FMCP_HSPC_DP4_M2C_N"] ;# Bank 125 - MGTYRXN0_125 -#set_property PACKAGE_PIN AW54 [get_ports "FMCP_HSPC_DP5_M2C_N"] ;# Bank 125 - MGTYRXN1_125 -#set_property PACKAGE_PIN AW50 [get_ports "FMCP_HSPC_DP6_M2C_N"] ;# Bank 125 - MGTYRXN2_125 -#set_property PACKAGE_PIN AV52 [get_ports "FMCP_HSPC_DP7_M2C_N"] ;# Bank 125 - MGTYRXN3_125 -#set_property PACKAGE_PIN AY51 [get_ports "FMCP_HSPC_DP4_M2C_P"] ;# Bank 125 - MGTYRXP0_125 -#set_property PACKAGE_PIN AW53 [get_ports "FMCP_HSPC_DP5_M2C_P"] ;# Bank 125 - MGTYRXP1_125 -#set_property PACKAGE_PIN AW49 [get_ports "FMCP_HSPC_DP6_M2C_P"] ;# Bank 125 - MGTYRXP2_125 -#set_property PACKAGE_PIN AV51 [get_ports "FMCP_HSPC_DP7_M2C_P"] ;# Bank 125 - MGTYRXP3_125 -#set_property PACKAGE_PIN AY47 [get_ports "FMCP_HSPC_DP4_C2M_N"] ;# Bank 125 - MGTYTXN0_125 -#set_property PACKAGE_PIN AW45 [get_ports "FMCP_HSPC_DP5_C2M_N"] ;# Bank 125 - MGTYTXN1_125 -#set_property PACKAGE_PIN AV47 [get_ports "FMCP_HSPC_DP6_C2M_N"] ;# Bank 125 - MGTYTXN2_125 -#set_property PACKAGE_PIN AU45 [get_ports "FMCP_HSPC_DP7_C2M_N"] ;# Bank 125 - MGTYTXN3_125 -#set_property PACKAGE_PIN AY46 [get_ports "FMCP_HSPC_DP4_C2M_P"] ;# Bank 125 - MGTYTXP0_125 -#set_property PACKAGE_PIN AW44 [get_ports "FMCP_HSPC_DP5_C2M_P"] ;# Bank 125 - MGTYTXP1_125 -#set_property PACKAGE_PIN AV46 [get_ports "FMCP_HSPC_DP6_C2M_P"] ;# Bank 125 - MGTYTXP2_125 -#set_property PACKAGE_PIN AU44 [get_ports "FMCP_HSPC_DP7_C2M_P"] ;# Bank 125 - MGTYTXP3_125 -#set_property PACKAGE_PIN AN41 [get_ports "FMCP_HSPC_GBTCLK2_M2C_N"] ;# Bank 126 - MGTREFCLK0N_126 -#set_property PACKAGE_PIN AN40 [get_ports "FMCP_HSPC_GBTCLK2_M2C_P"] ;# Bank 126 - MGTREFCLK0P_126 -#set_property PACKAGE_PIN AM43 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1N_126 -#set_property PACKAGE_PIN AM42 [get_ports "No Connect"] ;# Bank 126 - MGTREFCLK1P_126 -#set_property PACKAGE_PIN AU54 [get_ports "FMCP_HSPC_DP8_M2C_N"] ;# Bank 126 - MGTYRXN0_126 -#set_property PACKAGE_PIN AT52 [get_ports "FMCP_HSPC_DP9_M2C_N"] ;# Bank 126 - MGTYRXN1_126 -#set_property PACKAGE_PIN AR54 [get_ports "FMCP_HSPC_DP10_M2C_N"] ;# Bank 126 - MGTYRXN2_126 -#set_property PACKAGE_PIN AP52 [get_ports "FMCP_HSPC_DP11_M2C_N"] ;# Bank 126 - MGTYRXN3_126 -#set_property PACKAGE_PIN AU53 [get_ports "FMCP_HSPC_DP8_M2C_P"] ;# Bank 126 - MGTYRXP0_126 -#set_property PACKAGE_PIN AT51 [get_ports "FMCP_HSPC_DP9_M2C_P"] ;# Bank 126 - MGTYRXP1_126 -#set_property PACKAGE_PIN AR53 [get_ports "FMCP_HSPC_DP10_M2C_P"] ;# Bank 126 - MGTYRXP2_126 -#set_property PACKAGE_PIN AP51 [get_ports "FMCP_HSPC_DP11_M2C_P"] ;# Bank 126 - MGTYRXP3_126 -#set_property PACKAGE_PIN AU49 [get_ports "FMCP_HSPC_DP8_C2M_N"] ;# Bank 126 - MGTYTXN0_126 -#set_property PACKAGE_PIN AT47 [get_ports "FMCP_HSPC_DP9_C2M_N"] ;# Bank 126 - MGTYTXN1_126 -#set_property PACKAGE_PIN AR49 [get_ports "FMCP_HSPC_DP10_C2M_N"] ;# Bank 126 - MGTYTXN2_126 -#set_property PACKAGE_PIN AR45 [get_ports "FMCP_HSPC_DP11_C2M_N"] ;# Bank 126 - MGTYTXN3_126 -#set_property PACKAGE_PIN AU48 [get_ports "FMCP_HSPC_DP8_C2M_P"] ;# Bank 126 - MGTYTXP0_126 -#set_property PACKAGE_PIN AT46 [get_ports "FMCP_HSPC_DP9_C2M_P"] ;# Bank 126 - MGTYTXP1_126 -#set_property PACKAGE_PIN AR48 [get_ports "FMCP_HSPC_DP10_C2M_P"] ;# Bank 126 - MGTYTXP2_126 -#set_property PACKAGE_PIN AR44 [get_ports "FMCP_HSPC_DP11_C2M_P"] ;# Bank 126 - MGTYTXP3_126 -#set_property PACKAGE_PIN AL41 [get_ports "FMCP_HSPC_GBTCLK3_M2C_N"] ;# Bank 127 - MGTREFCLK0N_127 -#set_property PACKAGE_PIN AL40 [get_ports "FMCP_HSPC_GBTCLK3_M2C_P"] ;# Bank 127 - MGTREFCLK0P_127 -#set_property PACKAGE_PIN AK43 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1N_127 -#set_property PACKAGE_PIN AK42 [get_ports "No Connect"] ;# Bank 127 - MGTREFCLK1P_127 -#set_property PACKAGE_PIN AN54 [get_ports "FMCP_HSPC_DP12_M2C_N"] ;# Bank 127 - MGTYRXN0_127 -#set_property PACKAGE_PIN AN50 [get_ports "FMCP_HSPC_DP13_M2C_N"] ;# Bank 127 - MGTYRXN1_127 -#set_property PACKAGE_PIN AM52 [get_ports "FMCP_HSPC_DP14_M2C_N"] ;# Bank 127 - MGTYRXN2_127 -#set_property PACKAGE_PIN AL54 [get_ports "FMCP_HSPC_DP15_M2C_N"] ;# Bank 127 - MGTYRXN3_127 -#set_property PACKAGE_PIN AN53 [get_ports "FMCP_HSPC_DP12_M2C_P"] ;# Bank 127 - MGTYRXP0_127 -#set_property PACKAGE_PIN AN49 [get_ports "FMCP_HSPC_DP13_M2C_P"] ;# Bank 127 - MGTYRXP1_127 -#set_property PACKAGE_PIN AM51 [get_ports "FMCP_HSPC_DP14_M2C_P"] ;# Bank 127 - MGTYRXP2_127 -#set_property PACKAGE_PIN AL53 [get_ports "FMCP_HSPC_DP15_M2C_P"] ;# Bank 127 - MGTYRXP3_127 -#set_property PACKAGE_PIN AP47 [get_ports "FMCP_HSPC_DP12_C2M_N"] ;# Bank 127 - MGTYTXN0_127 -#set_property PACKAGE_PIN AN45 [get_ports "FMCP_HSPC_DP13_C2M_N"] ;# Bank 127 - MGTYTXN1_127 -#set_property PACKAGE_PIN AM47 [get_ports "FMCP_HSPC_DP14_C2M_N"] ;# Bank 127 - MGTYTXN2_127 -#set_property PACKAGE_PIN AL45 [get_ports "FMCP_HSPC_DP15_C2M_N"] ;# Bank 127 - MGTYTXN3_127 -#set_property PACKAGE_PIN AP46 [get_ports "FMCP_HSPC_DP12_C2M_P"] ;# Bank 127 - MGTYTXP0_127 -#set_property PACKAGE_PIN AN44 [get_ports "FMCP_HSPC_DP13_C2M_P"] ;# Bank 127 - MGTYTXP1_127 -#set_property PACKAGE_PIN AM46 [get_ports "FMCP_HSPC_DP14_C2M_P"] ;# Bank 127 - MGTYTXP2_127 -#set_property PACKAGE_PIN AL44 [get_ports "FMCP_HSPC_DP15_C2M_P"] ;# Bank 127 - MGTYTXP3_127 -#set_property PACKAGE_PIN AJ41 [get_ports "FMCP_HSPC_GBTCLK4_M2C_N"] ;# Bank 128 - MGTREFCLK0N_128 -#set_property PACKAGE_PIN AJ40 [get_ports "FMCP_HSPC_GBTCLK4_M2C_P"] ;# Bank 128 - MGTREFCLK0P_128 -#set_property PACKAGE_PIN AH43 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1N_128 -#set_property PACKAGE_PIN AH42 [get_ports "No Connect"] ;# Bank 128 - MGTREFCLK1P_128 -#set_property PACKAGE_PIN AL50 [get_ports "FMCP_HSPC_DP16_M2C_N"] ;# Bank 128 - MGTYRXN0_128 -#set_property PACKAGE_PIN AK52 [get_ports "FMCP_HSPC_DP17_M2C_N"] ;# Bank 128 - MGTYRXN1_128 -#set_property PACKAGE_PIN AJ54 [get_ports "FMCP_HSPC_DP18_M2C_N"] ;# Bank 128 - MGTYRXN2_128 -#set_property PACKAGE_PIN AH52 [get_ports "FMCP_HSPC_DP19_M2C_N"] ;# Bank 128 - MGTYRXN3_128 -#set_property PACKAGE_PIN AL49 [get_ports "FMCP_HSPC_DP16_M2C_P"] ;# Bank 128 - MGTYRXP0_128 -#set_property PACKAGE_PIN AK51 [get_ports "FMCP_HSPC_DP17_M2C_P"] ;# Bank 128 - MGTYRXP1_128 -#set_property PACKAGE_PIN AJ53 [get_ports "FMCP_HSPC_DP18_M2C_P"] ;# Bank 128 - MGTYRXP2_128 -#set_property PACKAGE_PIN AH51 [get_ports "FMCP_HSPC_DP19_M2C_P"] ;# Bank 128 - MGTYRXP3_128 -#set_property PACKAGE_PIN AK47 [get_ports "FMCP_HSPC_DP16_C2M_N"] ;# Bank 128 - MGTYTXN0_128 -#set_property PACKAGE_PIN AJ49 [get_ports "FMCP_HSPC_DP17_C2M_N"] ;# Bank 128 - MGTYTXN1_128 -#set_property PACKAGE_PIN AJ45 [get_ports "FMCP_HSPC_DP18_C2M_N"] ;# Bank 128 - MGTYTXN2_128 -#set_property PACKAGE_PIN AH47 [get_ports "FMCP_HSPC_DP19_C2M_N"] ;# Bank 128 - MGTYTXN3_128 -#set_property PACKAGE_PIN AK46 [get_ports "FMCP_HSPC_DP16_C2M_P"] ;# Bank 128 - MGTYTXP0_128 -#set_property PACKAGE_PIN AJ48 [get_ports "FMCP_HSPC_DP17_C2M_P"] ;# Bank 128 - MGTYTXP1_128 -#set_property PACKAGE_PIN AJ44 [get_ports "FMCP_HSPC_DP18_C2M_P"] ;# Bank 128 - MGTYTXP2_128 -#set_property PACKAGE_PIN AH46 [get_ports "FMCP_HSPC_DP19_C2M_P"] ;# Bank 128 - MGTYTXP3_128 -#set_property PACKAGE_PIN AG41 [get_ports "FMCP_HSPC_GBTCLK5_M2C_N"] ;# Bank 129 - MGTREFCLK0N_129 -#set_property PACKAGE_PIN AG40 [get_ports "FMCP_HSPC_GBTCLK5_M2C_P"] ;# Bank 129 - MGTREFCLK0P_129 -#set_property PACKAGE_PIN AF43 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1N_129 -#set_property PACKAGE_PIN AF42 [get_ports "No Connect"] ;# Bank 129 - MGTREFCLK1P_129 -#set_property PACKAGE_PIN AE41 [get_ports "N21075880"] ;# Bank 129 - MGTRREF_LC -#set_property PACKAGE_PIN AG54 [get_ports "FMCP_HSPC_DP20_M2C_N"] ;# Bank 129 - MGTYRXN0_129 -#set_property PACKAGE_PIN AF52 [get_ports "FMCP_HSPC_DP21_M2C_N"] ;# Bank 129 - MGTYRXN1_129 -#set_property PACKAGE_PIN AE54 [get_ports "FMCP_HSPC_DP22_M2C_N"] ;# Bank 129 - MGTYRXN2_129 -#set_property PACKAGE_PIN AE50 [get_ports "FMCP_HSPC_DP23_M2C_N"] ;# Bank 129 - MGTYRXN3_129 -#set_property PACKAGE_PIN AG53 [get_ports "FMCP_HSPC_DP20_M2C_P"] ;# Bank 129 - MGTYRXP0_129 -#set_property PACKAGE_PIN AF51 [get_ports "FMCP_HSPC_DP21_M2C_P"] ;# Bank 129 - MGTYRXP1_129 -#set_property PACKAGE_PIN AE53 [get_ports "FMCP_HSPC_DP22_M2C_P"] ;# Bank 129 - MGTYRXP2_129 -#set_property PACKAGE_PIN AE49 [get_ports "FMCP_HSPC_DP23_M2C_P"] ;# Bank 129 - MGTYRXP3_129 -#set_property PACKAGE_PIN AG49 [get_ports "FMCP_HSPC_DP20_C2M_N"] ;# Bank 129 - MGTYTXN0_129 -#set_property PACKAGE_PIN AG45 [get_ports "FMCP_HSPC_DP21_C2M_N"] ;# Bank 129 - MGTYTXN1_129 -#set_property PACKAGE_PIN AF47 [get_ports "FMCP_HSPC_DP22_C2M_N"] ;# Bank 129 - MGTYTXN2_129 -#set_property PACKAGE_PIN AE45 [get_ports "FMCP_HSPC_DP23_C2M_N"] ;# Bank 129 - MGTYTXN3_129 -#set_property PACKAGE_PIN AG48 [get_ports "FMCP_HSPC_DP20_C2M_P"] ;# Bank 129 - MGTYTXP0_129 -#set_property PACKAGE_PIN AG44 [get_ports "FMCP_HSPC_DP21_C2M_P"] ;# Bank 129 - MGTYTXP1_129 -#set_property PACKAGE_PIN AF46 [get_ports "FMCP_HSPC_DP22_C2M_P"] ;# Bank 129 - MGTYTXP2_129 -#set_property PACKAGE_PIN AE44 [get_ports "FMCP_HSPC_DP23_C2M_P"] ;# Bank 129 - MGTYTXP3_129 -#set_property PACKAGE_PIN AD43 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0N_130 -#set_property PACKAGE_PIN AD42 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK0P_130 -#set_property PACKAGE_PIN AC41 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1N_130 -#set_property PACKAGE_PIN AC40 [get_ports "No Connect"] ;# Bank 130 - MGTREFCLK1P_130 -#set_property PACKAGE_PIN AD52 [get_ports "GND"] ;# Bank 130 - MGTYRXN0_130 -#set_property PACKAGE_PIN AC54 [get_ports "GND"] ;# Bank 130 - MGTYRXN1_130 -#set_property PACKAGE_PIN AC50 [get_ports "GND"] ;# Bank 130 - MGTYRXN2_130 -#set_property PACKAGE_PIN AB52 [get_ports "GND"] ;# Bank 130 - MGTYRXN3_130 -#set_property PACKAGE_PIN AD51 [get_ports "GND"] ;# Bank 130 - MGTYRXP0_130 -#set_property PACKAGE_PIN AC53 [get_ports "GND"] ;# Bank 130 - MGTYRXP1_130 -#set_property PACKAGE_PIN AC49 [get_ports "GND"] ;# Bank 130 - MGTYRXP2_130 -#set_property PACKAGE_PIN AB51 [get_ports "GND"] ;# Bank 130 - MGTYRXP3_130 -#set_property PACKAGE_PIN AD47 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN0_130 -#set_property PACKAGE_PIN AC45 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN1_130 -#set_property PACKAGE_PIN AB47 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN2_130 -#set_property PACKAGE_PIN AA49 [get_ports "No Connect"] ;# Bank 130 - MGTYTXN3_130 -#set_property PACKAGE_PIN AD46 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP0_130 -#set_property PACKAGE_PIN AC44 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP1_130 -#set_property PACKAGE_PIN AB46 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP2_130 -#set_property PACKAGE_PIN AA48 [get_ports "No Connect"] ;# Bank 130 - MGTYTXP3_130 -#set_property PACKAGE_PIN AB43 [get_ports "QSFP4_SI570_CLOCK_N"] ;# Bank 131 - MGTREFCLK0N_131 -#set_property PACKAGE_PIN AB42 [get_ports "QSFP4_SI570_CLOCK_P"] ;# Bank 131 - MGTREFCLK0P_131 -#set_property PACKAGE_PIN AA41 [get_ports "SMA_REFCLK_INPUT_N"] ;# Bank 131 - MGTREFCLK1N_131 -#set_property PACKAGE_PIN AA40 [get_ports "SMA_REFCLK_INPUT_P"] ;# Bank 131 - MGTREFCLK1P_131 -#set_property PACKAGE_PIN AA54 [get_ports "QSFP4_RX1_N"] ;# Bank 131 - MGTYRXN0_131 -#set_property PACKAGE_PIN Y52 [get_ports "QSFP4_RX2_N"] ;# Bank 131 - MGTYRXN1_131 -#set_property PACKAGE_PIN W54 [get_ports "QSFP4_RX3_N"] ;# Bank 131 - MGTYRXN2_131 -#set_property PACKAGE_PIN V52 [get_ports "QSFP4_RX4_N"] ;# Bank 131 - MGTYRXN3_131 -#set_property PACKAGE_PIN AA53 [get_ports "QSFP4_RX1_P"] ;# Bank 131 - MGTYRXP0_131 -#set_property PACKAGE_PIN Y51 [get_ports "QSFP4_RX2_P"] ;# Bank 131 - MGTYRXP1_131 -#set_property PACKAGE_PIN W53 [get_ports "QSFP4_RX3_P"] ;# Bank 131 - MGTYRXP2_131 -#set_property PACKAGE_PIN V51 [get_ports "QSFP4_RX4_P"] ;# Bank 131 - MGTYRXP3_131 -#set_property PACKAGE_PIN AA45 [get_ports "QSFP4_TX1_N"] ;# Bank 131 - MGTYTXN0_131 -#set_property PACKAGE_PIN Y47 [get_ports "QSFP4_TX2_N"] ;# Bank 131 - MGTYTXN1_131 -#set_property PACKAGE_PIN W49 [get_ports "QSFP4_TX3_N"] ;# Bank 131 - MGTYTXN2_131 -#set_property PACKAGE_PIN W45 [get_ports "QSFP4_TX4_N"] ;# Bank 131 - MGTYTXN3_131 -#set_property PACKAGE_PIN AA44 [get_ports "QSFP4_TX1_P"] ;# Bank 131 - MGTYTXP0_131 -#set_property PACKAGE_PIN Y46 [get_ports "QSFP4_TX2_P"] ;# Bank 131 - MGTYTXP1_131 -#set_property PACKAGE_PIN W48 [get_ports "QSFP4_TX3_P"] ;# Bank 131 - MGTYTXP2_131 -#set_property PACKAGE_PIN W44 [get_ports "QSFP4_TX4_P"] ;# Bank 131 - MGTYTXP3_131 -#set_property PACKAGE_PIN Y43 [get_ports "QSFP3_SI570_CLOCK_N"] ;# Bank 132 - MGTREFCLK0N_132 -#set_property PACKAGE_PIN Y42 [get_ports "QSFP3_SI570_CLOCK_P"] ;# Bank 132 - MGTREFCLK0P_132 -#set_property PACKAGE_PIN W41 [get_ports "SI5328_CLOCK2_C_N"] ;# Bank 132 - MGTREFCLK1N_132 -#set_property PACKAGE_PIN W40 [get_ports "SI5328_CLOCK2_C_P"] ;# Bank 132 - MGTREFCLK1P_132 -#set_property PACKAGE_PIN U54 [get_ports "QSFP3_RX1_N"] ;# Bank 132 - MGTYRXN0_132 -#set_property PACKAGE_PIN U50 [get_ports "QSFP3_RX2_N"] ;# Bank 132 - MGTYRXN1_132 -#set_property PACKAGE_PIN T52 [get_ports "QSFP3_RX3_N"] ;# Bank 132 - MGTYRXN2_132 -#set_property PACKAGE_PIN R54 [get_ports "QSFP3_RX4_N"] ;# Bank 132 - MGTYRXN3_132 -#set_property PACKAGE_PIN U53 [get_ports "QSFP3_RX1_P"] ;# Bank 132 - MGTYRXP0_132 -#set_property PACKAGE_PIN U49 [get_ports "QSFP3_RX2_P"] ;# Bank 132 - MGTYRXP1_132 -#set_property PACKAGE_PIN T51 [get_ports "QSFP3_RX3_P"] ;# Bank 132 - MGTYRXP2_132 -#set_property PACKAGE_PIN R53 [get_ports "QSFP3_RX4_P"] ;# Bank 132 - MGTYRXP3_132 -#set_property PACKAGE_PIN V47 [get_ports "QSFP3_TX1_N"] ;# Bank 132 - MGTYTXN0_132 -#set_property PACKAGE_PIN U45 [get_ports "QSFP3_TX2_N"] ;# Bank 132 - MGTYTXN1_132 -#set_property PACKAGE_PIN T47 [get_ports "QSFP3_TX3_N"] ;# Bank 132 - MGTYTXN2_132 -#set_property PACKAGE_PIN R45 [get_ports "QSFP3_TX4_N"] ;# Bank 132 - MGTYTXN3_132 -#set_property PACKAGE_PIN V46 [get_ports "QSFP3_TX1_P"] ;# Bank 132 - MGTYTXP0_132 -#set_property PACKAGE_PIN U44 [get_ports "QSFP3_TX2_P"] ;# Bank 132 - MGTYTXP1_132 -#set_property PACKAGE_PIN T46 [get_ports "QSFP3_TX3_P"] ;# Bank 132 - MGTYTXP2_132 -#set_property PACKAGE_PIN R44 [get_ports "QSFP3_TX4_P"] ;# Bank 132 - MGTYTXP3_132 -#set_property PACKAGE_PIN V43 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK0N_133 -#set_property PACKAGE_PIN V42 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK0P_133 -#set_property PACKAGE_PIN U41 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK1N_133 -#set_property PACKAGE_PIN U40 [get_ports "No Connect"] ;# Bank 133 - MGTREFCLK1P_133 -#set_property PACKAGE_PIN N41 [get_ports "N22119065"] ;# Bank 133 - MGTRREF_LN -#set_property PACKAGE_PIN R50 [get_ports "GND"] ;# Bank 133 - MGTYRXN0_133 -#set_property PACKAGE_PIN P52 [get_ports "GND"] ;# Bank 133 - MGTYRXN1_133 -#set_property PACKAGE_PIN N54 [get_ports "GND"] ;# Bank 133 - MGTYRXN2_133 -#set_property PACKAGE_PIN M52 [get_ports "GND"] ;# Bank 133 - MGTYRXN3_133 -#set_property PACKAGE_PIN R49 [get_ports "GND"] ;# Bank 133 - MGTYRXP0_133 -#set_property PACKAGE_PIN P51 [get_ports "GND"] ;# Bank 133 - MGTYRXP1_133 -#set_property PACKAGE_PIN N53 [get_ports "GND"] ;# Bank 133 - MGTYRXP2_133 -#set_property PACKAGE_PIN M51 [get_ports "GND"] ;# Bank 133 - MGTYRXP3_133 -#set_property PACKAGE_PIN P47 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN0_133 -#set_property PACKAGE_PIN N49 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN1_133 -#set_property PACKAGE_PIN N45 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN2_133 -#set_property PACKAGE_PIN M47 [get_ports "No Connect"] ;# Bank 133 - MGTYTXN3_133 -#set_property PACKAGE_PIN P46 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP0_133 -#set_property PACKAGE_PIN N48 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP1_133 -#set_property PACKAGE_PIN N44 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP2_133 -#set_property PACKAGE_PIN M46 [get_ports "No Connect"] ;# Bank 133 - MGTYTXP3_133 -#set_property PACKAGE_PIN T43 [get_ports "QSFP2_SI570_CLOCK_N"] ;# Bank 134 - MGTREFCLK0N_134 -#set_property PACKAGE_PIN T42 [get_ports "QSFP2_SI570_CLOCK_P"] ;# Bank 134 - MGTREFCLK0P_134 -#set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 134 - MGTREFCLK1N_134 -#set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 134 - MGTREFCLK1P_134 -#set_property PACKAGE_PIN L54 [get_ports "QSFP2_RX1_N"] ;# Bank 134 - MGTYRXN0_134 -#set_property PACKAGE_PIN K52 [get_ports "QSFP2_RX2_N"] ;# Bank 134 - MGTYRXN1_134 -#set_property PACKAGE_PIN J54 [get_ports "QSFP2_RX3_N"] ;# Bank 134 - MGTYRXN2_134 -#set_property PACKAGE_PIN H52 [get_ports "QSFP2_RX4_N"] ;# Bank 134 - MGTYRXN3_134 -#set_property PACKAGE_PIN L53 [get_ports "QSFP2_RX1_P"] ;# Bank 134 - MGTYRXP0_134 -#set_property PACKAGE_PIN K51 [get_ports "QSFP2_RX2_P"] ;# Bank 134 - MGTYRXP1_134 -#set_property PACKAGE_PIN J53 [get_ports "QSFP2_RX3_P"] ;# Bank 134 - MGTYRXP2_134 -#set_property PACKAGE_PIN H51 [get_ports "QSFP2_RX4_P"] ;# Bank 134 - MGTYRXP3_134 -#set_property PACKAGE_PIN L49 [get_ports "QSFP2_TX1_N"] ;# Bank 134 - MGTYTXN0_134 -#set_property PACKAGE_PIN L45 [get_ports "QSFP2_TX2_N"] ;# Bank 134 - MGTYTXN1_134 -#set_property PACKAGE_PIN K47 [get_ports "QSFP2_TX3_N"] ;# Bank 134 - MGTYTXN2_134 -#set_property PACKAGE_PIN J49 [get_ports "QSFP2_TX4_N"] ;# Bank 134 - MGTYTXN3_134 -#set_property PACKAGE_PIN L48 [get_ports "QSFP2_TX1_P"] ;# Bank 134 - MGTYTXP0_134 -#set_property PACKAGE_PIN L44 [get_ports "QSFP2_TX2_P"] ;# Bank 134 - MGTYTXP1_134 -#set_property PACKAGE_PIN K46 [get_ports "QSFP2_TX3_P"] ;# Bank 134 - MGTYTXP2_134 -#set_property PACKAGE_PIN J48 [get_ports "QSFP2_TX4_P"] ;# Bank 134 - MGTYTXP3_134 -#set_property PACKAGE_PIN P43 [get_ports "QSFP1_SI570_CLOCK_N"] ;# Bank 135 - MGTREFCLK0N_135 -#set_property PACKAGE_PIN P42 [get_ports "QSFP1_SI570_CLOCK_P"] ;# Bank 135 - MGTREFCLK0P_135 -#set_property PACKAGE_PIN M43 [get_ports "No Connect"] ;# Bank 135 - MGTREFCLK1N_135 -#set_property PACKAGE_PIN M42 [get_ports "No Connect"] ;# Bank 135 - MGTREFCLK1P_135 -#set_property PACKAGE_PIN G54 [get_ports "QSFP1_RX1_N"] ;# Bank 135 - MGTYRXN0_135 -#set_property PACKAGE_PIN F52 [get_ports "QSFP1_RX2_N"] ;# Bank 135 - MGTYRXN1_135 -#set_property PACKAGE_PIN E54 [get_ports "QSFP1_RX3_N"] ;# Bank 135 - MGTYRXN2_135 -#set_property PACKAGE_PIN D52 [get_ports "QSFP1_RX4_N"] ;# Bank 135 - MGTYRXN3_135 -#set_property PACKAGE_PIN G53 [get_ports "QSFP1_RX1_P"] ;# Bank 135 - MGTYRXP0_135 -#set_property PACKAGE_PIN F51 [get_ports "QSFP1_RX2_P"] ;# Bank 135 - MGTYRXP1_135 -#set_property PACKAGE_PIN E53 [get_ports "QSFP1_RX3_P"] ;# Bank 135 - MGTYRXP2_135 -#set_property PACKAGE_PIN D51 [get_ports "QSFP1_RX4_P"] ;# Bank 135 - MGTYRXP3_135 -#set_property PACKAGE_PIN G49 [get_ports "QSFP1_TX1_N"] ;# Bank 135 - MGTYTXN0_135 -#set_property PACKAGE_PIN E49 [get_ports "QSFP1_TX2_N"] ;# Bank 135 - MGTYTXN1_135 -#set_property PACKAGE_PIN C49 [get_ports "QSFP1_TX3_N"] ;# Bank 135 - MGTYTXN2_135 -#set_property PACKAGE_PIN A50 [get_ports "QSFP1_TX4_N"] ;# Bank 135 - MGTYTXN3_135 -#set_property PACKAGE_PIN G48 [get_ports "QSFP1_TX1_P"] ;# Bank 135 - MGTYTXP0_135 -#set_property PACKAGE_PIN E48 [get_ports "QSFP1_TX2_P"] ;# Bank 135 - MGTYTXP1_135 -#set_property PACKAGE_PIN C48 [get_ports "QSFP1_TX3_P"] ;# Bank 135 - MGTYTXP2_135 -#set_property PACKAGE_PIN A49 [get_ports "QSFP1_TX4_P"] ;# Bank 135 - MGTYTXP3_135 -#set_property PACKAGE_PIN AV12 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK0N_224 -#set_property PACKAGE_PIN AV13 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK0P_224 -#set_property PACKAGE_PIN AT12 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK1N_224 -#set_property PACKAGE_PIN AT13 [get_ports "No Connect"] ;# Bank 224 - MGTREFCLK1P_224 -#set_property PACKAGE_PIN BC1 [get_ports "PCIE_EP_RX15_N"] ;# Bank 224 - MGTYRXN0_224 -#set_property PACKAGE_PIN BB3 [get_ports "PCIE_EP_RX14_N"] ;# Bank 224 - MGTYRXN1_224 -#set_property PACKAGE_PIN BA1 [get_ports "PCIE_EP_RX13_N"] ;# Bank 224 - MGTYRXN2_224 -#set_property PACKAGE_PIN BA5 [get_ports "PCIE_EP_RX12_N"] ;# Bank 224 - MGTYRXN3_224 -#set_property PACKAGE_PIN BC2 [get_ports "PCIE_EP_RX15_P"] ;# Bank 224 - MGTYRXP0_224 -#set_property PACKAGE_PIN BB4 [get_ports "PCIE_EP_RX14_P"] ;# Bank 224 - MGTYRXP1_224 -#set_property PACKAGE_PIN BA2 [get_ports "PCIE_EP_RX13_P"] ;# Bank 224 - MGTYRXP2_224 -#set_property PACKAGE_PIN BA6 [get_ports "PCIE_EP_RX12_P"] ;# Bank 224 - MGTYRXP3_224 -#set_property PACKAGE_PIN BC6 [get_ports "PCIE_EP_TX15_N"] ;# Bank 224 - MGTYTXN0_224 -#set_property PACKAGE_PIN BC10 [get_ports "PCIE_EP_TX14_N"] ;# Bank 224 - MGTYTXN1_224 -#set_property PACKAGE_PIN BB8 [get_ports "PCIE_EP_TX13_N"] ;# Bank 224 - MGTYTXN2_224 -#set_property PACKAGE_PIN BA10 [get_ports "PCIE_EP_TX12_N"] ;# Bank 224 - MGTYTXN3_224 -#set_property PACKAGE_PIN BC7 [get_ports "PCIE_EP_TX15_P"] ;# Bank 224 - MGTYTXP0_224 -#set_property PACKAGE_PIN BC11 [get_ports "PCIE_EP_TX14_P"] ;# Bank 224 - MGTYTXP1_224 -#set_property PACKAGE_PIN BB9 [get_ports "PCIE_EP_TX13_P"] ;# Bank 224 - MGTYTXP2_224 -#set_property PACKAGE_PIN BA11 [get_ports "PCIE_EP_TX12_P"] ;# Bank 224 - MGTYTXP3_224 -#set_property PACKAGE_PIN AR14 [get_ports "PCIE_CLK1_N"] ;# Bank 225 - MGTREFCLK0N_225 -#set_property PACKAGE_PIN AR15 [get_ports "PCIE_CLK1_P"] ;# Bank 225 - MGTREFCLK0P_225 -#set_property PACKAGE_PIN AP12 [get_ports "No Connect"] ;# Bank 225 - MGTREFCLK1N_225 -#set_property PACKAGE_PIN AP13 [get_ports "No Connect"] ;# Bank 225 - MGTREFCLK1P_225 -#set_property PACKAGE_PIN AU14 [get_ports "N22119509"] ;# Bank 225 - MGTRREF_RS -#set_property PACKAGE_PIN AY3 [get_ports "PCIE_EP_RX11_N"] ;# Bank 225 - MGTYRXN0_225 -#set_property PACKAGE_PIN AW1 [get_ports "PCIE_EP_RX10_N"] ;# Bank 225 - MGTYRXN1_225 -#set_property PACKAGE_PIN AW5 [get_ports "PCIE_EP_RX9_N"] ;# Bank 225 - MGTYRXN2_225 -#set_property PACKAGE_PIN AV3 [get_ports "PCIE_EP_RX8_N"] ;# Bank 225 - MGTYRXN3_225 -#set_property PACKAGE_PIN AY4 [get_ports "PCIE_EP_RX11_P"] ;# Bank 225 - MGTYRXP0_225 -#set_property PACKAGE_PIN AW2 [get_ports "PCIE_EP_RX10_P"] ;# Bank 225 - MGTYRXP1_225 -#set_property PACKAGE_PIN AW6 [get_ports "PCIE_EP_RX9_P"] ;# Bank 225 - MGTYRXP2_225 -#set_property PACKAGE_PIN AV4 [get_ports "PCIE_EP_RX8_P"] ;# Bank 225 - MGTYRXP3_225 -#set_property PACKAGE_PIN AY8 [get_ports "PCIE_EP_TX11_N"] ;# Bank 225 - MGTYTXN0_225 -#set_property PACKAGE_PIN AW10 [get_ports "PCIE_EP_TX10_N"] ;# Bank 225 - MGTYTXN1_225 -#set_property PACKAGE_PIN AV8 [get_ports "PCIE_EP_TX9_N"] ;# Bank 225 - MGTYTXN2_225 -#set_property PACKAGE_PIN AU6 [get_ports "PCIE_EP_TX8_N"] ;# Bank 225 - MGTYTXN3_225 -#set_property PACKAGE_PIN AY9 [get_ports "PCIE_EP_TX11_P"] ;# Bank 225 - MGTYTXP0_225 -#set_property PACKAGE_PIN AW11 [get_ports "PCIE_EP_TX10_P"] ;# Bank 225 - MGTYTXP1_225 -#set_property PACKAGE_PIN AV9 [get_ports "PCIE_EP_TX9_P"] ;# Bank 225 - MGTYTXP2_225 -#set_property PACKAGE_PIN AU7 [get_ports "PCIE_EP_TX8_P"] ;# Bank 225 - MGTYTXP3_225 -#set_property PACKAGE_PIN AN14 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK0N_226 -#set_property PACKAGE_PIN AN15 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK0P_226 -#set_property PACKAGE_PIN AM12 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK1N_226 -#set_property PACKAGE_PIN AM13 [get_ports "No Connect"] ;# Bank 226 - MGTREFCLK1P_226 -#set_property PACKAGE_PIN AU1 [get_ports "PCIE_EP_RX7_N"] ;# Bank 226 - MGTYRXN0_226 -#set_property PACKAGE_PIN AT3 [get_ports "PCIE_EP_RX6_N"] ;# Bank 226 - MGTYRXN1_226 -#set_property PACKAGE_PIN AR1 [get_ports "PCIE_EP_RX5_N"] ;# Bank 226 - MGTYRXN2_226 -#set_property PACKAGE_PIN AP3 [get_ports "PCIE_EP_RX4_N"] ;# Bank 226 - MGTYRXN3_226 -#set_property PACKAGE_PIN AU2 [get_ports "PCIE_EP_RX7_P"] ;# Bank 226 - MGTYRXP0_226 -#set_property PACKAGE_PIN AT4 [get_ports "PCIE_EP_RX6_P"] ;# Bank 226 - MGTYRXP1_226 -#set_property PACKAGE_PIN AR2 [get_ports "PCIE_EP_RX5_P"] ;# Bank 226 - MGTYRXP2_226 -#set_property PACKAGE_PIN AP4 [get_ports "PCIE_EP_RX4_P"] ;# Bank 226 - MGTYRXP3_226 -#set_property PACKAGE_PIN AU10 [get_ports "PCIE_EP_TX7_N"] ;# Bank 226 - MGTYTXN0_226 -#set_property PACKAGE_PIN AT8 [get_ports "PCIE_EP_TX6_N"] ;# Bank 226 - MGTYTXN1_226 -#set_property PACKAGE_PIN AR6 [get_ports "PCIE_EP_TX5_N"] ;# Bank 226 - MGTYTXN2_226 -#set_property PACKAGE_PIN AR10 [get_ports "PCIE_EP_TX4_N"] ;# Bank 226 - MGTYTXN3_226 -#set_property PACKAGE_PIN AU11 [get_ports "PCIE_EP_TX7_P"] ;# Bank 226 - MGTYTXP0_226 -#set_property PACKAGE_PIN AT9 [get_ports "PCIE_EP_TX6_P"] ;# Bank 226 - MGTYTXP1_226 -#set_property PACKAGE_PIN AR7 [get_ports "PCIE_EP_TX5_P"] ;# Bank 226 - MGTYTXP2_226 -#set_property PACKAGE_PIN AR11 [get_ports "PCIE_EP_TX4_P"] ;# Bank 226 - MGTYTXP3_226 -#set_property PACKAGE_PIN AL14 [get_ports "PCIE_CLK2_N"] ;# Bank 227 - MGTREFCLK0N_227 -#set_property PACKAGE_PIN AL15 [get_ports "PCIE_CLK2_P"] ;# Bank 227 - MGTREFCLK0P_227 -#set_property PACKAGE_PIN AK12 [get_ports "No Connect"] ;# Bank 227 - MGTREFCLK1N_227 -#set_property PACKAGE_PIN AK13 [get_ports "No Connect"] ;# Bank 227 - MGTREFCLK1P_227 -#set_property PACKAGE_PIN AN1 [get_ports "PCIE_EP_RX3_N"] ;# Bank 227 - MGTYRXN0_227 -#set_property PACKAGE_PIN AN5 [get_ports "PCIE_EP_RX2_N"] ;# Bank 227 - MGTYRXN1_227 -#set_property PACKAGE_PIN AM3 [get_ports "PCIE_EP_RX1_N"] ;# Bank 227 - MGTYRXN2_227 -#set_property PACKAGE_PIN AL1 [get_ports "PCIE_EP_RX0_N"] ;# Bank 227 - MGTYRXN3_227 -#set_property PACKAGE_PIN AN2 [get_ports "PCIE_EP_RX3_P"] ;# Bank 227 - MGTYRXP0_227 -#set_property PACKAGE_PIN AN6 [get_ports "PCIE_EP_RX2_P"] ;# Bank 227 - MGTYRXP1_227 -#set_property PACKAGE_PIN AM4 [get_ports "PCIE_EP_RX1_P"] ;# Bank 227 - MGTYRXP2_227 -#set_property PACKAGE_PIN AL2 [get_ports "PCIE_EP_RX0_P"] ;# Bank 227 - MGTYRXP3_227 -#set_property PACKAGE_PIN AP8 [get_ports "PCIE_EP_TX3_N"] ;# Bank 227 - MGTYTXN0_227 -#set_property PACKAGE_PIN AN10 [get_ports "PCIE_EP_TX2_N"] ;# Bank 227 - MGTYTXN1_227 -#set_property PACKAGE_PIN AM8 [get_ports "PCIE_EP_TX1_N"] ;# Bank 227 - MGTYTXN2_227 -#set_property PACKAGE_PIN AL10 [get_ports "PCIE_EP_TX0_N"] ;# Bank 227 - MGTYTXN3_227 -#set_property PACKAGE_PIN AP9 [get_ports "PCIE_EP_TX3_P"] ;# Bank 227 - MGTYTXP0_227 -#set_property PACKAGE_PIN AN11 [get_ports "PCIE_EP_TX2_P"] ;# Bank 227 - MGTYTXP1_227 -#set_property PACKAGE_PIN AM9 [get_ports "PCIE_EP_TX1_P"] ;# Bank 227 - MGTYTXP2_227 -#set_property PACKAGE_PIN AL11 [get_ports "PCIE_EP_TX0_P"] ;# Bank 227 - MGTYTXP3_227 -#set_property PACKAGE_PIN AJ14 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK0N_228 -#set_property PACKAGE_PIN AJ15 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK0P_228 -#set_property PACKAGE_PIN AH12 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK1N_228 -#set_property PACKAGE_PIN AH13 [get_ports "No Connect"] ;# Bank 228 - MGTREFCLK1P_228 -#set_property PACKAGE_PIN AL5 [get_ports "GND"] ;# Bank 228 - MGTYRXN0_228 -#set_property PACKAGE_PIN AK3 [get_ports "GND"] ;# Bank 228 - MGTYRXN1_228 -#set_property PACKAGE_PIN AJ1 [get_ports "GND"] ;# Bank 228 - MGTYRXN2_228 -#set_property PACKAGE_PIN AH3 [get_ports "GND"] ;# Bank 228 - MGTYRXN3_228 -#set_property PACKAGE_PIN AL6 [get_ports "GND"] ;# Bank 228 - MGTYRXP0_228 -#set_property PACKAGE_PIN AK4 [get_ports "GND"] ;# Bank 228 - MGTYRXP1_228 -#set_property PACKAGE_PIN AJ2 [get_ports "GND"] ;# Bank 228 - MGTYRXP2_228 -#set_property PACKAGE_PIN AH4 [get_ports "GND"] ;# Bank 228 - MGTYRXP3_228 -#set_property PACKAGE_PIN AK8 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN0_228 -#set_property PACKAGE_PIN AJ6 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN1_228 -#set_property PACKAGE_PIN AJ10 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN2_228 -#set_property PACKAGE_PIN AH8 [get_ports "No Connect"] ;# Bank 228 - MGTYTXN3_228 -#set_property PACKAGE_PIN AK9 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP0_228 -#set_property PACKAGE_PIN AJ7 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP1_228 -#set_property PACKAGE_PIN AJ11 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP2_228 -#set_property PACKAGE_PIN AH9 [get_ports "No Connect"] ;# Bank 228 - MGTYTXP3_228 -#set_property PACKAGE_PIN AG14 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK0N_229 -#set_property PACKAGE_PIN AG15 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK0P_229 -#set_property PACKAGE_PIN AF12 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK1N_229 -#set_property PACKAGE_PIN AF13 [get_ports "No Connect"] ;# Bank 229 - MGTREFCLK1P_229 -#set_property PACKAGE_PIN AE14 [get_ports "N22480070"] ;# Bank 229 - MGTRREF_RC -#set_property PACKAGE_PIN AG1 [get_ports "GND"] ;# Bank 229 - MGTYRXN0_229 -#set_property PACKAGE_PIN AF3 [get_ports "GND"] ;# Bank 229 - MGTYRXN1_229 -#set_property PACKAGE_PIN AE1 [get_ports "GND"] ;# Bank 229 - MGTYRXN2_229 -#set_property PACKAGE_PIN AE5 [get_ports "GND"] ;# Bank 229 - MGTYRXN3_229 -#set_property PACKAGE_PIN AG2 [get_ports "GND"] ;# Bank 229 - MGTYRXP0_229 -#set_property PACKAGE_PIN AF4 [get_ports "GND"] ;# Bank 229 - MGTYRXP1_229 -#set_property PACKAGE_PIN AE2 [get_ports "GND"] ;# Bank 229 - MGTYRXP2_229 -#set_property PACKAGE_PIN AE6 [get_ports "GND"] ;# Bank 229 - MGTYRXP3_229 -#set_property PACKAGE_PIN AG6 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN0_229 -#set_property PACKAGE_PIN AG10 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN1_229 -#set_property PACKAGE_PIN AF8 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN2_229 -#set_property PACKAGE_PIN AE10 [get_ports "No Connect"] ;# Bank 229 - MGTYTXN3_229 -#set_property PACKAGE_PIN AG7 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP0_229 -#set_property PACKAGE_PIN AG11 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP1_229 -#set_property PACKAGE_PIN AF9 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP2_229 -#set_property PACKAGE_PIN AE11 [get_ports "No Connect"] ;# Bank 229 - MGTYTXP3_229 -#set_property PACKAGE_PIN AD12 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK0N_230 -#set_property PACKAGE_PIN AD13 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK0P_230 -#set_property PACKAGE_PIN AC14 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK1N_230 -#set_property PACKAGE_PIN AC15 [get_ports "No Connect"] ;# Bank 230 - MGTREFCLK1P_230 -#set_property PACKAGE_PIN AD3 [get_ports "GND"] ;# Bank 230 - MGTYRXN0_230 -#set_property PACKAGE_PIN AC1 [get_ports "GND"] ;# Bank 230 - MGTYRXN1_230 -#set_property PACKAGE_PIN AC5 [get_ports "GND"] ;# Bank 230 - MGTYRXN2_230 -#set_property PACKAGE_PIN AB3 [get_ports "GND"] ;# Bank 230 - MGTYRXN3_230 -#set_property PACKAGE_PIN AD4 [get_ports "GND"] ;# Bank 230 - MGTYRXP0_230 -#set_property PACKAGE_PIN AC2 [get_ports "GND"] ;# Bank 230 - MGTYRXP1_230 -#set_property PACKAGE_PIN AC6 [get_ports "GND"] ;# Bank 230 - MGTYRXP2_230 -#set_property PACKAGE_PIN AB4 [get_ports "GND"] ;# Bank 230 - MGTYRXP3_230 -#set_property PACKAGE_PIN AD8 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN0_230 -#set_property PACKAGE_PIN AC10 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN1_230 -#set_property PACKAGE_PIN AB8 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN2_230 -#set_property PACKAGE_PIN AA6 [get_ports "No Connect"] ;# Bank 230 - MGTYTXN3_230 -#set_property PACKAGE_PIN AD9 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP0_230 -#set_property PACKAGE_PIN AC11 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP1_230 -#set_property PACKAGE_PIN AB9 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP2_230 -#set_property PACKAGE_PIN AA7 [get_ports "No Connect"] ;# Bank 230 - MGTYTXP3_230 -#set_property PACKAGE_PIN AB12 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK0N_231 -#set_property PACKAGE_PIN AB13 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK0P_231 -#set_property PACKAGE_PIN AA14 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK1N_231 -#set_property PACKAGE_PIN AA15 [get_ports "No Connect"] ;# Bank 231 - MGTREFCLK1P_231 -#set_property PACKAGE_PIN AA1 [get_ports "GND"] ;# Bank 231 - MGTYRXN0_231 -#set_property PACKAGE_PIN Y3 [get_ports "GND"] ;# Bank 231 - MGTYRXN1_231 -#set_property PACKAGE_PIN W1 [get_ports "GND"] ;# Bank 231 - MGTYRXN2_231 -#set_property PACKAGE_PIN V3 [get_ports "GND"] ;# Bank 231 - MGTYRXN3_231 -#set_property PACKAGE_PIN AA2 [get_ports "GND"] ;# Bank 231 - MGTYRXP0_231 -#set_property PACKAGE_PIN Y4 [get_ports "GND"] ;# Bank 231 - MGTYRXP1_231 -#set_property PACKAGE_PIN W2 [get_ports "GND"] ;# Bank 231 - MGTYRXP2_231 -#set_property PACKAGE_PIN V4 [get_ports "GND"] ;# Bank 231 - MGTYRXP3_231 -#set_property PACKAGE_PIN AA10 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN0_231 -#set_property PACKAGE_PIN Y8 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN1_231 -#set_property PACKAGE_PIN W6 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN2_231 -#set_property PACKAGE_PIN W10 [get_ports "No Connect"] ;# Bank 231 - MGTYTXN3_231 -#set_property PACKAGE_PIN AA11 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP0_231 -#set_property PACKAGE_PIN Y9 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP1_231 -#set_property PACKAGE_PIN W7 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP2_231 -#set_property PACKAGE_PIN W11 [get_ports "No Connect"] ;# Bank 231 - MGTYTXP3_231 -#set_property PACKAGE_PIN Y12 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK0N_232 -#set_property PACKAGE_PIN Y13 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK0P_232 -#set_property PACKAGE_PIN W14 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK1N_232 -#set_property PACKAGE_PIN W15 [get_ports "No Connect"] ;# Bank 232 - MGTREFCLK1P_232 -#set_property PACKAGE_PIN U1 [get_ports "GND"] ;# Bank 232 - MGTYRXN0_232 -#set_property PACKAGE_PIN U5 [get_ports "GND"] ;# Bank 232 - MGTYRXN1_232 -#set_property PACKAGE_PIN T3 [get_ports "GND"] ;# Bank 232 - MGTYRXN2_232 -#set_property PACKAGE_PIN R1 [get_ports "GND"] ;# Bank 232 - MGTYRXN3_232 -#set_property PACKAGE_PIN U2 [get_ports "GND"] ;# Bank 232 - MGTYRXP0_232 -#set_property PACKAGE_PIN U6 [get_ports "GND"] ;# Bank 232 - MGTYRXP1_232 -#set_property PACKAGE_PIN T4 [get_ports "GND"] ;# Bank 232 - MGTYRXP2_232 -#set_property PACKAGE_PIN R2 [get_ports "GND"] ;# Bank 232 - MGTYRXP3_232 -#set_property PACKAGE_PIN V8 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN0_232 -#set_property PACKAGE_PIN U10 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN1_232 -#set_property PACKAGE_PIN T8 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN2_232 -#set_property PACKAGE_PIN R10 [get_ports "No Connect"] ;# Bank 232 - MGTYTXN3_232 -#set_property PACKAGE_PIN V9 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP0_232 -#set_property PACKAGE_PIN U11 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP1_232 -#set_property PACKAGE_PIN T9 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP2_232 -#set_property PACKAGE_PIN R11 [get_ports "No Connect"] ;# Bank 232 - MGTYTXP3_232 -#set_property PACKAGE_PIN V12 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK0N_233 -#set_property PACKAGE_PIN V13 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK0P_233 -#set_property PACKAGE_PIN U14 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK1N_233 -#set_property PACKAGE_PIN U15 [get_ports "No Connect"] ;# Bank 233 - MGTREFCLK1P_233 -#set_property PACKAGE_PIN N14 [get_ports "N22119643"] ;# Bank 233 - MGTRREF_RN -#set_property PACKAGE_PIN R5 [get_ports "GND"] ;# Bank 233 - MGTYRXN0_233 -#set_property PACKAGE_PIN P3 [get_ports "GND"] ;# Bank 233 - MGTYRXN1_233 -#set_property PACKAGE_PIN N1 [get_ports "GND"] ;# Bank 233 - MGTYRXN2_233 -#set_property PACKAGE_PIN M3 [get_ports "GND"] ;# Bank 233 - MGTYRXN3_233 -#set_property PACKAGE_PIN R6 [get_ports "GND"] ;# Bank 233 - MGTYRXP0_233 -#set_property PACKAGE_PIN P4 [get_ports "GND"] ;# Bank 233 - MGTYRXP1_233 -#set_property PACKAGE_PIN N2 [get_ports "GND"] ;# Bank 233 - MGTYRXP2_233 -#set_property PACKAGE_PIN M4 [get_ports "GND"] ;# Bank 233 - MGTYRXP3_233 -#set_property PACKAGE_PIN P8 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN0_233 -#set_property PACKAGE_PIN N6 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN1_233 -#set_property PACKAGE_PIN N10 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN2_233 -#set_property PACKAGE_PIN M8 [get_ports "No Connect"] ;# Bank 233 - MGTYTXN3_233 -#set_property PACKAGE_PIN P9 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP0_233 -#set_property PACKAGE_PIN N7 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP1_233 -#set_property PACKAGE_PIN N11 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP2_233 -#set_property PACKAGE_PIN M9 [get_ports "No Connect"] ;# Bank 233 - MGTYTXP3_233 -#set_property PACKAGE_PIN T12 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK0N_234 -#set_property PACKAGE_PIN T13 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK0P_234 -#set_property PACKAGE_PIN R14 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK1N_234 -#set_property PACKAGE_PIN R15 [get_ports "No Connect"] ;# Bank 234 - MGTREFCLK1P_234 -#set_property PACKAGE_PIN L1 [get_ports "GND"] ;# Bank 234 - MGTYRXN0_234 -#set_property PACKAGE_PIN K3 [get_ports "GND"] ;# Bank 234 - MGTYRXN1_234 -#set_property PACKAGE_PIN J1 [get_ports "GND"] ;# Bank 234 - MGTYRXN2_234 -#set_property PACKAGE_PIN H3 [get_ports "GND"] ;# Bank 234 - MGTYRXN3_234 -#set_property PACKAGE_PIN L2 [get_ports "GND"] ;# Bank 234 - MGTYRXP0_234 -#set_property PACKAGE_PIN K4 [get_ports "GND"] ;# Bank 234 - MGTYRXP1_234 -#set_property PACKAGE_PIN J2 [get_ports "GND"] ;# Bank 234 - MGTYRXP2_234 -#set_property PACKAGE_PIN H4 [get_ports "GND"] ;# Bank 234 - MGTYRXP3_234 -#set_property PACKAGE_PIN L6 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN0_234 -#set_property PACKAGE_PIN L10 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN1_234 -#set_property PACKAGE_PIN K8 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN2_234 -#set_property PACKAGE_PIN J6 [get_ports "No Connect"] ;# Bank 234 - MGTYTXN3_234 -#set_property PACKAGE_PIN L7 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP0_234 -#set_property PACKAGE_PIN L11 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP1_234 -#set_property PACKAGE_PIN K9 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP2_234 -#set_property PACKAGE_PIN J7 [get_ports "No Connect"] ;# Bank 234 - MGTYTXP3_234 -#set_property PACKAGE_PIN P12 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK0N_235 -#set_property PACKAGE_PIN P13 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK0P_235 -#set_property PACKAGE_PIN M12 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK1N_235 -#set_property PACKAGE_PIN M13 [get_ports "No Connect"] ;# Bank 235 - MGTREFCLK1P_235 -#set_property PACKAGE_PIN G1 [get_ports "GND"] ;# Bank 235 - MGTYRXN0_235 -#set_property PACKAGE_PIN F3 [get_ports "GND"] ;# Bank 235 - MGTYRXN1_235 -#set_property PACKAGE_PIN E1 [get_ports "GND"] ;# Bank 235 - MGTYRXN2_235 -#set_property PACKAGE_PIN D3 [get_ports "GND"] ;# Bank 235 - MGTYRXN3_235 -#set_property PACKAGE_PIN G2 [get_ports "GND"] ;# Bank 235 - MGTYRXP0_235 -#set_property PACKAGE_PIN F4 [get_ports "GND"] ;# Bank 235 - MGTYRXP1_235 -#set_property PACKAGE_PIN E2 [get_ports "GND"] ;# Bank 235 - MGTYRXP2_235 -#set_property PACKAGE_PIN D4 [get_ports "GND"] ;# Bank 235 - MGTYRXP3_235 -#set_property PACKAGE_PIN G6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN0_235 -#set_property PACKAGE_PIN E6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN1_235 -#set_property PACKAGE_PIN C6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN2_235 -#set_property PACKAGE_PIN A5 [get_ports "No Connect"] ;# Bank 235 - MGTYTXN3_235 -#set_property PACKAGE_PIN G7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP0_235 -#set_property PACKAGE_PIN E7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP1_235 -#set_property PACKAGE_PIN C7 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP2_235 -#set_property PACKAGE_PIN A6 [get_ports "No Connect"] ;# Bank 235 - MGTYTXP3_235 - +# Clock diff @ 100MHz set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] @@ -1804,7 +76,6 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] -#set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] -#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] -#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] -#connect_debug_port dbg_hub/clk [get_nets clk] +# Active high reset +set_property PACKAGE_PIN BM29 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset] diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl index d0a83baf..f29e56fc 100644 --- a/target/xilinx/flavor_vanilla/scripts/run.tcl +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -19,12 +19,13 @@ read_ip $::env(XILINX_IP_PATHS) # Contraints files selection switch $::env(XILINX_BOARD) { - "genesys2" - "kc705" - "vc707" - "vcu128" - "zcu102" { + "genesys2" - "vcu128" { import_files -fileset constrs_1 -norecurse constraints/cheshire.xdc import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc } default { - exit 1 + puts "Unknown board $::env(XILINX_BOARD)" + exit 1 } } diff --git a/target/xilinx/flavor_vanilla/sim/sim.mk b/target/xilinx/flavor_vanilla/sim/sim.mk index 72449d83..2153b9bd 100644 --- a/target/xilinx/flavor_vanilla/sim/sim.mk +++ b/target/xilinx/flavor_vanilla/sim/sim.mk @@ -4,55 +4,57 @@ # # Cyril Koenig -CHS_XIL_SIM_DIR ?= $(CHS_XIL_DIR)/sim +CHS_XIL_SIM_DIR ?= $(CHS_XIL_DIR)/flavor_vanilla/sim XILINX_SIMLIB_PATH ?= /home/$(USER)/xlib_questa-2022.3_vivado-2022.1 SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin -ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) +# Compile script for each IP model +chs-ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) -# Pre-generated/modified example projects (contain the simulation top level) -ifneq ($(filter xlnx_mig_ddr4,$(ips-names)),) - ip-example-projects := xlnx_mig_ddr4_ex -endif -ifneq ($(filter xlnx_mig_7_ddr3,$(ips-names)),) - ip-example-projects := xlnx_mig_7_ddr3_ex -endif +# Getting the DDR model requires exporting the Vivado example project for the controller's IP +chs-ddr-example-project := $(filter xlnx_mig_,$(ips-names))_ex +chs-ddr-sim-script := $(CHS_XIL_SIM_DIR)/ips/$(chs-ddr-example-projects)/questa/compile.do -ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects))) +chs-vivado-env-sim := $(VIVADOENV) \ + XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ + SIMULATOR_PATH=$(SIMULATOR_PATH) \ + GCC_PATH=$(GCC_PATH) \ + VIVADO_PROJECT=$(CHS_XIL_DIR)/flavor_vanilla/chesire.xpr +chs-xil-vlog-args := -suppress 2583 -suppress 13314 -VIVADOENV_SIM := $(VIVADOENV) \ - XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ - SIMULATOR_PATH=$(SIMULATOR_PATH) \ - GCC_PATH=$(GCC_PATH) \ - VIVADO_PROJECT=../${PROJECT}.xpr -VLOG_ARGS := -suppress 2583 -suppress 13314 - -# Fetch example projects at IIS (containing SRAM behavioral models) -$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: - mkdir -p $(CHS_XIL_SIM_DIR)/ips - tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips - -# Generate simulation libraries +# First generate the generic Xilinx simulation libraries for questa $(XILINX_SIMLIB_PATH)/modelsim.ini: cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" -# +# Then generate the IP models for the project cheshire.xpr $(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do: mkdir -p $(CHS_XIL_SIM_DIR)/ips cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" -$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl: - $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@ - -chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl +# Get the DRAM simulation models +$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + # First create the example project + cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example" + # Then export the simulation models + cd $(CHS_XIL_SIM_DIR) && $(chs-vivado-env-sim) VIVADO_PROJECT=$(CHS_XIL_SIM_DIR)/ips/$*_ex/$*_ex.xpr $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_example_simulation" + # And replace the DUT by cheshire top + patch $(CHS_XIL_SIM_DIR)/ips/$*_ex/imports/sim_tb_top.sv $(CHS_XIL_SIM_DIR)/sim_tb_top.diff + +# Export the Cheshire questa compile script +$(CHS_XIL_SIM_DIR)/add_sources_vsim.tcl: + $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(chs-xil-vlog-args)" > $@ + +# Run all +chs-xil-sim: $(CHS_XIL_DIR)/flavor_vanilla/cheshire.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(chs-ddr-sim-script) $(chs-ip-sim-scripts) $(CHS_XIL_SIM_DIR)/add_sources_vsim.tcl mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR) chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini cd $(CHS_XIL_SIM_DIR) && IPS="$(ips-names)" questa-2022.3 vsim -work work -do "run_simulation.tcl" chs-xil-clean-sim: - cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini + cd $(CHS_XIL_SIM_DIR) && rm -rf *.log questa_lib work transcript vsim.wlf vsim_cheshire.tcl .Xil modelsim.ini .PHONY: clean-sim sim