From 3dca6cf8afb4a7043209e879349f406a3fe99737 Mon Sep 17 00:00:00 2001 From: Paul Scheffler Date: Wed, 6 Mar 2024 13:24:04 +0100 Subject: [PATCH] target/xilinx: Clean up flow, multi-board support, add VCU128 (#105) * hw: Add `RegAdaptMemCut` inside `axi_to_reg_v2` * Bender.yml: Update `register_interface` * target/xilinx: Clean up flow, multi-board support, add VCU128 * sw: Update CVA6 SDK, add multi-device-tree flow * doc: Add new Xilinx target features * target/xilinx: Make utility targets weekly depend on input files * util: Add HS2 OpenOCD script, amend docs * doc: Some cleanup * nonfree: Update * doc: Fix typo --------- Co-authored-by: Cyril Koenig --- .github/workflows/build.yml | 2 +- .gitignore | 7 + Bender.lock | 4 +- Bender.yml | 4 +- cheshire.mk | 9 +- docs/tg/xilinx.md | 71 +- docs/um/arch.md | 1 + hw/cheshire_pkg.sv | 2 + hw/cheshire_soc.sv | 3 +- sw/boot/{cheshire.dts => cheshire.dtsi} | 12 +- sw/boot/cheshire.genesys2.dts | 18 + sw/boot/cheshire.vcu128.dts | 27 + sw/deps/cva6-sdk | 2 +- sw/sw.mk | 2 +- target/xilinx/.gitignore | 23 - target/xilinx/Makefile | 71 -- target/xilinx/constraints/cheshire.xdc | 136 +--- target/xilinx/constraints/genesys2.xdc | 527 ++++---------- target/xilinx/constraints/vcu128.xdc | 80 +++ target/xilinx/scripts/common.tcl | 142 ++++ target/xilinx/scripts/impl_ip.tcl | 172 +++++ target/xilinx/scripts/impl_sys.tcl | 73 ++ target/xilinx/scripts/program.tcl | 28 - target/xilinx/scripts/prologue.tcl | 17 - target/xilinx/scripts/run.tcl | 80 --- target/xilinx/scripts/util/flash.tcl | 50 ++ target/xilinx/scripts/util/program.tcl | 20 + target/xilinx/scripts/write_cfgmem.tcl | 28 - target/xilinx/src/cheshire_top_xilinx.sv | 655 ++++++++---------- target/xilinx/src/dram_wrapper_xilinx.sv | 363 ++++++++++ .../ips/genesys2.mig7s.prj} | 11 +- target/xilinx/src/phy_definitions.svh | 83 +++ target/xilinx/xilinx.mk | 91 +++ target/xilinx/xilinx/.gitignore | 5 - target/xilinx/xilinx/common.mk | 27 - target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile | 6 - .../xilinx/xlnx_mig_7_ddr3/mig_kc705.prj | 200 ------ .../xilinx/xlnx_mig_7_ddr3/mig_vc707.prj | 203 ------ .../xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl | 26 - .../xilinx/xlnx_protocol_checker/Makefile | 6 - .../xilinx/xlnx_protocol_checker/tcl/run.tcl | 40 -- util/{openocd.cfg => openocd.common.tcl} | 23 +- util/openocd.genesys2.tcl | 14 + util/openocd.hs2.tcl | 14 + 44 files changed, 1685 insertions(+), 1693 deletions(-) rename sw/boot/{cheshire.dts => cheshire.dtsi} (94%) create mode 100644 sw/boot/cheshire.genesys2.dts create mode 100644 sw/boot/cheshire.vcu128.dts delete mode 100644 target/xilinx/.gitignore delete mode 100644 target/xilinx/Makefile create mode 100644 target/xilinx/constraints/vcu128.xdc create mode 100644 target/xilinx/scripts/common.tcl create mode 100644 target/xilinx/scripts/impl_ip.tcl create mode 100644 target/xilinx/scripts/impl_sys.tcl delete mode 100644 target/xilinx/scripts/program.tcl delete mode 100644 target/xilinx/scripts/prologue.tcl delete mode 100644 target/xilinx/scripts/run.tcl create mode 100644 target/xilinx/scripts/util/flash.tcl create mode 100644 target/xilinx/scripts/util/program.tcl delete mode 100644 target/xilinx/scripts/write_cfgmem.tcl create mode 100644 target/xilinx/src/dram_wrapper_xilinx.sv rename target/xilinx/{xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj => src/ips/genesys2.mig7s.prj} (97%) mode change 100755 => 100644 create mode 100644 target/xilinx/src/phy_definitions.svh create mode 100644 target/xilinx/xilinx.mk delete mode 100644 target/xilinx/xilinx/.gitignore delete mode 100644 target/xilinx/xilinx/common.mk delete mode 100644 target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile delete mode 100644 target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj delete mode 100644 target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj delete mode 100644 target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl delete mode 100644 target/xilinx/xilinx/xlnx_protocol_checker/Makefile delete mode 100644 target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl rename util/{openocd.cfg => openocd.common.tcl} (61%) create mode 100644 util/openocd.genesys2.tcl create mode 100644 util/openocd.hs2.tcl diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 691d5878..54e3f087 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -13,7 +13,7 @@ jobs: build: strategy: matrix: - target: [sw, hw, sim, xilinx] + target: [sw, hw, sim] fail-fast: false runs-on: ubuntu-22.04 steps: diff --git a/.gitignore b/.gitignore index 6ff6a9bf..b0a00098 100644 --- a/.gitignore +++ b/.gitignore @@ -23,6 +23,7 @@ site/ *.gpth *.o *.a +*.dtb sw/deps/.patched # Test models @@ -35,3 +36,9 @@ target/sim/vsim/modelsim.ini target/sim/vsim/transcript target/sim/vsim/vsim.wlf target/sim/vsim/work/ + +# Xilinx generated files +target/xilinx/build +target/xilinx/out +target/xilinx/scripts/add_sources.* +vivado* diff --git a/Bender.lock b/Bender.lock index 3166ff8d..9b97dfe4 100644 --- a/Bender.lock +++ b/Bender.lock @@ -145,8 +145,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c - version: 0.4.2 + revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19 + version: 0.4.3 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index c460f28f..9daf8779 100644 --- a/Bender.yml +++ b/Bender.yml @@ -26,7 +26,7 @@ dependencies: iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 } unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 } @@ -52,5 +52,7 @@ sources: - target: all(fpga, xilinx) files: + - target/xilinx/src/phy_definitions.svh + - target/xilinx/src/dram_wrapper_xilinx.sv - target/xilinx/src/fan_ctrl.sv - target/xilinx/src/cheshire_top_xilinx.sv diff --git a/cheshire.mk b/cheshire.mk index 43cc8282..dd7c4e34 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -53,7 +53,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= dafd3c1 +CHS_NONFREE_COMMIT ?= 99973e8 chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -159,10 +159,7 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl # FPGA Flow # ############# -$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: $(CHS_ROOT)/Bender.yml - $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@ - -CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl +include target/xilinx/xilinx.mk ################################# # Phonies (KEEP AT END OF FILE) # @@ -170,7 +167,7 @@ CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl .PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all -CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL) +CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) chs-all: $(CHS_ALL) chs-sw-all: $(CHS_SW_ALL) diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md index 3d688beb..1a220414 100644 --- a/docs/tg/xilinx.md +++ b/docs/tg/xilinx.md @@ -7,23 +7,23 @@ This page describes how to map Cheshire on Xilinx FPGAs to *execute baremetal pr We currently provide working setups for: - Digilent Genesys 2 with Vivado `>= 2020.2` +- Xilinx VCU128 with Vivado `>= 2020.2` We are working on support for more boards in the future. ## Implementation -Since the implementation steps and available features vary between boards, we provide instructions and document available features for each. - -### Digilent Genesys 2 - -Generate the bitstream `target/xilinx/out/cheshire_top_xilinx.bit` by running: +Generate the bitstream `target/xilinx/out/cheshire..bit` for your desired board by running: ``` -make -C target/xilinx +make chs-xilinx- ``` -Before flashing the bitstream to your device, take note of the position of onboard switches, which control important functionality: +Since available features vary between boards, we provide further documentation for each. +### Digilent Genesys 2 (`genesys2`) + +Before flashing the bitstream to your device, take note of the position of onboard switches, which control important functionality: | Switch | Function | | ------ | ------------------------------------------------| @@ -33,14 +33,41 @@ Before flashing the bitstream to your device, take note of the position of onboa The reset, JTAG TAP, UART, I2C, and VGA are all connected to their onboard logic or ports. The UART has *no flow control*. The microSD slot is connected to chip select 0 of the SPI host peripheral. Serial link and GPIOs are currently not available. +### Xilinx VCU128 (`vcu128`) + +Since there are no switches on this board, the boot mode must be selected using Virtual IOs (see [Virtual IOs](#virtual_ios) below). + +This board provides a JTAG TAP and a UART without flow control connected to onboard ports. The SPI host peripheral connects to the `STARTUPE3` IP block, which provides access to the onboard flash. All other IOs are currently not available. + +### Virtual IOs + +To provide control of important IO without direct access to onboard switches, we provide the following virtual IOs on all boards, which may be controlled at runtime through Vivado's hardware manager: + + | Virtual IO | Function | + | ------------------- | -------------------------------------------| + | `vio_reset` | Assert reset (active high) | + | `vio_boot_mode` | Externally override boot mode | + | `vio_boot_mode_sel` | Whether to override boot mode from FPGA IO | + +### Inserting ILA probes + +For analysis and debugging purposes, integrated logic analyzer (ILA) probes may be added to the design's RTL description. You can do this either by marking signals with appropriate attributes or by using the `ila` macro from the `phy_definitions.svh` header: + +```systemverilog +/* Option 1 */ (* dont_touch = "yes" *) (* mark_debug = "true" *) logic mysignal; +/* Option 2 */ `ila(my_ila_name, mysignal) +``` + ## Debugging with OpenOCD To establish a debug bridge over JTAG, ensure the target is in a debuggable state (for example by resetting into the idle boot mode 0) and launch OpenOCD with: ``` -openocd -f $(bender path ariane)/corev_apu/fpga/ariane.cfg +openocd -f util/openocd..tcl ``` +If multiple JTAG adapters are connected to your debugging machine, you may have to extend the script to specify desired adapter's serial number. + In another shell, launch a RISC-V GDB session attaching to OpenOCD: ``` @@ -55,7 +82,7 @@ You can now interrupt (Ctrl+C), inspect, and repoint execution with GDB as usual ## Running Baremetal Code -Baremetal code can be preloaded through JTAG using OpenOCD and GDB or loaded from an SD Card. In principle, other interfaces may also be used to boot if the board provides them, but no setups are available for this. +Baremetal code can be preloaded through JTAG using OpenOCD and GDB or loaded from a bootable device, such as an SD card. In principle, other interfaces may also be used to boot if the board provides them, but no setups are available for this. First, connect to UART using a serial communication program like minicom: @@ -78,9 +105,9 @@ continue You should see `Hello World!` output printed on the UART. -### Boot from SD Card +### Boot from SD card (`genesys2` only) -First, build an up-to-date a disk image for your desired binary. For `helloworld`: +First, build an up-to-date GPT disk image for your desired binary. For `helloworld`: ``` make sw/tests/helloworld.gpt.bin @@ -97,6 +124,20 @@ The second command only ensures correctness of the partition layout; it moves th Insert your SD card and reset into boot mode 1. You should see a `Hello World!` UART output. +### Boot from onboard flash (`vcu128` only) + +Build a GPT disk image for your desired binary as explained above, then flash it to your board's flash. For `helloworld`: + +``` +make CHS_XILINX_FLASH_BIN=sw/tests/helloworld.gpt.bin chs-xilinx-flash- +``` + +Flashing an image should take about 10 minutes. *Note that after flashing, your board's bitstream must be reprogrammed* as it is overridden for this task. + +If the image given by `CHS_XILINX_FLASH_BIN` does not exist, `make` will attempt to build it before flashing. If `CHS_XILINX_FLASH_BIN` is not provided, the target assumes the board's Linux image by default. + +After flashing your disk image and reprogramming your bitstream, reset into boot mode 2. For `helloworld`, you should again see a `Hello World!` UART output. + ## Booting Linux To boot Linux, we must load the *OpenSBI* firmware, which takes over M mode and launches the U-boot bootloader. U-boot then loads Linux. For more details, see [Boot Flow](../um/sw.md#boot-flow). @@ -108,17 +149,17 @@ git submodule update --init --recursive sw/deps/cva6-sdk cd sw/deps/cva6-sdk && make images ``` -In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card. +In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card or SPI flash. In this case, OpenSBI is loaded by a regular baremetal program called the [Zero-Stage Loader](../um/sw.md#zero-stage-loader) (ZSL). The [boot ROM](../um/sw.md#boot-rom) loads the ZSL from SD card, which then loads the device tree and firmware from other SD card partitions into memory and launches OpenSBI. -To create a full Linux disk image from the ZSL, device tree, firmware, and Linux, run: +To create a full Linux disk image from the ZSL, your board's device tree, the firmware, and Linux, run: ``` -make ${CHS_ROOT}/sw/boot/linux.gpt.bin +make ${CHS_ROOT}/sw/boot/linux..gpt.bin ``` -where `CHS_ROOT` is the root of the Cheshire repository. Flash this image to an SD card as you did in the previous section, then insert the SD card and reset into boot mode 1. You should first see the ZSL print on the UART: +where `CHS_ROOT` is the root of the Cheshire repository. Flash this image to an SD card or SPI flash as described in the preceding sections, then reset into the boot mode corresponding for your boot medium. You should first see the ZSL print on the UART: ``` /\___/\ Boot mode: 1 diff --git a/docs/um/arch.md b/docs/um/arch.md index d56f4bff..41413ce2 100644 --- a/docs/um/arch.md +++ b/docs/um/arch.md @@ -151,6 +151,7 @@ The internal interconnect exposes the following parameters: | `RegMax(Read|Write)Txns` | `dw_bt` | Max. inflight transactions at Regbus AMO filter | | `RegAmoNumCuts` | `aw_bt` | Number of timing cuts inside Regbus AMO filter | | `RegAmoPostCut` | `bit` | Whether to insert a cut after Regbus AMO filter | +| `RegAdaptMemCut` | `bit` | Whether to insert a cut inside AXI-to-Rb. adapter | | `(Axi|Reg)ExtNum(Mst|Slv)` | `0..15` | AXI4 and Regbus number of external Mgrs. or Subs. | | `(Axi|Reg)ExtNumRules` | `0..15` | AXI4 and Regbus number of external address rules | | `(Axi|Reg)ExtRegion*` | `doub_bt` | AXI4 and Regbus external address regions | diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 867bf981..93e764f0 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -105,6 +105,7 @@ package cheshire_pkg; dw_bt RegMaxWriteTxns; aw_bt RegAmoNumCuts; bit RegAmoPostCut; + bit RegAdaptMemCut; // External AXI ports (limited number of ports and rules) bit [MaxExtAxiMstWidth-1:0] AxiExtNumMst; bit [MaxExtAxiSlvWidth-1:0] AxiExtNumSlv; @@ -579,6 +580,7 @@ package cheshire_pkg; RegMaxWriteTxns : 8, RegAmoNumCuts : 1, RegAmoPostCut : 1, + RegAdaptMemCut : 1, // RTC RtcFreq : 32768, // Features diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index f6ba75ee..e87e7518 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -361,7 +361,8 @@ module cheshire_soc import cheshire_pkg::*; #( .AxiDataWidth ( Cfg.AxiDataWidth ), .AxiIdWidth ( AxiSlvIdWidth ), .AxiUserWidth ( Cfg.AxiUserWidth ), - .RegDataWidth ( 32'd32 ), + .RegDataWidth ( 32 ), + .CutMemReqs ( Cfg.RegAdaptMemCut ), .axi_req_t ( axi_slv_req_t ), .axi_rsp_t ( axi_slv_rsp_t ), .reg_req_t ( reg_req_t ), diff --git a/sw/boot/cheshire.dts b/sw/boot/cheshire.dtsi similarity index 94% rename from sw/boot/cheshire.dts rename to sw/boot/cheshire.dtsi index dbef5e50..76decc85 100644 --- a/sw/boot/cheshire.dts +++ b/sw/boot/cheshire.dtsi @@ -7,11 +7,13 @@ // Axel Vanoni /dts-v1/; + / { #address-cells = <2>; #size-cells = <2>; compatible = "eth,cheshire-dev"; model = "eth,cheshire"; + chosen { stdout-path = "/soc/serial@3002000:115200"; }; @@ -74,22 +76,16 @@ interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>; reg = <0x0 0x3003000 0x0 0x1000>; }; - spi@3004000 { + spi: spi@3004000 { compatible = "opentitan,spi-host", "lowrisc,spi"; interrupt-parent = <&PLIC0>; interrupts = <17 18>; reg = <0x0 0x3004000 0x0 0x1000>; + num-cs = <2>; clock-frequency = <50000000>; max-frequency = <25000000>; #address-cells = <1>; #size-cells = <0>; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <25000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; }; vga@3007000 { compatible = "eth,axi-vga"; diff --git a/sw/boot/cheshire.genesys2.dts b/sw/boot/cheshire.genesys2.dts new file mode 100644 index 00000000..43359a85 --- /dev/null +++ b/sw/boot/cheshire.genesys2.dts @@ -0,0 +1,18 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; // CS + spi-max-frequency = <25000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; diff --git a/sw/boot/cheshire.vcu128.dts b/sw/boot/cheshire.vcu128.dts new file mode 100644 index 00000000..6088d358 --- /dev/null +++ b/sw/boot/cheshire.vcu128.dts @@ -0,0 +1,27 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +/include/ "cheshire.dtsi" + +&spi { + boot-with = <1>; + nor@1 { + #address-cells = <0x1>; + #size-cells = <0x1>; + // Note : u-boot does not find mt25qu02g + compatible = "mt25qu02g", "jedec,spi-nor"; + reg = <0x1>; // CS + spi-max-frequency = <25000000>; + spi-rx-bus-width = <0x1>; + spi-tx-bus-width = <0x1>; + disable-wp; + partition@0 { + label = "all"; + reg = <0x0 0x6000000>; // 96 MB + read-only; + }; + }; +}; diff --git a/sw/deps/cva6-sdk b/sw/deps/cva6-sdk index 3b08b0ea..1d4ef36b 160000 --- a/sw/deps/cva6-sdk +++ b/sw/deps/cva6-sdk @@ -1 +1 @@ -Subproject commit 3b08b0ea40a259c13443c50e506e6998e73ae1f5 +Subproject commit 1d4ef36baba9ecc63528fa2c0f6fa49db8fb0fbb diff --git a/sw/sw.mk b/sw/sw.mk index 6a377a2f..89987310 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -140,7 +140,7 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*. CHS_CVA6_SDK_IMGS ?= $(addprefix $(CHS_SW_DIR)/deps/cva6-sdk/install64/,fw_payload.bin uImage) # Create full Linux disk image -$(CHS_SW_DIR)/boot/linux.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire.dtb $(CHS_CVA6_SDK_IMGS) +$(CHS_SW_DIR)/boot/linux.%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire.%.dtb $(CHS_CVA6_SDK_IMGS) truncate -s $(CHS_SW_DISK_SIZE) $@ sgdisk --clear -g --set-alignment=1 \ --new=1:64:96 --typecode=1:$(CHS_SW_ZSL_TGUID) \ diff --git a/target/xilinx/.gitignore b/target/xilinx/.gitignore deleted file mode 100644 index 96fd7f52..00000000 --- a/target/xilinx/.gitignore +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Nicole Narr -# Christopher Reinwardt - -*.log -*.jou -*.str -*.mif -*.xci -*.Xil/ -scripts/add_sources.tcl -cheshire.cache/ -cheshire.hw/ -cheshire.ioplanning/ -cheshire.ip_user_files/ -cheshire.runs/ -cheshire.sim/ -cheshire.xpr -out/ -reports/ diff --git a/target/xilinx/Makefile b/target/xilinx/Makefile deleted file mode 100644 index 2bc7d135..00000000 --- a/target/xilinx/Makefile +++ /dev/null @@ -1,71 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Nicole Narr -# Christopher Reinwardt - -PROJECT ?= cheshire -BOARD ?= genesys2 -XILINX_PART ?= xc7k325tffg900-2 -XILINX_BOARD ?= digilentinc.com:genesys2:part0:1.1 -XILINX_PORT ?= 3332 -XILINX_HOST ?= bordcomputer -FPGA_PATH ?= xilinx_tcf/Digilent/200300A8C60DB - -out := out -bit := $(out)/cheshire_top_xilinx.bit -mcs := $(out)/cheshire_top_xilinx.mcs -BIT ?= $(bit) - - -VIVADOENV ?= PROJECT=$(PROJECT) \ - BOARD=$(BOARD) \ - XILINX_PART=$(XILINX_PART) \ - XILINX_BOARD=$(XILINX_BOARD) \ - PORT=$(XILINX_PORT) \ - HOST=$(XILINX_HOST) \ - FPGA_PATH=$(FPGA_PATH) \ - BIT=$(BIT) - -# select IIS-internal tool commands if we run on IIS machines -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2022.1 vivado -else - VIVADO ?= vivado -endif - -VIVADOFLAGS ?= -nojournal -mode batch - -ip-dir := xilinx -ips := xlnx_mig_7_ddr3.xci - -all: $(mcs) - -# Generate mcs from bitstream -$(mcs): $(bit) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ - -$(bit): $(ips) - @mkdir -p $(out) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/prologue.tcl -source scripts/run.tcl - cp $(PROJECT).runs/impl_1/$(PROJECT)* ./$(out) - -$(ips): - @echo "Generating IP $(basename $@)" - cd $(ip-dir)/$(basename $@) && $(MAKE) clean && $(VIVADOENV) VIVADO="$(VIVADO)" $(MAKE) - cp $(ip-dir)/$(basename $@)/$(basename $@).srcs/sources_1/ip/$(basename $@)/$@ $@ - -gui: - @echo "Starting $(vivado) GUI" - @$(VIVADOENV) $(VIVADO) -nojournal -mode gui $(PROJECT).xpr & - -program: - @echo "Programming board $(BOARD) ($(XILINX_PART))" - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl - -clean: - rm -rf *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim - -.PHONY: - clean diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc index 398a8166..61c79a2c 100644 --- a/target/xilinx/constraints/cheshire.xdc +++ b/target/xilinx/constraints/cheshire.xdc @@ -4,67 +4,38 @@ # # Nicole Narr # Christopher Reinwardt +# Cyril Koenig +# Paul Scheffler -################### -# Global Settings # -################### +################# +# Clock routing # +################# -# Testmode is set to 0 during normal use -set_case_analysis 0 [get_ports test_mode_i] +# JTAG is on non-clock-capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] -# Preserve the output mux of the clock divider -set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports sys_reset*]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports sys_reset*]] -# The pin of which we get the 200 MHz single ended clock from the MIG -set MIG_CLK_SRC {i_dram/ui_clk} +# Remove avoid tc_clk_mux2 to use global clock routing +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux -##################### -# Timing Parameters # -##################### - -# 200 MHz FPGA diff clock -set FPGA_TCK 5.0 - -# 50 MHz SoC clock -set SOC_TCK 20.0 +######## +# JTAG # +######## -# 10 MHz JTAG clock +# 10 MHz (max) JTAG clock set JTAG_TCK 100.0 -# I2C High-speed mode is 3.2 Mb/s -set I2C_IO_SPEED 312.5 - -# UART speed is at most 5 Mb/s -set UART_IO_SPEED 200.0 - -########## -# Clocks # -########## - -# System Clock -create_generated_clock -name clk_soc -source [get_pins $MIG_CLK_SRC] -divide_by 4 [get_pins i_sys_clk_div/i_clk_bypass_mux/i_BUFGMUX/O] - # JTAG Clock create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] set_input_jitter clk_jtag 1.000 -################ -# Clock Groups # -################ - # JTAG Clock is asynchronous to all other clocks -set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag] - -####################### -# Placement Overrides # -####################### - -# Accept suboptimal BUFG-BUFG cascades -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i] - -######## -# JTAG # -######## +set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} set_input_delay -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] set_input_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}] @@ -75,79 +46,26 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK set_false_path -hold -from [get_ports jtag_trst_ni] -####### -# MIG # -####### - -set_max_delay -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] $FPGA_TCK -set_false_path -hold -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] - -######## -# SPIM # -######## - -set_input_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_input_delay -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] -set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] -set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] - -####### -# I2C # -####### - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] - -set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] -set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] - ######## # UART # ######## +# UART speed is at most 5 Mb/s +set UART_IO_SPEED 200.0 + set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i] set_false_path -hold -from [get_ports uart_rx_i] set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o] set_false_path -hold -to [get_ports uart_tx_o] -####### -# VGA # -####### - -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*] - -############ -# Switches # -############ - -set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* test_mode_i}] -set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* test_mode_i}] - -set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm] -set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm] - -set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* test_mode_i}] -set_false_path -hold -from [get_ports {boot_mode* fan_sw* test_mode_i}] - -set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] -set_false_path -hold -to [get_ports fan_pwm] - ######## # CDCs # ######## -# cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew -set_property KEEP_HIERARCHY SOFT [get_cells i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync] -set_false_path -hold -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK - -################### -# Reset Generator # -################### +# Disable hold checks on CDCs +set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}] -set_max_delay -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] $SOC_TCK -set_false_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index 7142b159..18debabc 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -1,29 +1,107 @@ -#### This file is a general .xdc for the Genesys 2 Rev. H -#### To use it in a project: -#### - uncomment the lines corresponding to used pins -#### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig +# Paul Scheffler + +############# +# Sys Clock # +############# + +# 200 MHz input clock +set SYS_TCK 5 +create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] + +# SoC clock is generated by clock wizard and its constraints +set SOC_TCK 20.0 +set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]] + +############ +# Switches # +############ + +# Testmode is set to 0 during normal use +set_case_analysis 0 [get_ports test_mode_i] + +set_input_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* test_mode_i}] +set_input_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* test_mode_i}] + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports fan_pwm] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports fan_pwm] + +set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* test_mode_i}] +set_false_path -hold -from [get_ports {boot_mode* fan_sw* test_mode_i}] + +set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm] +set_false_path -hold -to [get_ports fan_pwm] + +####### +# MIG # +####### + +# Dram axi clock : 200 MHz (defined by MIG constraints) +set MIG_TCK 5 + +# False-path incoming reset +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/aresetn] +set_false_path -hold -setup -through $MIG_RST_I + +# Constrain outgoing reset +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk_sync_rst] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK + +# Limit delay across DRAM CDC (hold already false-pathed) +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK + +####### +# VGA # +####### + +set_output_delay -min -clock $soc_clk [expr $SOC_TCK * 0.10] [get_ports vga*] +set_output_delay -max -clock $soc_clk [expr $SOC_TCK * 0.35] [get_ports vga*] + +######## +# SPIM # +######## + +set_input_delay -min -clock $soc_clk [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +set_input_delay -max -clock $soc_clk [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}] +# TODO: fix this by raising it back up... +set_output_delay -min -clock $soc_clk [expr 0.02 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] +set_output_delay -max -clock $soc_clk [expr 0.063 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}] + +####### +# I2C # +####### + +# I2C High-speed mode is 3.2 Mb/s +set I2C_IO_SPEED 312.5 + +set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}] +set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}] + +set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}] +set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] + +############### +# Assign Pins # +############### ## Clock Signal -set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n -set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p ## Buttons -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc -#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_0_15 Sch=btnd -#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L6P_T0_15 Sch=btnl -#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L24P_T3_17 Sch=btnr -#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_L24N_T3_17 Sch=btnu -set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_0_14 Sch=cpu_resetn - -## LEDs -#set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0] -#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1] -#set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2] -#set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L16P_T2_CSI_B_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L20N_T3_A07_D23_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L20P_T3_A08_D24_14 Sch=led[7] +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { sys_resetn }]; #IO_0_14 Sch=cpu_resetn ## Switches set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS12 } [get_ports { boot_mode_i[0] }]; #IO_0_17 Sch=sw[0] @@ -32,18 +110,13 @@ set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS12 } [get_ports { fan_sw set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[1] }]; #IO_L6P_T0_17 Sch=sw[3] set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[2] }]; #IO_L19P_T3_A22_15 Sch=sw[4] set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS12 } [get_ports { fan_sw[3] }]; #IO_25_15 Sch=sw[5] -#set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L10P_T1_D14_14 Sch=sw[6] set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { test_mode_i }]; #IO_L8P_T1_D11_14 Sch=sw[7] -## USB HIDs For Both Mouse and Keyboard -#set_property -dict { PACKAGE_PIN AD23 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk_0 }]; #IO_L12P_T1_MRCC_12 Sch=ps2_clk[0] -#set_property -dict { PACKAGE_PIN AE20 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data_0 }]; #IO_25_12 Sch=ps2_data[0] - -## UART +# UART set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L1P_T0_12 Sch=uart_rx_out set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_0_12 Sch=uart_tx_in -## SD Card +# SD Card set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { sd_cd_i }]; #IO_L8N_T1_D12_14 Sch=sd_cd set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd_o }]; #IO_L7N_T1_D10_14 Sch=sd_cmd set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { sd_d_io[0] }]; #IO_L10N_T1_D15_14 Sch=sd_dat[0] @@ -53,384 +126,40 @@ set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { sd_d_i set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { sd_reset_o }]; #IO_L12N_T1_MRCC_12 Sch=sd_reset set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { sd_sclk_o }]; #IO_L11P_T1_SRCC_14 Sch=sd_sclk -## Audio Codec -#set_property -dict { PACKAGE_PIN AH19 IOSTANDARD LVCMOS18 } [get_ports { aud_adc_sdata }]; #IO_L8N_T1_32 Sch=aud_adc_sdata -#set_property -dict { PACKAGE_PIN AD19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[0] }]; #IO_L10P_T1_32 Sch=aud_adr[0] -#set_property -dict { PACKAGE_PIN AG19 IOSTANDARD LVCMOS18 } [get_ports { aud_adr[1] }]; #IO_L8P_T1_32 Sch=aud_adr[1] -#set_property -dict { PACKAGE_PIN AG18 IOSTANDARD LVCMOS18 } [get_ports { aud_bclk }]; #IO_L11N_T1_SRCC_32 Sch=aud_bclk -#set_property -dict { PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18 } [get_ports { aud_dac_sdata }]; #IO_L7P_T1_32 Sch=aud_dac_sdata -#set_property -dict { PACKAGE_PIN AJ18 IOSTANDARD LVCMOS18 } [get_ports { aud_lrclk }]; #IO_L9P_T1_DQS_32 Sch=aud_lrclk -#set_property -dict { PACKAGE_PIN AK19 IOSTANDARD LVCMOS18 } [get_ports { aud_mclk }]; #IO_L7N_T1_32 Sch=aud_mclk -#set_property -dict { PACKAGE_PIN AE19 IOSTANDARD LVCMOS18 } [get_ports { aud_scl }]; #IO_L10N_T1_32 Sch=aud_scl -#set_property -dict { PACKAGE_PIN AF18 IOSTANDARD LVCMOS18 } [get_ports { aud_sda }]; #IO_L11P_T1_SRCC_32 Sch=aud_sda - -## Ethernet -#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb -#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc -#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio -#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n -#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb -#set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk -#set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { eth_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl -#set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0] -#set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1] -#set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2] -#set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { eth_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3] -#set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { eth_txck }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk -#set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0] -#set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1] -#set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2] -#set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3] -#set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { ETH_TX_EN }]; #IO_L20P_T3_33 Sch=eth_tx_en - -## VGA Connector -set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] -set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] -set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] -set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] -set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_b[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] - -set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] -set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] -set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] -set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] -set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_g[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] -set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_g[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] - -set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] -set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] -set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] -set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] -set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_r[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] - -set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L19P_T3_12 Sch=vga_hs -set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs - -## HDMI in -#set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L2P_T0_12 Sch=hdmi_rx_cec -#set_property -dict { PACKAGE_PIN AF28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_clk_n -#set_property -dict { PACKAGE_PIN AE28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L14P_T2_SRCC_13 Sch=hdmi_rx_clk_p -#set_property -dict { PACKAGE_PIN AH29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpa }]; #IO_L13N_T2_MRCC_13 Sch=hdmi_rx_hpa -#set_property -dict { PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L17P_T2_13 Sch=hdmi_rx_scl -#set_property -dict { PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_13 Sch=hdmi_rx_sda -#set_property -dict { PACKAGE_PIN AK26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L24N_T3_13 Sch=hdmi_rx_n[0] -#set_property -dict { PACKAGE_PIN AJ26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L24P_T3_13 Sch=hdmi_rx_p[0] -#set_property -dict { PACKAGE_PIN AG28 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L21N_T3_DQS_13 Sch=hdmi_rx_n[1] -#set_property -dict { PACKAGE_PIN AG27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L21P_T3_DQS_13 Sch=hdmi_rx_p[1] -#set_property -dict { PACKAGE_PIN AH27 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L22N_T3_13 Sch=hdmi_rx_n[2] -#set_property -dict { PACKAGE_PIN AH26 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L22P_T3_13 Sch=hdmi_rx_p[2] - -## HDMI out -#set_property -dict { PACKAGE_PIN Y24 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L1N_T0_12 Sch=hdmi_tx_cec -#set_property -dict { PACKAGE_PIN AB20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L6N_T0_VREF_12 Sch=hdmi_tx_clk_n -#set_property -dict { PACKAGE_PIN AA20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L6P_T0_12 Sch=hdmi_tx_clk_p -#set_property -dict { PACKAGE_PIN AG29 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L13P_T2_MRCC_13 Sch=hdmi_tx_hpd -#set_property -dict { PACKAGE_PIN AF27 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L23N_T3_13 Sch=hdmi_tx_scl -#set_property -dict { PACKAGE_PIN AF26 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L23P_T3_13 Sch=hdmi_tx_sda -#set_property -dict { PACKAGE_PIN AC21 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_12 Sch=hdmi_tx_n[0] -#set_property -dict { PACKAGE_PIN AC20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_12 Sch=hdmi_tx_p[0] -#set_property -dict { PACKAGE_PIN AA23 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L4N_T0_12 Sch=hdmi_tx_n[1] -#set_property -dict { PACKAGE_PIN AA22 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L4P_T0_12 Sch=hdmi_tx_p[1] -#set_property -dict { PACKAGE_PIN AC25 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L7N_T1_12 Sch=hdmi_tx_n[2] -#set_property -dict { PACKAGE_PIN AB24 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L7P_T1_12 Sch=hdmi_tx_p[2] - -## OLED Display -#set_property -dict { PACKAGE_PIN AC17 IOSTANDARD LVCMOS18 } [get_ports { oled_dc }]; #IO_L18N_T2_32 Sch=oled_dc -#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS18 } [get_ports { oled_res }]; #IO_L18P_T2_32 Sch=oled_res -#set_property -dict { PACKAGE_PIN AF17 IOSTANDARD LVCMOS18 } [get_ports { oled_sclk }]; #IO_L12P_T1_MRCC_32 Sch=oled_sclk -#set_property -dict { PACKAGE_PIN Y15 IOSTANDARD LVCMOS18 } [get_ports { oled_sdin }]; #IO_L24N_T3_32 Sch=oled_sdin -#set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_L3P_T0_DQS_12 Sch=oled_vbat -#set_property -dict { PACKAGE_PIN AG17 IOSTANDARD LVCMOS18 } [get_ports { oled_vdd }]; #IO_L12N_T1_MRCC_32 Sch=oled_vdd - -## PMOD Header JA -#set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1] -#set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1] -#set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2] -#set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2] -#set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3] -#set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] -#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] -#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] - -## PMOD Header JB -#set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1] -#set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1] -#set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2] -#set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2] -#set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3] -#set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3] -#set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4] -#set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4] - -## PMOD Header JC -#set_property -dict { PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L19P_T3_13 Sch=jc[1] -#set_property -dict { PACKAGE_PIN AJ27 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20P_T3_13 Sch=jc[2] -#set_property -dict { PACKAGE_PIN AH30 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L18N_T2_13 Sch=jc[3] -#set_property -dict { PACKAGE_PIN AK29 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L15P_T2_DQS_13 Sch=jc[4] -#set_property -dict { PACKAGE_PIN AD26 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L19N_T3_VREF_13 Sch=jc[7] -#set_property -dict { PACKAGE_PIN AG30 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L18P_T2_13 Sch=jc[8] -#set_property -dict { PACKAGE_PIN AK30 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L15N_T2_DQS_13 Sch=jc[9] -#set_property -dict { PACKAGE_PIN AK28 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_13 Sch=jc[10] - -## PMOD Header JD -#set_property -dict { PACKAGE_PIN V27 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L16N_T2_A15_D31_14 Sch=jd[1] -#set_property -dict { PACKAGE_PIN Y30 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L8P_T1_13 Sch=jd[2] -#set_property -dict { PACKAGE_PIN V24 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L23N_T3_A02_D18_14 Sch=jd[3] -#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L24N_T3_A00_D16_14 Sch=jd[4] -#set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 } [get_ports { spi_sck_o }]; #IO_L23P_T3_A03_D19_14 Sch=jd[7] -#set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 } [get_ports { spi_cs_o }]; #IO_L1P_T0_13 Sch=jd[8] -#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { spi_mosi_o }]; #IO_L22N_T3_A04_D20_14 Sch=jd[9] -#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { spi_miso_i }]; #IO_L24P_T3_A01_D17_14 Sch=jd[10] - -## XADC Header -#set_property -dict { PACKAGE_PIN J24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD0N_15 Sch=xadc0r_n -#set_property -dict { PACKAGE_PIN J23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD0P_15 Sch=xadc0r_p -#set_property -dict { PACKAGE_PIN K24 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xadc1r_n -#set_property -dict { PACKAGE_PIN K23 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xadc1r_p -#set_property -dict { PACKAGE_PIN L23 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xadc8r_n -#set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xadc8r_p -#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L4N_T0_AD9N_15 Sch=xadc9r_n -#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L4P_T0_AD9P_15 Sch=xadc9r_p - -## FMC -#set_property -dict { PACKAGE_PIN AB30 IOSTANDARD LVCMOS33 } [get_ports { FMC_CLK_DIR }]; #IO_L10N_T1_13 Sch=fmc_clk_dir -#set_property -dict { PACKAGE_PIN E20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_17 Sch=fmc_clk0_m2c_n -#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_17 Sch=fmc_clk0_m2c_p -#set_property -dict { PACKAGE_PIN D28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L14N_T2_SRCC_16 Sch=fmc_clk1_m2c_n -#set_property -dict { PACKAGE_PIN E28 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L14P_T2_SRCC_16 Sch=fmc_clk1_m2c_p -#set_property -dict { PACKAGE_PIN K25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_N[2] }]; #IO_L12N_T1_MRCC_AD5N_15 Sch=fmc_clk_n[2] -#set_property -dict { PACKAGE_PIN L25 IOSTANDARD LVCMOS12 } [get_ports { FMC_CLK_P[2] }]; #IO_L12P_T1_MRCC_AD5P_15 Sch=fmc_clk_p[2] -#set_property -dict { PACKAGE_PIN K29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[00] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_ha_n[00] -#set_property -dict { PACKAGE_PIN K28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[00] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_ha_p[00] -#set_property -dict { PACKAGE_PIN L28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[01] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_ha_n[01] -#set_property -dict { PACKAGE_PIN M28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[01] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_ha_p[01] -#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[02] }]; #IO_L22N_T3_A16_15 Sch=fmc_ha_n[02] -#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[02] }]; #IO_L22P_T3_A17_15 Sch=fmc_ha_p[02] -#set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[03] }]; #IO_L18N_T2_A23_15 Sch=fmc_ha_n[03] -#set_property -dict { PACKAGE_PIN N25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[03] }]; #IO_L18P_T2_A24_15 Sch=fmc_ha_p[03] -#set_property -dict { PACKAGE_PIN M25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[04] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_ha_n[04] -#set_property -dict { PACKAGE_PIN M24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[04] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_ha_p[04] -#set_property -dict { PACKAGE_PIN H29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[05] }]; #IO_L7N_T1_AD10N_15 Sch=fmc_ha_n[05] -#set_property -dict { PACKAGE_PIN J29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[05] }]; #IO_L7P_T1_AD10P_15 Sch=fmc_ha_p[05] -#set_property -dict { PACKAGE_PIN N30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[06] }]; #IO_L17N_T2_A25_15 Sch=fmc_ha_n[06] -#set_property -dict { PACKAGE_PIN N29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[06] }]; #IO_L17P_T2_A26_15 Sch=fmc_ha_p[06] -#set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[07] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_ha_n[07] -#set_property -dict { PACKAGE_PIN M29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[07] }]; #IO_L15P_T2_DQS_15 Sch=fmc_ha_p[07] -#set_property -dict { PACKAGE_PIN J28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[08] }]; #IO_L8N_T1_AD3N_15 Sch=fmc_ha_n[08] -#set_property -dict { PACKAGE_PIN J27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[08] }]; #IO_L8P_T1_AD3P_15 Sch=fmc_ha_p[08] -#set_property -dict { PACKAGE_PIN K30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[09] }]; #IO_L9N_T1_DQS_AD11N_15 Sch=fmc_ha_n[09] -#set_property -dict { PACKAGE_PIN L30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[09] }]; #IO_L9P_T1_DQS_AD11P_15 Sch=fmc_ha_p[09] -#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[10] }]; #IO_L20N_T3_A19_15 Sch=fmc_ha_n[10] -#set_property -dict { PACKAGE_PIN N21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[10] }]; #IO_L20P_T3_A20_15 Sch=fmc_ha_p[10] -#set_property -dict { PACKAGE_PIN N24 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[11] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_ha_n[11] -#set_property -dict { PACKAGE_PIN P23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[11] }]; #IO_L21P_T3_DQS_15 Sch=fmc_ha_p[11] -#set_property -dict { PACKAGE_PIN L27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[12] }]; #IO_L11N_T1_SRCC_AD12N_15 Sch=fmc_ha_n[12] -#set_property -dict { PACKAGE_PIN L26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[12] }]; #IO_L11P_T1_SRCC_AD12P_15 Sch=fmc_ha_p[12] -#set_property -dict { PACKAGE_PIN J26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[13] }]; #IO_L10N_T1_AD4N_15 Sch=fmc_ha_n[13] -#set_property -dict { PACKAGE_PIN K26 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[13] }]; #IO_L10P_T1_AD4P_15 Sch=fmc_ha_p[13] -#set_property -dict { PACKAGE_PIN M27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[14] }]; #IO_L16N_T2_A27_15 Sch=fmc_ha_n[14] -#set_property -dict { PACKAGE_PIN N27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[14] }]; #IO_L16P_T2_A28_15 Sch=fmc_ha_p[14] -#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[15] }]; #IO_L5N_T0_AD2N_15 Sch=fmc_ha_n[15] -#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[15] }]; #IO_L5P_T0_AD2P_15 Sch=fmc_ha_p[15] -#set_property -dict { PACKAGE_PIN M23 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[16] }]; #IO_L24N_T3_RS0_15 Sch=fmc_ha_n[16] -#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[16] }]; #IO_L24P_T3_RS1_15 Sch=fmc_ha_p[16] -#set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[17] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_ha_n[17] -#set_property -dict { PACKAGE_PIN C25 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[17] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_ha_p[17] -#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[18] }]; #IO_L14N_T2_SRCC_17 Sch=fmc_ha_n[18] -#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[18] }]; #IO_L14P_T2_SRCC_17 Sch=fmc_ha_p[18] -#set_property -dict { PACKAGE_PIN F30 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[19] }]; #IO_L22N_T3_16 Sch=fmc_ha_n[19] -#set_property -dict { PACKAGE_PIN G29 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[19] }]; #IO_L22P_T3_16 Sch=fmc_ha_p[19] -#set_property -dict { PACKAGE_PIN F27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[20] }]; #IO_L21N_T3_DQS_16 Sch=fmc_ha_n[20] -#set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[20] }]; #IO_L21P_T3_DQS_16 Sch=fmc_ha_p[20] -#set_property -dict { PACKAGE_PIN F28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[21] }]; #IO_L20N_T3_16 Sch=fmc_ha_n[21] -#set_property -dict { PACKAGE_PIN G28 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[21] }]; #IO_L20P_T3_16 Sch=fmc_ha_p[21] -#set_property -dict { PACKAGE_PIN C21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[22] }]; #IO_L8N_T1_17 Sch=fmc_ha_n[22] -#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[22] }]; #IO_L8P_T1_17 Sch=fmc_ha_p[22] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_N[23] }]; #IO_L16N_T2_17 Sch=fmc_ha_n[23] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { FMC_HA_P[23] }]; #IO_L16P_T2_17 Sch=fmc_ha_p[23] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[00] }]; #IO_L12N_T1_MRCC_18 Sch=fmc_hb_n[00] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[00] }]; #IO_L12P_T1_MRCC_18 Sch=fmc_hb_p[00] -#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[01] }]; #IO_L7N_T1_18 Sch=fmc_hb_n[01] -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[01] }]; #IO_L7P_T1_18 Sch=fmc_hb_p[01] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[02] }]; #IO_L2N_T0_18 Sch=fmc_hb_n[02] -#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[02] }]; #IO_L2P_T0_18 Sch=fmc_hb_p[02] -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[03] }]; #IO_L11N_T1_SRCC_18 Sch=fmc_hb_n[03] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[03] }]; #IO_L11P_T1_SRCC_18 Sch=fmc_hb_p[03] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[04] }]; #IO_L9N_T1_DQS_18 Sch=fmc_hb_n[04] -#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[04] }]; #IO_L9P_T1_DQS_18 Sch=fmc_hb_p[04] -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[05] }]; #IO_L1N_T0_18 Sch=fmc_hb_n[05] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[05] }]; #IO_L1P_T0_18 Sch=fmc_hb_p[05] -#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[06] }]; #IO_L14N_T2_SRCC_18 Sch=fmc_hb_n[06] -#set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[06] }]; #IO_L14P_T2_SRCC_18 Sch=fmc_hb_p[06] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[07] }]; #IO_L22N_T3_18 Sch=fmc_hb_n[07] -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[07] }]; #IO_L22P_T3_18 Sch=fmc_hb_p[07] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[08] }]; #IO_L5N_T0_18 Sch=fmc_hb_n[08] -#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[08] }]; #IO_L5P_T0_18 Sch=fmc_hb_p[08] -#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[09] }]; #IO_L23N_T3_18 Sch=fmc_hb_n[09] -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[09] }]; #IO_L23P_T3_18 Sch=fmc_hb_p[09] -#set_property -dict { PACKAGE_PIN J12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[10] }]; #IO_L8N_T1_18 Sch=fmc_hb_n[10] -#set_property -dict { PACKAGE_PIN J11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[10] }]; #IO_L8P_T1_18 Sch=fmc_hb_p[10] -#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[11] }]; #IO_L18N_T2_18 Sch=fmc_hb_n[11] -#set_property -dict { PACKAGE_PIN D11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[11] }]; #IO_L18P_T2_18 Sch=fmc_hb_p[11] -#set_property -dict { PACKAGE_PIN A12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[12] }]; #IO_L17N_T2_18 Sch=fmc_hb_n[12] -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[12] }]; #IO_L17P_T2_18 Sch=fmc_hb_p[12] -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[13] }]; #IO_L15N_T2_DQS_18 Sch=fmc_hb_n[13] -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[13] }]; #IO_L15P_T2_DQS_18 Sch=fmc_hb_p[13] -#set_property -dict { PACKAGE_PIN H12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[14] }]; #IO_L10N_T1_18 Sch=fmc_hb_n[14] -#set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[14] }]; #IO_L10P_T1_18 Sch=fmc_hb_p[14] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[15] }]; #IO_L3N_T0_DQS_18 Sch=fmc_hb_n[15] -#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[15] }]; #IO_L3P_T0_DQS_18 Sch=fmc_hb_p[15] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[16] }]; #IO_L4N_T0_18 Sch=fmc_hb_n[16] -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[16] }]; #IO_L4P_T0_18 Sch=fmc_hb_p[16] -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[17] }]; #IO_L13N_T2_MRCC_18 Sch=fmc_hb_n[17] -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[17] }]; #IO_L13P_T2_MRCC_18 Sch=fmc_hb_p[17] -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[18] }]; #IO_L20N_T3_18 Sch=fmc_hb_n[18] -#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[18] }]; #IO_L20P_T3_18 Sch=fmc_hb_p[18] -#set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[19] }]; #IO_L16N_T2_18 Sch=fmc_hb_n[19] -#set_property -dict { PACKAGE_PIN F11 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[19] }]; #IO_L16P_T2_18 Sch=fmc_hb_p[19] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[20] }]; #IO_L24N_T3_18 Sch=fmc_hb_n[20] -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[20] }]; #IO_L24P_T3_18 Sch=fmc_hb_p[20] -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_N[21] }]; #IO_L21N_T3_DQS_18 Sch=fmc_hb_n[21] -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { FMC_HB_P[21] }]; #IO_L21P_T3_DQS_18 Sch=fmc_hb_p[21] -#set_property -dict { PACKAGE_PIN C27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[00] }]; #IO_L13N_T2_MRCC_16 Sch=fmc_la_n[00] -#set_property -dict { PACKAGE_PIN D27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[00] }]; #IO_L13P_T2_MRCC_16 Sch=fmc_la_p[00] -#set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[01] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la_n[01] -#set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[01] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la_p[01] -#set_property -dict { PACKAGE_PIN G30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L24N_T3_16 Sch=fmc_la_n[02] -#set_property -dict { PACKAGE_PIN H30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L24P_T3_16 Sch=fmc_la_p[02] -#set_property -dict { PACKAGE_PIN E30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L18N_T2_16 Sch=fmc_la_n[03] -#set_property -dict { PACKAGE_PIN E29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L18P_T2_16 Sch=fmc_la_p[03] -#set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L23N_T3_16 Sch=fmc_la_n[04] -#set_property -dict { PACKAGE_PIN H26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L23P_T3_16 Sch=fmc_la_p[04] -#set_property -dict { PACKAGE_PIN A30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L17N_T2_16 Sch=fmc_la_n[05] -#set_property -dict { PACKAGE_PIN B30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L17P_T2_16 Sch=fmc_la_p[05] -#set_property -dict { PACKAGE_PIN C30 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L16N_T2_16 Sch=fmc_la_n[06] -#set_property -dict { PACKAGE_PIN D29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L16P_T2_16 Sch=fmc_la_p[06] -#set_property -dict { PACKAGE_PIN E25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[07] -#set_property -dict { PACKAGE_PIN F25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[07] -#set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[08] -#set_property -dict { PACKAGE_PIN C29 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[08] -#set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[09] -#set_property -dict { PACKAGE_PIN B28 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[09] -#set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L7N_T1_16 Sch=fmc_la_n[10] -#set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L7P_T1_16 Sch=fmc_la_p[10] -#set_property -dict { PACKAGE_PIN A26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L10N_T1_16 Sch=fmc_la_n[11] -#set_property -dict { PACKAGE_PIN A25 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L10P_T1_16 Sch=fmc_la_p[11] -#set_property -dict { PACKAGE_PIN E26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L5N_T0_16 Sch=fmc_la_n[12] -#set_property -dict { PACKAGE_PIN F26 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L5P_T0_16 Sch=fmc_la_p[12] -#set_property -dict { PACKAGE_PIN D24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L4N_T0_16 Sch=fmc_la_n[13] -#set_property -dict { PACKAGE_PIN E24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L4P_T0_16 Sch=fmc_la_p[13] -#set_property -dict { PACKAGE_PIN B24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[14] -#set_property -dict { PACKAGE_PIN C24 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[14] -#set_property -dict { PACKAGE_PIN A23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L1N_T0_16 Sch=fmc_la_n[15] -#set_property -dict { PACKAGE_PIN B23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L1P_T0_16 Sch=fmc_la_p[15] -#set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L2N_T0_16 Sch=fmc_la_n[16] -#set_property -dict { PACKAGE_PIN E23 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L2P_T0_16 Sch=fmc_la_p[16] -#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[17] }]; #IO_L11N_T1_SRCC_17 Sch=fmc_la_n[17] -#set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[17] }]; #IO_L11P_T1_SRCC_17 Sch=fmc_la_p[17] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[18] }]; #IO_L13N_T2_MRCC_17 Sch=fmc_la_n[18] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[18] }]; #IO_L13P_T2_MRCC_17 Sch=fmc_la_p[18] -#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L7N_T1_17 Sch=fmc_la_n[19] -#set_property -dict { PACKAGE_PIN H21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L7P_T1_17 Sch=fmc_la_p[19] -#set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L9N_T1_DQS_17 Sch=fmc_la_n[20] -#set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L9P_T1_DQS_17 Sch=fmc_la_p[20] -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L5N_T0_17 Sch=fmc_la_n[21] -#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L5P_T0_17 Sch=fmc_la_p[21] -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L3N_T0_DQS_17 Sch=fmc_la_n[22] -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L3P_T0_DQS_17 Sch=fmc_la_p[22] -#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L18N_T2_17 Sch=fmc_la_n[23] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L18P_T2_17 Sch=fmc_la_p[23] -#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L2N_T0_17 Sch=fmc_la_n[24] -#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L2P_T0_17 Sch=fmc_la_p[24] -#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L10N_T1_17 Sch=fmc_la_n[25] -#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L10P_T1_17 Sch=fmc_la_p[25] -#set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L23N_T3_17 Sch=fmc_la_n[26] -#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L23P_T3_17 Sch=fmc_la_p[26] -#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L21N_T3_DQS_17 Sch=fmc_la_n[27] -#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L21P_T3_DQS_17 Sch=fmc_la_p[27] -#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L4N_T0_17 Sch=fmc_la_n[28] -#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L4P_T0_17 Sch=fmc_la_p[28] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L22N_T3_17 Sch=fmc_la_n[29] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L22P_T3_17 Sch=fmc_la_p[29] -#set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L20N_T3_17 Sch=fmc_la_n[30] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L20P_T3_17 Sch=fmc_la_p[30] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L17N_T2_17 Sch=fmc_la_n[31] -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L17P_T2_17 Sch=fmc_la_p[31] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L1N_T0_17 Sch=fmc_la_n[32] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L1P_T0_17 Sch=fmc_la_p[32] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L15N_T2_DQS_17 Sch=fmc_la_n[33] -#set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L15P_T2_DQS_17 Sch=fmc_la_p[33] -#set_property -dict { PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SCL }]; #IO_L9P_T1_DQS_12 Sch=fmc_scl -#set_property -dict { PACKAGE_PIN AD24 IOSTANDARD LVCMOS33 } [get_ports { FMC_SDA }]; #IO_L9N_T1_DQS_12 Sch=fmc_sda +# VGA Connector +set_property -dict { PACKAGE_PIN AH20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[0] }]; #IO_L22N_T3_12 Sch=vga_b[3] +set_property -dict { PACKAGE_PIN AG20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[1] }]; #IO_L22P_T3_12 Sch=vga_b[4] +set_property -dict { PACKAGE_PIN AF21 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[2] }]; #IO_L19N_T3_VREF_12 Sch=vga_b[5] +set_property -dict { PACKAGE_PIN AK20 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[3] }]; #IO_L24P_T3_12 Sch=vga_b[6] +set_property -dict { PACKAGE_PIN AG22 IOSTANDARD LVCMOS33 } [get_ports { vga_blue_o[4] }]; #IO_L20P_T3_12 Sch=vga_b[7] + +set_property -dict { PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33 } [get_ports { vga_green_o[0] }]; #IO_L21N_T3_DQS_12 Sch=vga_g[2] +set_property -dict { PACKAGE_PIN AJ22 IOSTANDARD LVCMOS33 } [get_ports { vga_green_o[1] }]; #IO_L21P_T3_DQS_12 Sch=vga_g[3] +set_property -dict { PACKAGE_PIN AH22 IOSTANDARD LVCMOS33 } [get_ports { vga_green_o[2] }]; #IO_L20N_T3_12 Sch=vga_g[4] +set_property -dict { PACKAGE_PIN AK21 IOSTANDARD LVCMOS33 } [get_ports { vga_green_o[3] }]; #IO_L24N_T3_12 Sch=vga_g[5] +set_property -dict { PACKAGE_PIN AJ21 IOSTANDARD LVCMOS33 } [get_ports { vga_green_o[4] }]; #IO_L23N_T3_12 Sch=vga_g[6] +set_property -dict { PACKAGE_PIN AK23 IOSTANDARD LVCMOS33 } [get_ports { vga_green_o[5] }]; #IO_L17P_T2_12 Sch=vga_g[7] + +set_property -dict { PACKAGE_PIN AK25 IOSTANDARD LVCMOS33 } [get_ports { vga_red_o[0] }]; #IO_L15N_T2_DQS_12 Sch=vga_r[3] +set_property -dict { PACKAGE_PIN AG25 IOSTANDARD LVCMOS33 } [get_ports { vga_red_o[1] }]; #IO_L18P_T2_12 Sch=vga_r[4] +set_property -dict { PACKAGE_PIN AH25 IOSTANDARD LVCMOS33 } [get_ports { vga_red_o[2] }]; #IO_L18N_T2_12 Sch=vga_r[5] +set_property -dict { PACKAGE_PIN AK24 IOSTANDARD LVCMOS33 } [get_ports { vga_red_o[3] }]; #IO_L17N_T2_12 Sch=vga_r[6] +set_property -dict { PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33 } [get_ports { vga_red_o[4] }]; #IO_L15P_T2_DQS_12 Sch=vga_r[7] + +set_property -dict { PACKAGE_PIN AF20 IOSTANDARD LVCMOS33 } [get_ports { vga_hsync_o }]; #IO_L19P_T3_12 Sch=vga_hs +set_property -dict { PACKAGE_PIN AG23 IOSTANDARD LVCMOS33 } [get_ports { vga_vsync_o }]; #IO_L13N_T2_MRCC_12 Sch=vga_vs ## Fan Control set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { fan_pwm }]; #IO_25_14 Sch=fan_pwm -#set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { FAN_TACH }]; #IO_L22P_T3_A05_D21_14 Sch=fan_tach -## DPTI -## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. -#set_property -dict { PACKAGE_PIN AB27 IOSTANDARD LVCMOS33 } [get_ports { PROG_CLKO }]; #IO_L12P_T1_MRCC_13 Sch=prog_clko +# DPTI +# Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; #IO_L2P_T0_13 Sch=prog_d1/mosi set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; #IO_L2N_T0_13 Sch=prog_d2/miso set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; #IO_L4P_T0_13 Sch=prog_d3/ss set_property -dict { PACKAGE_PIN Y29 IOSTANDARD LVCMOS33 } [get_ports { jtag_trst_ni }]; #IO_L4N_T0_13 Sch=prog_d[4] -#set_property -dict { PACKAGE_PIN Y28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[5] }]; #IO_L3P_T0_DQS_13 Sch=prog_d[5] -#set_property -dict { PACKAGE_PIN AA28 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[6] }]; #IO_L3N_T0_DQS_13 Sch=prog_d[6] -#set_property -dict { PACKAGE_PIN AA26 IOSTANDARD LVCMOS33 } [get_ports { PROG_D[7] }]; #IO_L1N_T0_13 Sch=prog_d[7] -#set_property -dict { PACKAGE_PIN AC30 IOSTANDARD LVCMOS33 } [get_ports { PROG_OEN }]; #IO_L7N_T1_13 Sch=prog_oen -#set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { PROG_RDN }]; #IO_L6N_T0_VREF_13 Sch=prog_rdn -#set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 } [get_ports { PROG_RXFN }]; #IO_L10P_T1_13 Sch=prog_rxfn -#set_property -dict { PACKAGE_PIN AB28 IOSTANDARD LVCMOS33 } [get_ports { PROG_SIWUN }]; #IO_L5N_T0_13 Sch=prog_siwun -#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien -#set_property -dict { PACKAGE_PIN AA25 IOSTANDARD LVCMOS33 } [get_ports { PROG_TXEN }]; #IO_L6P_T0_13 Sch=prog_txen -#set_property -dict { PACKAGE_PIN AC27 IOSTANDARD LVCMOS33 } [get_ports { PROG_WRN }]; #IO_L12N_T1_MRCC_13 Sch=prog_wrn - -## DSPI -## Note: DPTI and DSPI constraints cannot be used in the same design, as they share pins. -#set_property -dict { PACKAGE_PIN AD29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SPIEN }]; #IO_L9P_T1_DQS_13 Sch=prog_spien -#set_property -dict { PACKAGE_PIN AD27 IOSTANDARD LVCMOS33 } [get_ports { PROG_SCK }]; #IO_L11P_T1_SRCC_13 Sch=prog_d0/sck -#set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 } [get_ports { PROG_MOSI }]; #IO_L2P_T0_13 Sch=prog_d1/mosi -#set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 } [get_ports { PROG_MISO }]; #IO_L2N_T0_13 Sch=prog_d2/miso -#set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 } [get_ports { PROG_SS }]; #IO_L4P_T0_13 Sch=prog_d3/ss - -## QSPI -#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn -#set_property -dict { PACKAGE_PIN P24 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_d[0] -#set_property -dict { PACKAGE_PIN R25 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_d[1] -#set_property -dict { PACKAGE_PIN R20 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_d[2] -#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { QSPI_D[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_d[3] - -## IIC Bus + +# I2C Bus set_property -dict { PACKAGE_PIN AE30 IOSTANDARD LVCMOS33 } [get_ports { i2c_scl_io }]; #IO_L16P_T2_13 Sch=sys_scl set_property -dict { PACKAGE_PIN AF30 IOSTANDARD LVCMOS33 } [get_ports { i2c_sda_io }]; #IO_L16N_T2_13 Sch=sys_sda - -## Display Port IN -#set_property -dict { PACKAGE_PIN AC19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_N }]; #IO_L17N_T2_32 Sch=rx_aux_ch_n -#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_N }]; #IO_L15N_T2_DQS_32 Sch=rx_aux_ch_n -#set_property -dict { PACKAGE_PIN AB19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_IN_CH_P }]; #IO_L17P_T2_32 Sch=rx_aux_ch_p -#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS18 } [get_ports { RX_AUX_OUT_CH_P }]; #IO_L15P_T2_DQS_32 Sch=rx_aux_ch_p -#set_property -dict { PACKAGE_PIN AE21 IOSTANDARD LVCMOS33 } [get_ports { RX_HPD }]; #IO_L10N_T1_12 Sch=rx_hpd - -## Display Port OUT -#set_property -dict { PACKAGE_PIN AD16 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_N }]; #IO_L14N_T2_SRCC_32 Sch=tx_aux_ch_n -#set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_N }]; #IO_L16N_T2_32 Sch=tx_aux_ch_n -#set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_OUT_CH_P }]; #IO_L16P_T2_32 Sch=tx_aux_ch_p -#set_property -dict { PACKAGE_PIN AD17 IOSTANDARD LVCMOS18 } [get_ports { TX_AUX_IN_CH_P }]; #IO_L14P_T2_SRCC_32 Sch=tx_aux_ch_p -#set_property -dict { PACKAGE_PIN AD21 IOSTANDARD LVCMOS33 } [get_ports { TX_HPD }]; #IO_L10P_T1_12 Sch=tx_hpd - -## USB -#set_property -dict { PACKAGE_PIN AD18 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_CLK }]; #IO_L13P_T2_MRCC_32 Sch=usb_otg_clk -#set_property -dict { PACKAGE_PIN AE14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[0] }]; #IO_L19N_T3_VREF_32 Sch=usb_otg_d[0] -#set_property -dict { PACKAGE_PIN AE15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[1] }]; #IO_L19P_T3_32 Sch=usb_otg_d[1] -#set_property -dict { PACKAGE_PIN AC15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[2] }]; #IO_L21N_T3_DQS_32 Sch=usb_otg_d[2] -#set_property -dict { PACKAGE_PIN AC16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[3] }]; #IO_L21P_T3_DQS_32 Sch=usb_otg_d[3] -#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[4] }]; #IO_L20N_T3_32 Sch=usb_otg_d[4] -#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[5] }]; #IO_L20P_T3_32 Sch=usb_otg_d[5] -#set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[6] }]; #IO_L22N_T3_32 Sch=usb_otg_d[6] -#set_property -dict { PACKAGE_PIN AC14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_D[7] }]; #IO_L22P_T3_32 Sch=usb_otg_d[7] -#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_DIR }]; #IO_L24P_T3_32 Sch=usb_otg_dir -#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_NXT }]; #IO_L23N_T3_32 Sch=usb_otg_nxt -#set_property -dict { PACKAGE_PIN AB14 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_RESETB }]; #IO_25_VRP_32 Sch=usb_otg_resetb -#set_property -dict { PACKAGE_PIN AA17 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_STP }]; #IO_L23P_T3_32 Sch=usb_otg_stp -#set_property -dict { PACKAGE_PIN AF16 IOSTANDARD LVCMOS18 } [get_ports { USB_OTG_VBUSOC }]; #IO_L6N_T0_VREF_32 Sch=usb_otg_vbusoc diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc new file mode 100644 index 00000000..420073f5 --- /dev/null +++ b/target/xilinx/constraints/vcu128.xdc @@ -0,0 +1,80 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig +# Paul Scheffler + +############# +# Sys Clock # +############# + +# 100 MHz input clock +set SYS_TCK 10 +create_clock -period $SYS_TCK -name sys_clk [get_ports sys_clk_p] + +# SoC clock is generated by clock wizard and its constraints +set SOC_TCK 20.0 +set soc_clk [get_clocks -of_objects [get_pins i_clkwiz/clk_50]] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets soc_clk] + +####### +# MIG # +####### + +# Dram axi clock : 333 MHz (defined by MIG constraints) +set MIG_TCK 3 + +# False-path incoming reset +set MIG_RST_I [get_pin i_dram_wrapper/i_dram/c0_ddr4_aresetn] +set_false_path -hold -setup -through $MIG_RST_I + +# Constrain outgoing reset +set MIG_RST_O [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +set_false_path -hold -through $MIG_RST_O +set_max_delay -through $MIG_RST_O $MIG_TCK + +# Limit delay across DRAM CDC (hold already false-pathed) +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK +set_max_delay -datapath_only \ + -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \ + -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK + +############### +# Assign Pins # +############### + +set_property PACKAGE_PIN BP26 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_rx_i"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +set_property PACKAGE_PIN BN26 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +set_property IOSTANDARD LVCMOS18 [get_ports "uart_tx_o"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 + +# Jtag GPIOs goes to the FMC XM105 where the debug cable is connected (example Digilent HS2) +set_property PACKAGE_PIN A23 [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND +set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ; +set_property PACKAGE_PIN B23 [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD +set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ; +set_property PACKAGE_PIN B25 [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o] +set_property PACKAGE_PIN B26 [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ; +set_property PACKAGE_PIN H22 [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ; +set_property PACKAGE_PIN J22 [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI +set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i] + +# Clock diff @ 100MHz +set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] +set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] +set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] +set_property PACKAGE_PIN BH51 [get_ports sys_clk_p] +set_property PACKAGE_PIN BJ51 [get_ports sys_clk_n] + +# Active high reset +set_property PACKAGE_PIN BM29 [get_ports sys_reset] +set_property IOSTANDARD LVCMOS12 [get_ports sys_reset] diff --git a/target/xilinx/scripts/common.tcl b/target/xilinx/scripts/common.tcl new file mode 100644 index 00000000..32066b8a --- /dev/null +++ b/target/xilinx/scripts/common.tcl @@ -0,0 +1,142 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Paul Scheffler + +# genesys2 board params +set bpart(genesys2) "digilentinc.com:genesys2:part0:1.1" +set fpart(genesys2) "xc7k325tffg900-2" +set hwdev(genesys2) "xc7k325t_0" + +# vcu128 board params +set bpart(vcu128) "xilinx.com:vcu128:part0:1.0" +set fpart(vcu128) "xcvu37p-fsvh2892-2L-e" +set hwdev(vcu128) "xcvu37p_0" +set cfgmp(vcu128) "mt25qu02g-spi-x1_x2_x4" + + +# Initialize an implementation project +proc init_impl {xilinx_root argc argv} { + global fpart + global bpart + # We declare these variables into the global context + global num_threads + global num_jobs + global project_root + global board + global proj + # Check argument count + if {$argc < 2} { + puts "Error: Insufficient implementation arguments (${argc}): ${argv}." + return -code error + } + # Configure parallelism + set num_threads 8 + set num_jobs 8 + # Get arguments + set board [lindex $argv 0] + set proj [lindex $argv 1] + # Set up multithreading + set_param general.maxThreads $num_threads + # Remove prior build + set project_root ${xilinx_root}/build/${board}.${proj} + file delete -force [glob -nocomplain ${project_root}/*] + # Create project + create_project $proj $project_root -force -part $fpart($board) + set_property board_part $bpart($board) [current_project] +} + +# Open a target device in the hardware manager +proc open_target {xilinx_root argc argv suffix} { + global hwdev + # We declare these variables into the global context + global project_root + global board + global hw_tgt + global hw_device + # Check argument count + if {$argc < 3} { + puts "Error: Insufficient target arguments (${argc}): ${argv}." + return -code error + } + # Get arguments + set url [lindex $argv 0] + set path [lindex $argv 1] + set board [lindex $argv 2] + # Remove prior build + set project_root ${xilinx_root}/build/${board}.${suffix} + file delete -force [glob -nocomplain ${project_root}/*] + # Connect to HW server + open_hw_manager + connect_hw_server -url $url + # Open HW target, set JTAG frequency + set hw_tgt [get_hw_targets ${url}/${path}] + open_hw_target $hw_tgt + set_property PARAM.FREQUENCY 15000000 $hw_tgt + # Get hardware device + set hw_device [get_hw_devices $hwdev($board)] +} + +# Exit if a project does not support a given board +proc no_cfg_exit {proj board} { + puts "Error: Unsupported board ${board} for ${proj}." + return -code error +} + +# Create timing reports +proc gen_reports {rptdir} { + file delete -force $rptdir + file mkdir ${rptdir} + check_timing -file ${rptdir}/check_timing.rpt -verbose + report_timing -file ${rptdir}/timing_worst_100.rpt -max_paths 100 -nworst 100 -delay_type max -sort_by slack + report_timing -file ${rptdir}/timing_worst.rpt -nworst 1 -delay_type max -sort_by group + report_utilization -file ${rptdir}/utilization.rpt -hierarchical + report_cdc -file ${rptdir}/cdc.rpt + report_clock_interaction -file ${rptdir}/clock_interaction.rpt + report_timing_summary -file ${rptdir}/timing_summary.rpt +} + +# Insert debug core and ILAs +proc insert_ilas {clk_net_name} { + global project_root + # Get nets to debug + set debug_nets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]] + # Create debug core only if there are probes + if {![llength $debug_nets]} {return} + # Create and configure debug core + create_debug_core i_ila ila + set_property -dict [list \ + ALL_PROBE_SAME_MU {true} ALL_PROBE_SAME_MU_CNT {4} C_ADV_TRIGGER {true} \ + C_DATA_DEPTH {16384} C_EN_STRG_QUAL {true} C_INPUT_PIPE_STAGES {0} \ + C_TRIGIN_EN {false} C_TRIGOUT_EN {false} \ + ] [get_debug_cores i_ila] + # Connect SoC clock + set_property port_width 1 [get_debug_ports i_ila/clk] + connect_debug_port i_ila/clk [get_nets $clk_net_name] + # Loop through debug nets (add extra list element to ensure last net is processed) + set net_name_last "" + set i 0 + foreach net [concat $debug_nets {""}] { + # Remove trailing array index + regsub {\[[0-9]*\]$} $net {} net_name + # Create probe after all signals with the same name have been collected + if {$net_name_last != $net_name} { + if {$net_name_last != ""} { + puts "Creating probe $i of width [llength $sig_list] for `$net_name_last`." + # probe0 already exists, and does not need to be created + if {$i != 0} {create_debug_port i_ila probe} + set_property port_width [llength $sig_list] [get_debug_ports i_ila/probe$i] + set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports i_ila/probe$i] + connect_debug_port i_ila/probe$i [get_nets $sig_list] + incr i + } + set sig_list "" + } + lappend sig_list $net + set net_name_last $net_name + } + # Save constraints, then implement the debug core + save_constraints -force + implement_debug_core +} diff --git a/target/xilinx/scripts/impl_ip.tcl b/target/xilinx/scripts/impl_ip.tcl new file mode 100644 index 00000000..474787fe --- /dev/null +++ b/target/xilinx/scripts/impl_ip.tcl @@ -0,0 +1,172 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Florian Zaruba +# Cyril Koenig +# Paul Scheffler + +# Initialize implementation +set xilinx_root [file dirname [file dirname [file normalize [info script]]]] +source ${xilinx_root}/scripts/common.tcl +init_impl $xilinx_root $argc $argv + +# Create and configure selected IP +switch $proj { + + clkwiz { + create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $proj + switch $board { + genesys2 { + set_property -dict [list \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {200.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKIN1_JITTER_PS {50.0} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {20} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {50} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {100} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT1_JITTER {112.316} \ + CONFIG.CLKOUT1_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT2_JITTER {129.198} \ + CONFIG.CLKOUT2_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT3_JITTER {155.330} \ + CONFIG.CLKOUT3_PHASE_ERROR {89.971} \ + CONFIG.CLKOUT4_JITTER {178.053} \ + CONFIG.CLKOUT4_PHASE_ERROR {89.971} \ + ] [get_ips $proj] + } + vcu128 { + set_property -dict [list \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_100} \ + CONFIG.CLK_OUT2_PORT {clk_50} \ + CONFIG.CLK_OUT3_PORT {clk_20} \ + CONFIG.CLK_OUT4_PORT {clk_10} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.USE_RESET {true} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {60} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {120} \ + CONFIG.NUM_OUT_CLKS {4} \ + CONFIG.CLKOUT2_JITTER {132.683} \ + CONFIG.CLKOUT2_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT3_JITTER {162.167} \ + CONFIG.CLKOUT3_PHASE_ERROR {87.180} \ + CONFIG.CLKOUT4_JITTER {188.586} \ + CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ + ] [get_ips $proj] + } + default {nocfgexit $proj $board} + } + } + + vio { + create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $proj + switch $board { + genesys2 { + set_property -dict [list \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $proj] + } + vcu128 { + set_property -dict [list \ + CONFIG.C_NUM_PROBE_OUT {3} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \ + CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \ + CONFIG.C_NUM_PROBE_IN {0} \ + ] [get_ips $proj] + } + default {nocfgexit $proj $board} + } + } + + mig7s { + create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $proj + # Inject existing project file + file copy ${xilinx_root}/src/ips/${board}.${proj}.prj \ + ${project_root}/${proj}.srcs/sources_1/ip/${proj}/mig_a.prj + switch $board { + genesys2 { + set_property -dict [list \ + CONFIG.XML_INPUT_FILE {mig_a.prj} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \ + CONFIG.BOARD_MIG_PARAM {Custom} \ + ] [get_ips $proj] + } + default {nocfgexit $proj $board} + } + } + + ddr4 { + create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name $proj + switch $board { + vcu128 { + set_property -dict [list \ + CONFIG.C0.DDR4_Clamshell {true} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ + CONFIG.C0.DDR4_InputClockPeriod {10000} \ + CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.C0.BANK_GROUP_WIDTH {1} \ + CONFIG.C0.CS_WIDTH {2} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + ] [get_ips $proj] + } + default {nocfgexit $proj $board} + } + } + +} + +# Generate targets +set xci ${project_root}/${proj}.srcs/sources_1/ip/${proj}/${proj}.xci +generate_target all [get_files $xci] + +# Synthesize proj +create_ip_run [get_files -of_objects [get_fileset sources_1] $xci] +launch_run -jobs $num_jobs ${proj}_synth_1 +wait_on_run ${proj}_synth_1 + +# Symlink proj for easy access and build tracking, ensuring its update +file delete -force ${project_root}/out.xci +file link -symbolic ${project_root}/out.xci $xci diff --git a/target/xilinx/scripts/impl_sys.tcl b/target/xilinx/scripts/impl_sys.tcl new file mode 100644 index 00000000..08e14a7f --- /dev/null +++ b/target/xilinx/scripts/impl_sys.tcl @@ -0,0 +1,73 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Florian Zaruba +# Nils Wistoff +# Cyril Koenig +# Paul Scheffler + +# Initialize implementation +set xilinx_root [file dirname [file dirname [file normalize [info script]]]] +source ${xilinx_root}/scripts/common.tcl +init_impl $xilinx_root $argc $argv + +# Addtional args provide IPs +read_ip [exec realpath {*}[lrange $argv 2 end]] + +# Load constraints +import_files -fileset constrs_1 -norecurse ${xilinx_root}/constraints/${proj}.xdc +import_files -fileset constrs_1 -norecurse ${xilinx_root}/constraints/${board}.xdc + +# Load RTL sources +source ${xilinx_root}/scripts/add_sources.${board}.tcl + +# Set top module +set_property top ${proj}_top_xilinx [current_fileset] +update_compile_order -fileset sources_1 + +# Set synthesis properties +# TODO: investigate resource-affordable retiming +set_property XPM_LIBRARIES XPM_MEMORY [current_project] +set_property strategy Flow_PerfOptimized_high [get_runs synth_1] + +# Elaborate and open design to explore all clocks +synth_design -rtl -name rtl_1 +report_clocks -file ${project_root}/clocks.rpt + +# Synthesis +launch_runs -jobs $num_jobs synth_1 +wait_on_run synth_1 +open_run synth_1 + +# Generate synthesis reports +gen_reports ${project_root}/reports.synth + +# Instantiate debug core and ILAs +# TODO: debug this +insert_ilas {soc_clk} + +# Set implementation properties +set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] + +# Implementation +launch_runs -jobs $num_jobs impl_1 -to_step write_bitstream +wait_on_run impl_1 +open_run impl_1 + +# Generate implementation reports +gen_reports ${project_root}/reports.impl + +# Check timing constraints +set trep [report_timing_summary -no_header -no_detailed_paths -return_string] +if {![string match -nocase {*timing constraints are met*} $trep]} { + puts "Error: Timing constraints not met for ${proj} on ${board}." + return -code error +} + +# Copy out final bitstream +file mkdir ${xilinx_root}/out +file copy -force ${project_root}/${proj}.runs/impl_1/cheshire_top_xilinx.bit \ + ${xilinx_root}/out/${proj}.${board}.bit +file copy -force ${project_root}/${proj}.runs/impl_1/cheshire_top_xilinx.ltx \ + ${xilinx_root}/out/${proj}.${board}.ltx diff --git a/target/xilinx/scripts/program.tcl b/target/xilinx/scripts/program.tcl deleted file mode 100644 index 846519a6..00000000 --- a/target/xilinx/scripts/program.tcl +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba -# Description: Program Genesys II - -open_hw_manager - -connect_hw_server -url $::env(HOST):$::env(PORT) - -if {$::env(BOARD) eq "genesys2"} { - open_hw_target $::env(HOST):$::env(PORT)/$::env(FPGA_PATH) - - current_hw_device [get_hw_devices xc7k325t_0] - set_property PROGRAM.FILE $::env(BIT) [get_hw_devices xc7k325t_0] - program_hw_devices [get_hw_devices xc7k325t_0] - refresh_hw_device [lindex [get_hw_devices xc7k325t_0] 0] -} elseif {$::env(BOARD) eq "vc707"} { - open_hw_target {$::env(HOST):$::env(PORT)/$::env(FPGA_PATH)} - - current_hw_device [get_hw_devices xc7vx485t_0] - set_property PROGRAM.FILE $::env(BIT) [get_hw_devices xc7vx485t_0] - program_hw_devices [get_hw_devices xc7vx485t_0] - refresh_hw_device [lindex [get_hw_devices xc7vx485t_0] 0] -} else { - exit 1 -} diff --git a/target/xilinx/scripts/prologue.tcl b/target/xilinx/scripts/prologue.tcl deleted file mode 100644 index 4985d3d1..00000000 --- a/target/xilinx/scripts/prologue.tcl +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba - -set project $::env(PROJECT) - -create_project $project . -force -part $::env(XILINX_PART) -set_property board_part $::env(XILINX_BOARD) [current_project] - -# set number of threads to 8 (maximum, unfortunately) -set_param general.maxThreads 8 - -#set_msg_config -id {[Synth 8-5858]} -new_severity "info" - -#set_msg_config -id {[Synth 8-4480]} -limit 1000 \ No newline at end of file diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl deleted file mode 100644 index c99247e9..00000000 --- a/target/xilinx/scripts/run.tcl +++ /dev/null @@ -1,80 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba - -# hard-coded to Genesys 2 for the moment - -if {$::env(BOARD) eq "genesys2"} { - add_files -fileset constrs_1 -norecurse constraints/genesys2.xdc -} elseif {$::env(BOARD) eq "kc705"} { - add_files -fileset constrs_1 -norecurse constraints/kc705.xdc -} elseif {$::env(BOARD) eq "vc707"} { - add_files -fileset constrs_1 -norecurse constraints/vc707.xdc -} else { - exit 1 -} - -read_ip { \ - "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ -} - -source scripts/add_sources.tcl - -set_property top ${project}_top_xilinx [current_fileset] - -update_compile_order -fileset sources_1 - -add_files -fileset constrs_1 -norecurse constraints/$project.xdc - -set_property strategy Flow_PerfOptimized_high [get_runs synth_1] -set_property strategy Performance_ExtraTimingOpt [get_runs impl_1] - -set_property XPM_LIBRARIES XPM_MEMORY [current_project] - -synth_design -rtl -name rtl_1 - -set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] - -launch_runs synth_1 -wait_on_run synth_1 -open_run synth_1 - -exec mkdir -p reports/ -exec rm -rf reports/* - -check_timing -verbose -file reports/$project.check_timing.rpt -report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt -report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt -report_utilization -hierarchical -file reports/$project.utilization.rpt -report_cdc -file reports/$project.cdc.rpt -report_clock_interaction -file reports/$project.clock_interaction.rpt - -launch_runs impl_1 -wait_on_run impl_1 -launch_runs impl_1 -to_step write_bitstream -wait_on_run impl_1 - -#Check timing constraints -open_run impl_1 -set timingrep [report_timing_summary -no_header -no_detailed_paths -return_string] -if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} { - if {! [string match -nocase {*timing constraints are met*} $timingrep]} { - send_msg_id {USER 1-1} ERROR {Timing constraints were not met.} - return -code error - } -} - -# output Verilog netlist + SDC for timing simulation -write_verilog -force -mode funcsim out/${project}_funcsim.v -write_verilog -force -mode timesim out/${project}_timesim.v -write_sdf -force out/${project}_timesim.sdf - -# reports -exec mkdir -p reports/ -exec rm -rf reports/* -check_timing -file reports/${project}.check_timing.rpt -report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt -report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt -report_utilization -hierarchical -file reports/${project}.utilization.rpt diff --git a/target/xilinx/scripts/util/flash.tcl b/target/xilinx/scripts/util/flash.tcl new file mode 100644 index 00000000..bcf672c6 --- /dev/null +++ b/target/xilinx/scripts/util/flash.tcl @@ -0,0 +1,50 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nils Wistoff +# Noah Huetter +# Paul Scheffler + +# Open hardware target +set xilinx_root [file dirname [file dirname [file dirname [file normalize [info script]]]]] +source -quiet ${xilinx_root}/scripts/common.tcl +open_target $xilinx_root $argc $argv flash + +# Additional argument provide image file and offset +set file [lindex $argv 3] +set offs [lindex $argv 4] + +set hw_memdev [lindex [get_cfgmem_parts $cfgmp($board)] 0] +create_hw_cfgmem -hw_device $hw_device $hw_memdev +set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] + +# Create image for and configure memory depending on board +# TODO: add bitstream flashing for genesys2 +switch $board { + vcu128 { + set mcs ${project_root}/image.mcs + write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offs $file" -checksum -file $mcs + set_property -dict [list \ + PROGRAM.ADDRESS_RANGE {use_file} \ + PROGRAM.FILES [list $mcs] \ + PROGRAM.PRM_FILE {} \ + PROGRAM.UNUSED_PIN_TERMINATION {pull-none} \ + PROGRAM.BLANK_CHECK {0} \ + PROGRAM.ERASE {1} \ + PROGRAM.CFG_PROGRAM {1} \ + PROGRAM.VERIFY {1} \ + PROGRAM.CHECKSUM {0} \ + ] $hw_cfgmem + } + default {nocfgexit flash_spi $board} +} + +# Create bitstream to access config memory +create_hw_bitstream -hw_device $hw_device [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_device]; +program_hw_devices $hw_device; +refresh_hw_device $hw_device; + +# Program config memory +program_hw_cfgmem -hw_cfgmem $hw_cfgmem diff --git a/target/xilinx/scripts/util/program.tcl b/target/xilinx/scripts/util/program.tcl new file mode 100644 index 00000000..4bcedead --- /dev/null +++ b/target/xilinx/scripts/util/program.tcl @@ -0,0 +1,20 @@ +# Copyright 2018 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Florian Zaruba +# Paul Scheffler + +# Open hardware target +set xilinx_root [file dirname [file dirname [file dirname [file normalize [info script]]]]] +source -quiet ${xilinx_root}/scripts/common.tcl +open_target $xilinx_root $argc $argv program + +# Additional argument provides bitstream +set bit [lindex $argv 3] + +# Flash bitstream and refresh device +current_hw_device $hw_device +set_property PROGRAM.FILE $bit $hw_device +program_hw_devices $hw_device +refresh_hw_device $hw_device diff --git a/target/xilinx/scripts/write_cfgmem.tcl b/target/xilinx/scripts/write_cfgmem.tcl deleted file mode 100644 index 580d1fd7..00000000 --- a/target/xilinx/scripts/write_cfgmem.tcl +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba -# Description: Generate a memory configuration file from a bitstream (Genesys II only right now) - -if {$argc < 2 || $argc > 4} { - puts $argc - puts {Error: Invalid number of arguments} - puts {Usage: write_cfgmem.tcl mcsfile bitfile [datafile]} - exit 1 -} - -lassign $argv mcsfile bitfile - -# https://scholar.princeton.edu/jbalkind/blog/programming-genesys-2-qspi-spi-x4-flash -# https://scholar.princeton.edu/jbalkind/blog/programming-vc707-virtex-7-bpi-flash -if {$::env(BOARD) eq "genesys2"} { - #write_cfgmem -format mcs -interface SPIx4 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force - write_cfgmem -format mcs -interface SPIx1 -size 256 -loadbit "up 0x0 $bitfile" -file $mcsfile -force -} elseif {$::env(BOARD) eq "vc707"} { - write_cfgmem -format mcs -interface bpix16 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force -} elseif {$::env(BOARD) eq "kc705"} { - write_cfgmem -format mcs -interface SPIx4 -size 128 -loadbit "up 0x0 $bitfile" -file $mcsfile -force -} else { - exit 1 -} diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index aad319b8..bddac283 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -1,331 +1,205 @@ -// Copyright 2022 ETH Zurich and University of Bologna. +// Copyright 2023 ETH Zurich and University of Bologna. // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // // Nicole Narr // Christopher Reinwardt +// Cyril Koenig +// Yann Picod +// Paul Scheffler `include "cheshire/typedef.svh" - -module cheshire_top_xilinx - import cheshire_pkg::*; -( - input logic sysclk_p, - input logic sysclk_n, - input logic cpu_resetn, - - input logic test_mode_i, - - input logic [1:0] boot_mode_i, - - output logic uart_tx_o, - input logic uart_rx_i, - - input logic jtag_tck_i, - input logic jtag_trst_ni, - input logic jtag_tms_i, - input logic jtag_tdi_i, - output logic jtag_tdo_o, - - inout wire i2c_scl_io, - inout wire i2c_sda_io, - - input logic sd_cd_i, +`include "phy_definitions.svh" + +// TODO: Expose more IO: unused SPI CS, Serial Link, etc. + +module cheshire_top_xilinx ( + input logic sys_clk_p, + input logic sys_clk_n, + +`ifdef USE_RESET + input logic sys_reset, +`endif +`ifdef USE_RESETN + input logic sys_resetn, +`endif + +`ifdef USE_SWITCHES + input logic test_mode_i, + input logic [1:0] boot_mode_i, +`endif + +`ifdef USE_JTAG + input logic jtag_tck_i, + input logic jtag_tms_i, + input logic jtag_tdi_i, + output logic jtag_tdo_o, +`ifdef USE_JTAG_TRSTN + input logic jtag_trst_ni, +`endif +`ifdef USE_JTAG_VDDGND + output logic jtag_vdd_o, + output logic jtag_gnd_o, + `endif +`endif + +`ifdef USE_I2C + inout wire i2c_scl_io, + inout wire i2c_sda_io, +`endif + +`ifdef USE_SD + input logic sd_cd_i, output logic sd_cmd_o, - inout wire [3:0] sd_d_io, + inout wire [3:0] sd_d_io, output logic sd_reset_o, output logic sd_sclk_o, +`endif - input logic [3:0] fan_sw, +`ifdef USE_FAN + input logic [3:0] fan_sw, output logic fan_pwm, +`endif - // DDR3 DRAM interface - output wire [14:0] ddr3_addr, - output wire [2:0] ddr3_ba, - output wire ddr3_cas_n, - output wire [0:0] ddr3_ck_n, - output wire [0:0] ddr3_ck_p, - output wire [0:0] ddr3_cke, - output wire [0:0] ddr3_cs_n, - output wire [3:0] ddr3_dm, - inout wire [31:0] ddr3_dq, - inout wire [3:0] ddr3_dqs_n, - inout wire [3:0] ddr3_dqs_p, - output wire [0:0] ddr3_odt, - output wire ddr3_ras_n, - output wire ddr3_reset_n, - output wire ddr3_we_n, - +`ifdef USE_VGA // VGA Colour signals - output logic [4:0] vga_b, - output logic [5:0] vga_g, - output logic [4:0] vga_r, - - // VGA Sync signals - output logic vga_hs, - output logic vga_vs + output logic vga_hsync_o, + output logic vga_vsync_o, + output logic [4:0] vga_red_o, + output logic [5:0] vga_green_o, + output logic [4:0] vga_blue_o, +`endif + +`ifdef USE_DDR4 + `DDR4_INTF +`endif +`ifdef USE_DDR3 + `DDR3_INTF +`endif + + output logic uart_tx_o, + input logic uart_rx_i ); + /////////////////////// + // Cheshire Config // + /////////////////////// + + import cheshire_pkg::*; + + // Use default config as far as possible + function automatic cheshire_cfg_t gen_cheshire_xilinx_cfg(); + cheshire_cfg_t ret = DefaultCfg; + ret.RtcFreq = 1000000; + // TODO: UNBENT breaks SD boot; why? + ret.BusErr = 0; + ret.SerialLink = 0; + ret.VgaRedWidth = 5; + ret.VgaGreenWidth = 6; + ret.VgaBlueWidth = 5; + return ret; + endfunction + // Configure cheshire for FPGA mapping - localparam cheshire_cfg_t FPGACfg = '{ - // CVA6 parameters - Cva6RASDepth : 2, - Cva6BTBEntries : 32, - Cva6BHTEntries : 128, - Cva6NrPMPEntries : 0, - Cva6ExtCieLength : 'h2000_0000, - // Harts - NumCores : 1, - CoreMaxTxns : 8, - CoreMaxTxnsPerId : 4, - // Interrupts - NumExtIntrSyncs : 2, - // Interconnect - AddrWidth : 48, - AxiDataWidth : 64, - AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link - AxiMstIdWidth : 2, - AxiMaxMstTrans : 8, - AxiMaxSlvTrans : 8, - AxiUserAmoMsb : 1, - AxiUserAmoLsb : 0, - RegMaxReadTxns : 8, - RegMaxWriteTxns : 8, - RegAmoNumCuts : 1, - RegAmoPostCut : 1, - // RTC - RtcFreq : 1000000, - // Features - Bootrom : 1, - Uart : 1, - I2c : 1, - SpiHost : 1, - Gpio : 1, - Dma : 1, - SerialLink : 0, - Vga : 1, - // Debug - DbgIdCode : CheshireIdCode, - DbgMaxReqs : 4, - DbgMaxReadTxns : 4, - DbgMaxWriteTxns : 4, - DbgAmoNumCuts : 1, - DbgAmoPostCut : 1, - // LLC: 128 KiB, up to 2 GiB DRAM - LlcNotBypass : 1, - LlcSetAssoc : 8, - LlcNumLines : 256, - LlcNumBlocks : 8, - LlcMaxReadTxns : 8, - LlcMaxWriteTxns : 8, - LlcAmoNumCuts : 1, - LlcAmoPostCut : 1, - LlcOutConnect : 1, - LlcOutRegionStart : 'h8000_0000, - LlcOutRegionEnd : 'h1_0000_0000, - // VGA: RGB332 - VgaRedWidth : 5, - VgaGreenWidth : 6, - VgaBlueWidth : 5, - VgaHCountWidth : 24, // TODO: Default is 32; is this needed? - VgaVCountWidth : 24, // TODO: See above - // Serial Link: map other chip's lower 32bit to 'h1_000_0000 - SlinkMaxTxnsPerId : 4, - SlinkMaxUniqIds : 4, - SlinkMaxClkDiv : 1024, - SlinkRegionStart : 'h1_0000_0000, - SlinkRegionEnd : 'h2_0000_0000, - SlinkTxAddrMask : 'hFFFF_FFFF, - SlinkTxAddrDomain : 'h0000_0000, - SlinkUserAmoBit : 1, // Upper atomics bit for serial link - // DMA config - DmaConfMaxReadTxns : 4, - DmaConfMaxWriteTxns : 4, - DmaConfAmoNumCuts : 1, - DmaConfAmoPostCut : 1, - DmaConfEnableTwoD : 1, - DmaNumAxInFlight : 16, - DmaMemSysDepth : 8, - DmaJobFifoDepth : 2, - DmaRAWCouplingAvail : 1, - // GPIOs - GpioInputSyncs : 1, - // All non-set values should be zero - default: '0 - }; - - localparam cheshire_cfg_t CheshireFPGACfg = FPGACfg; - `CHESHIRE_TYPEDEF_ALL(, CheshireFPGACfg) - - axi_llc_req_t axi_llc_mst_req, dram_req, dram_req_cdc; - axi_llc_rsp_t axi_llc_mst_rsp, dram_resp, dram_resp_cdc; - - wire dram_clock_out; - wire dram_sync_reset; + localparam cheshire_cfg_t FPGACfg = gen_cheshire_xilinx_cfg(); + `CHESHIRE_TYPEDEF_ALL(, FPGACfg) + + //////////////////////// + // Clock Generation // + //////////////////////// + + wire sys_clk; wire soc_clk; - logic rst_n; - - // Statically assign the response user signals - // B Channel user - assign dram_resp.b.user = '0; - - // R Channel user - assign dram_resp.r.user = '0; - - /////////////////// - // Clock Divider // - /////////////////// - - clk_int_div #( - .DIV_VALUE_WIDTH ( 4 ), - .DEFAULT_DIV_VALUE ( 4'h4 ), - .ENABLE_CLOCK_IN_RESET ( 1'b0 ) - ) i_sys_clk_div ( - .clk_i ( dram_clock_out ), - .rst_ni ( ~dram_sync_reset ), - .en_i ( 1'b1 ), - .test_mode_en_i ( testmode_i ), - .div_i ( 4'h4 ), - .div_valid_i ( 1'b0 ), - .div_ready_o ( ), - .clk_o ( soc_clk ), - .cycl_count_o ( ) + IBUFDS #( + .IBUF_LOW_PWR ("FALSE") + ) i_bufds_sys_clk ( + .I ( sys_clk_p ), + .IB ( sys_clk_n ), + .O ( sys_clk ) + ); + + clkwiz i_clkwiz ( + .clk_in1 ( sys_clk ), + .reset ( '0 ), + .locked ( ), + .clk_100 ( ), + .clk_50 ( soc_clk ), + .clk_20 ( ), + .clk_10 ( ) ); ///////////////////// - // Reset Generator // + // System Inputs // ///////////////////// - rstgen i_rstgen_main ( - .clk_i ( soc_clk ), - .rst_ni ( ~dram_sync_reset ), - .test_mode_i ( test_en ), - .rst_no ( rst_n ), - .init_no ( ) // keep open + // Select SoC reset +`ifdef USE_RESET + logic sys_resetn; + assign sys_resetn = ~sys_reset; +`elsif USE_RESETN + logic sys_reset; + assign sys_reset = ~sys_resetn; +`endif + + // Tie off inputs of no switches +`ifndef USE_SWITCHES + logic test_mode_i; + logic [1:0] boot_mode_i; + assign test_mode_i = '0; + assign boot_mode_i = '0; +`endif + + //////////// + // VIOs // + //////////// + + logic vio_reset, vio_boot_mode_sel; + logic [1:0] boot_mode, vio_boot_mode; + logic sys_rst; + +`ifdef USE_VIO + vio i_vio ( + .clk ( soc_clk ), + .probe_out0 ( vio_reset ), + .probe_out1 ( vio_boot_mode ), + .probe_out2 ( vio_boot_mode_sel ) ); +`else + assign vio_reset = '0; + assign vio_boot_mode = '0; + assign vio_boot_mode_sel = '0; +`endif + assign sys_rst = ~sys_resetn | vio_reset; + assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; - /////////////////////////////////////////// - // AXI Clock Domain Crossing SoC -> DRAM // - /////////////////////////////////////////// - - axi_cdc #( - .aw_chan_t ( axi_llc_aw_chan_t ), - .w_chan_t ( axi_llc_w_chan_t ), - .b_chan_t ( axi_llc_b_chan_t ), - .ar_chan_t ( axi_llc_ar_chan_t ), - .r_chan_t ( axi_llc_r_chan_t ), - .axi_req_t ( axi_llc_req_t ), - .axi_resp_t ( axi_llc_rsp_t ), - .LogDepth ( 1 ) - ) i_axi_cdc_mig ( - .src_clk_i ( soc_clk ), - .src_rst_ni ( rst_n ), - .src_req_i ( axi_llc_mst_req ), - .src_resp_o ( axi_llc_mst_rsp ), - .dst_clk_i ( dram_clock_out ), - .dst_rst_ni ( rst_n ), - .dst_req_o ( dram_req_cdc ), - .dst_resp_i ( dram_resp_cdc ) - ); - - // AXI CUT (spill register) between the AXI CDC and the MIG to - // reduce timing pressure - axi_cut #( - .Bypass ( 1'b0 ), - .aw_chan_t ( axi_llc_aw_chan_t ), - .w_chan_t ( axi_llc_w_chan_t ), - .b_chan_t ( axi_llc_b_chan_t ), - .ar_chan_t ( axi_llc_ar_chan_t ), - .r_chan_t ( axi_llc_r_chan_t ), - .axi_req_t ( axi_llc_req_t ), - .axi_resp_t ( axi_llc_rsp_t ) - ) i_axi_cut_soc_dram ( - .clk_i ( dram_clock_out ), - .rst_ni ( rst_n ), - - .slv_req_i ( dram_req_cdc ), - .slv_resp_o ( dram_resp_cdc ), - - .mst_req_o ( dram_req ), - .mst_resp_i ( dram_resp ) - ); + ////////////////// + // Reset Sync // + ////////////////// - ////////////// - // DRAM MIG // - ////////////// + wire rst_n; - xlnx_mig_7_ddr3 i_dram ( - .sys_clk_p ( sysclk_p ), - .sys_clk_n ( sysclk_n ), - .ddr3_dq, - .ddr3_dqs_n, - .ddr3_dqs_p, - .ddr3_addr, - .ddr3_ba, - .ddr3_ras_n, - .ddr3_cas_n, - .ddr3_we_n, - .ddr3_reset_n, - .ddr3_ck_p, - .ddr3_ck_n, - .ddr3_cke, - .ddr3_cs_n, - .ddr3_dm, - .ddr3_odt, - .mmcm_locked ( ), // keep open - .app_sr_req ( '0 ), - .app_ref_req ( '0 ), - .app_zq_req ( '0 ), - .app_sr_active ( ), // keep open - .app_ref_ack ( ), // keep open - .app_zq_ack ( ), // keep open - .ui_clk ( dram_clock_out ), - .ui_clk_sync_rst ( dram_sync_reset ), - .aresetn ( rst_n ), - .s_axi_awid ( dram_req.aw.id ), - .s_axi_awaddr ( dram_req.aw.addr[29:0] ), - .s_axi_awlen ( dram_req.aw.len ), - .s_axi_awsize ( dram_req.aw.size ), - .s_axi_awburst ( dram_req.aw.burst ), - .s_axi_awlock ( dram_req.aw.lock ), - .s_axi_awcache ( dram_req.aw.cache ), - .s_axi_awprot ( dram_req.aw.prot ), - .s_axi_awqos ( dram_req.aw.qos ), - .s_axi_awvalid ( dram_req.aw_valid ), - .s_axi_awready ( dram_resp.aw_ready ), - .s_axi_wdata ( dram_req.w.data ), - .s_axi_wstrb ( dram_req.w.strb ), - .s_axi_wlast ( dram_req.w.last ), - .s_axi_wvalid ( dram_req.w_valid ), - .s_axi_wready ( dram_resp.w_ready ), - .s_axi_bready ( dram_req.b_ready ), - .s_axi_bid ( dram_resp.b.id ), - .s_axi_bresp ( dram_resp.b.resp ), - .s_axi_bvalid ( dram_resp.b_valid ), - .s_axi_arid ( dram_req.ar.id ), - .s_axi_araddr ( dram_req.ar.addr[29:0] ), - .s_axi_arlen ( dram_req.ar.len ), - .s_axi_arsize ( dram_req.ar.size ), - .s_axi_arburst ( dram_req.ar.burst ), - .s_axi_arlock ( dram_req.ar.lock ), - .s_axi_arcache ( dram_req.ar.cache ), - .s_axi_arprot ( dram_req.ar.prot ), - .s_axi_arqos ( dram_req.ar.qos ), - .s_axi_arvalid ( dram_req.ar_valid ), - .s_axi_arready ( dram_resp.ar_ready ), - .s_axi_rready ( dram_req.r_ready ), - .s_axi_rid ( dram_resp.r.id ), - .s_axi_rdata ( dram_resp.r.data ), - .s_axi_rresp ( dram_resp.r.resp ), - .s_axi_rlast ( dram_resp.r.last ), - .s_axi_rvalid ( dram_resp.r_valid ), - .init_calib_complete ( ), // keep open - .device_temp ( ), // keep open - .sys_rst ( cpu_resetn ) + rstgen i_rstgen ( + .clk_i ( soc_clk ), + .rst_ni ( ~sys_rst ), + .test_mode_i ( test_mode_i ), + .rst_no ( rst_n ), + .init_no ( ) ); + //////////// + // JTAG // + //////////// + +`ifdef USE_JTAG_VDDGND + assign jtag_vdd_o = 1'b1; + assign jtag_gnd_o = 1'b0; +`endif +`ifndef USE_JTAG_TRSTN + logic jtag_trst_ni; + assign jtag_trst_ni = 1'b1; +`endif ////////////////// // I2C Adaption // @@ -338,36 +212,35 @@ module cheshire_top_xilinx logic i2c_sda_en; logic i2c_scl_en; - // Three state buffer for SCL +`ifdef USE_I2C IOBUF #( .DRIVE ( 12 ), .IBUF_LOW_PWR ( "FALSE" ), .IOSTANDARD ( "DEFAULT" ), .SLEW ( "FAST" ) ) i_scl_iobuf ( - .O ( i2c_scl_soc_in ), - .IO ( i2c_scl_io ), - .I ( i2c_scl_soc_out ), - .T ( ~i2c_scl_en ) + .O ( i2c_scl_soc_in ), + .IO ( i2c_scl_io ), + .I ( i2c_scl_soc_out ), + .T ( ~i2c_scl_en ) ); - // Three state buffer for SDA IOBUF #( .DRIVE ( 12 ), .IBUF_LOW_PWR ( "FALSE" ), .IOSTANDARD ( "DEFAULT" ), .SLEW ( "FAST" ) ) i_sda_iobuf ( - .O ( i2c_sda_soc_in ), - .IO ( i2c_sda_io ), - .I ( i2c_sda_soc_out ), - .T ( ~i2c_sda_en ) + .O ( i2c_sda_soc_in ), + .IO ( i2c_sda_io ), + .I ( i2c_sda_soc_out ), + .T ( ~i2c_sda_en ) ); +`endif - - ////////////////// - // SPI Adaption // - ////////////////// + /////////////// + // SPI to SD // + /////////////// logic spi_sck_soc; logic [1:0] spi_cs_soc; @@ -378,36 +251,83 @@ module cheshire_top_xilinx logic [1:0] spi_cs_en; logic [3:0] spi_sd_en; +`ifdef USE_SD // Assert reset low => Apply power to the SD Card assign sd_reset_o = 1'b0; - // SCK - SD CLK signal assign sd_sclk_o = spi_sck_en ? spi_sck_soc : 1'b1; - // CS - SD DAT3 signal assign sd_d_io[3] = spi_cs_en[0] ? spi_cs_soc[0] : 1'b1; - // MOSI - SD CMD signal assign sd_cmd_o = spi_sd_en[0] ? spi_sd_soc_out[0] : 1'b1; - // MISO - SD DAT0 signal assign spi_sd_soc_in[1] = sd_d_io[0]; - // SD DAT1 and DAT2 signal tie-off - Not used for SPI mode assign sd_d_io[2:1] = 2'b11; - // Bind input side of SoC low for output signals assign spi_sd_soc_in[0] = 1'b0; assign spi_sd_soc_in[2] = 1'b0; assign spi_sd_soc_in[3] = 1'b0; - +`endif + + //////////// + // QSPI // + //////////// + +`ifdef USE_QSPI + logic qspi_clk; + logic qspi_clk_ts; + logic [3:0] qspi_dqi; + logic [3:0] qspi_dqo_ts; + logic [3:0] qspi_dqo; + logic [SpihNumCs-1:0] qspi_cs_b; + logic [SpihNumCs-1:0] qspi_cs_b_ts; + + assign qspi_clk = spi_sck_soc; + assign qspi_cs_b = spi_cs_soc; + assign qspi_dqo = spi_sd_soc_out; + assign spi_sd_soc_in = qspi_dqi; + + // Tristate enables + assign qspi_clk_ts = ~spi_sck_en; + assign qspi_cs_b_ts = ~spi_cs_en; + assign qspi_dqo_ts = ~spi_sd_en; + + // On VCU128/ZCU102, SPI ports are not directly available +`ifdef USE_STARTUPE3 + STARTUPE3 #( + .PROG_USR("FALSE"), + .SIM_CCLK_FREQ(0.0) + ) i_startupe3 ( + .CFGCLK ( ), + .CFGMCLK ( ), + .DI ( qspi_dqi ), + .EOS ( ), + .PREQ ( ), + .DO ( qspi_dqo ), + .DTS ( qspi_dqo_ts ), + .FCSBO ( qspi_cs_b[1] ), + .FCSBTS ( qspi_cs_b_ts[1] ), + .GSR ( 1'b0 ), + .GTS ( 1'b0 ), + .KEYCLEARB ( 1'b1 ), + .PACK ( 1'b0 ), + .USRCCLKO ( qspi_clk ), + .USRCCLKTS ( qspi_clk_ts ), + .USRDONEO ( 1'b1 ), + .USRDONETS ( 1'b1 ) + ); +`else + // TODO: off-chip QSPI interface +`endif +`endif ///////////////////////// // "RTC" Clock Divider // ///////////////////////// logic rtc_clk_d, rtc_clk_q; - logic [4:0] counter_d, counter_q; + logic [15:0] counter_d, counter_q; // Divide soc_clk (50 MHz) by 50 => 1 MHz RTC Clock always_comb begin @@ -415,14 +335,14 @@ module cheshire_top_xilinx rtc_clk_d = rtc_clk_q; if(counter_q == 24) begin - counter_d = 5'b0; + counter_d = '0; rtc_clk_d = ~rtc_clk_q; end end always_ff @(posedge soc_clk, negedge rst_n) begin if(~rst_n) begin - counter_q <= 5'b0; + counter_q <= '0; rtc_clk_q <= 0; end else begin counter_q <= counter_d; @@ -430,36 +350,45 @@ module cheshire_top_xilinx end end - ///////////////// // Fan Control // ///////////////// +`ifdef USE_FAN fan_ctrl i_fan_ctrl ( - .clk_i ( soc_clk ), - .rst_ni ( rst_n ), - .pwm_setting_i ( fan_sw ), - .fan_pwm_o ( fan_pwm ) + .clk_i ( soc_clk ), + .rst_ni ( rst_n ), + .pwm_setting_i ( fan_sw ), + .fan_pwm_o ( fan_pwm ) ); +`endif + ////////////// + // DRAM MIG // + ////////////// - //////////////////////// - // Regbus Error Slave // - //////////////////////// - - reg_req_t ext_req; - reg_rsp_t ext_rsp; - - reg_err_slv #( - .DW ( 32 ), - .ERR_VAL ( 32'hBADCAB1E ), - .req_t ( reg_req_t ), - .rsp_t ( reg_rsp_t ) - ) i_reg_err_slv_ext ( - .req_i ( ext_req ), - .rsp_o ( ext_rsp ) + axi_llc_req_t axi_llc_mst_req; + axi_llc_rsp_t axi_llc_mst_rsp; + +`ifdef USE_DDR + dram_wrapper_xilinx #( + .axi_soc_aw_chan_t ( axi_llc_aw_chan_t ), + .axi_soc_w_chan_t ( axi_llc_w_chan_t ), + .axi_soc_b_chan_t ( axi_llc_b_chan_t ), + .axi_soc_ar_chan_t ( axi_llc_ar_chan_t ), + .axi_soc_r_chan_t ( axi_llc_r_chan_t ), + .axi_soc_req_t ( axi_llc_req_t ), + .axi_soc_resp_t ( axi_llc_rsp_t ) + ) i_dram_wrapper ( + .sys_rst_i ( sys_rst ), + .soc_resetn_i ( rst_n ), + .soc_clk_i ( soc_clk ), + .dram_clk_i ( sys_clk ), + .soc_req_i ( axi_llc_mst_req ), + .soc_rsp_o ( axi_llc_mst_rsp ), + .* ); - +`endif ////////////////// // Cheshire SoC // @@ -479,9 +408,9 @@ module cheshire_top_xilinx ) i_cheshire_soc ( .clk_i ( soc_clk ), .rst_ni ( rst_n ), - .test_mode_i, - .boot_mode_i, - .rtc_i ( rtc_clk_q ), + .test_mode_i ( test_mode_i ), + .boot_mode_i ( boot_mode ), + .rtc_i ( rtc_clk_q ), .axi_llc_mst_req_o ( axi_llc_mst_req ), .axi_llc_mst_rsp_i ( axi_llc_mst_rsp ), .axi_ext_mst_req_i ( '0 ), @@ -498,20 +427,19 @@ module cheshire_top_xilinx .dbg_active_o ( ), .dbg_ext_req_o ( ), .dbg_ext_unavail_i ( '0 ), + .slink_rcv_clk_i ( 1'b1 ), + .slink_rcv_clk_o ( ), + .slink_i ( '0 ), + .slink_o ( ), +`ifdef USE_JTAG .jtag_tck_i, .jtag_trst_ni, .jtag_tms_i, .jtag_tdi_i, .jtag_tdo_o, + // TODO: connect to the tdo pad .jtag_tdo_oe_o ( ), - .uart_tx_o, - .uart_rx_i, - .uart_rts_no ( ), - .uart_dtr_no ( ), - .uart_cts_ni ( 1'b0 ), - .uart_dsr_ni ( 1'b0 ), - .uart_dcd_ni ( 1'b0 ), - .uart_rin_ni ( 1'b0 ), +`endif .i2c_sda_o ( i2c_sda_soc_out ), .i2c_sda_i ( i2c_sda_soc_in ), .i2c_sda_en_o ( i2c_sda_en ), @@ -525,18 +453,15 @@ module cheshire_top_xilinx .spih_sd_o ( spi_sd_soc_out ), .spih_sd_en_o ( spi_sd_en ), .spih_sd_i ( spi_sd_soc_in ), - .gpio_i ( '0 ), - .gpio_o ( ), - .gpio_en_o ( ), - .slink_rcv_clk_i ( '1 ), - .slink_rcv_clk_o ( ), - .slink_i ( '0 ), - .slink_o ( ), - .vga_hsync_o ( vga_hs ), - .vga_vsync_o ( vga_vs ), - .vga_red_o ( vga_r ), - .vga_green_o ( vga_g ), - .vga_blue_o ( vga_b ) +`ifdef USE_VGA + .vga_hsync_o, + .vga_vsync_o, + .vga_red_o, + .vga_green_o, + .vga_blue_o, +`endif + .uart_tx_o, + .uart_rx_i ); endmodule diff --git a/target/xilinx/src/dram_wrapper_xilinx.sv b/target/xilinx/src/dram_wrapper_xilinx.sv new file mode 100644 index 00000000..2a4719a0 --- /dev/null +++ b/target/xilinx/src/dram_wrapper_xilinx.sv @@ -0,0 +1,363 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig +// Paul Scheffler +// +// Resize AXI AW, IW, and DW before connecting to a Xilinx DRAM controller. + +`include "cheshire/typedef.svh" +`include "phy_definitions.svh" +`include "common_cells/registers.svh" + +module dram_wrapper_xilinx #( + parameter type axi_soc_aw_chan_t = logic, + parameter type axi_soc_w_chan_t = logic, + parameter type axi_soc_b_chan_t = logic, + parameter type axi_soc_ar_chan_t = logic, + parameter type axi_soc_r_chan_t = logic, + parameter type axi_soc_req_t = logic, + parameter type axi_soc_resp_t = logic +) ( + // System reset + input logic sys_rst_i, + input logic dram_clk_i, + // Controller reset + input logic soc_resetn_i, + input logic soc_clk_i, + // PHY interfaces +`ifdef USE_DDR4 + `DDR4_INTF +`endif +`ifdef USE_DDR3 + `DDR3_INTF +`endif + // DRAM AXI interface + input axi_soc_req_t soc_req_i, + output axi_soc_resp_t soc_rsp_o +); + + ////////////////////////////////////// + // Configurations and definitions // + ////////////////////////////////////// + + typedef struct packed { + bit EnCdc; + integer CdcLogDepth; + integer IdWidth; + integer AddrWidth; + integer DataWidth; + integer StrobeWidth; + integer MaxUniqIds; + integer MaxTxns; + } dram_cfg_t; + +`ifdef TARGET_VCU128 + localparam dram_cfg_t cfg = '{ + EnCdc : 1, // 333 MHz AXI (cf. CdcLogDepth) + CdcLogDepth : 5, + IdWidth : 8, + AddrWidth : 32, + DataWidth : 512, + StrobeWidth : 64, + MaxUniqIds : 8, // TODO: suboptimal, but limited by CVA6/LLC + MaxTxns : 24 // TODO: suboptimal, but limited by CVA6/LLC + }; +`endif + +`ifdef TARGET_GENESYS2 + localparam dram_cfg_t cfg = '{ + EnCdc : 1, // 200 MHz AXI (cf. CCdcLogDepth) + CdcLogDepth : 5, + IdWidth : 4, // Fixed + AddrWidth : 30, + DataWidth : 64, + StrobeWidth : 8, + MaxUniqIds : 8, // TODO: suboptimal, but limited by CVA6/LLC + MaxTxns : 24 // TODO: suboptimal, but limited by CVA6/LLC + }; +`endif + + localparam SocDataWidth = $bits(soc_req_i.w.data); + localparam SocIdWidth = $bits(soc_req_i.ar.id); + localparam SocUserWidth = $bits(soc_req_i.ar.user); + localparam SocAddrWidth = $bits(soc_req_i.ar.addr); + + // Define type after data width and address resizer + `AXI_TYPEDEF_ALL(axi_dw, logic[SocAddrWidth-1:0], logic[SocIdWidth-1:0], + logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0], + logic[SocUserWidth-1:0]) + + // Define type after data & id width resizers + `AXI_TYPEDEF_ALL(axi_dw_iw, logic[SocAddrWidth-1:0], logic[cfg.IdWidth-1:0], + logic[cfg.DataWidth-1:0], logic[cfg.StrobeWidth-1:0], + logic[SocUserWidth-1:0]) + + // Clock on which is clocked the DRAM AXI + logic dram_axi_clk; + logic dram_rst_o; + + // Signals before resizing + axi_soc_req_t soc_dresizer_req; + axi_soc_resp_t soc_dresizer_rsp; + + // Signals after data width resizing + axi_dw_req_t dresizer_iresizer_req; + axi_dw_resp_t dresizer_iresizer_rsp; + + // Signals after id width resizing + axi_dw_iw_req_t iresizer_cdc_req, cdc_dram_req; + axi_dw_iw_resp_t iresizer_cdc_rsp, cdc_dram_rsp; + + // Entry signals + assign soc_dresizer_req = soc_req_i; + assign soc_rsp_o = soc_dresizer_rsp; + + //////////////////// + // DW converter // + //////////////////// + + axi_dw_converter #( + .AxiMaxReads ( cfg.MaxTxns ), + .AxiSlvPortDataWidth ( SocDataWidth ), + .AxiMstPortDataWidth ( cfg.DataWidth ), + .AxiAddrWidth ( SocAddrWidth ), + .AxiIdWidth ( SocIdWidth ), + // Common AW, AR, B + .aw_chan_t ( axi_soc_aw_chan_t ), + .b_chan_t ( axi_soc_b_chan_t ), + .ar_chan_t ( axi_soc_ar_chan_t ), + // Manager W, R + .mst_w_chan_t ( axi_dw_w_chan_t ), + .mst_r_chan_t ( axi_dw_r_chan_t ), + .axi_mst_req_t ( axi_dw_req_t ), + .axi_mst_resp_t ( axi_dw_resp_t ), + // Subordinate W, R + .slv_w_chan_t ( axi_soc_w_chan_t ), + .slv_r_chan_t ( axi_soc_r_chan_t ), + .axi_slv_req_t ( axi_soc_req_t ), + .axi_slv_resp_t ( axi_soc_resp_t ) + ) i_axi_dw_converter ( + .clk_i ( soc_clk_i ), + .rst_ni ( soc_resetn_i ), + .slv_req_i ( soc_dresizer_req ), + .slv_resp_o ( soc_dresizer_rsp ), + .mst_req_o ( dresizer_iresizer_req ), + .mst_resp_i ( dresizer_iresizer_rsp ) + ); + + ////////////////// + // ID resizer // + ////////////////// + + // TODO: Implement simpler solutions + axi_iw_converter #( + .AxiAddrWidth ( SocAddrWidth ), + .AxiDataWidth ( cfg.DataWidth ), + .AxiUserWidth ( SocUserWidth ), + .AxiSlvPortIdWidth ( SocIdWidth ), + .AxiSlvPortMaxUniqIds ( cfg.MaxUniqIds ), + .AxiSlvPortMaxTxnsPerId ( cfg.MaxTxns ), + .AxiSlvPortMaxTxns ( cfg.MaxTxns ), + .AxiMstPortIdWidth ( cfg.IdWidth ), + .AxiMstPortMaxUniqIds ( cfg.MaxUniqIds ), + .AxiMstPortMaxTxnsPerId ( cfg.MaxTxns ), + .slv_req_t ( axi_dw_req_t ), + .slv_resp_t ( axi_dw_resp_t ), + .mst_req_t ( axi_dw_iw_req_t ), + .mst_resp_t ( axi_dw_iw_resp_t ) + ) i_axi_iw_converter ( + .clk_i ( soc_clk_i ), + .rst_ni ( soc_resetn_i ), + .slv_req_i ( dresizer_iresizer_req ), + .slv_resp_o ( dresizer_iresizer_rsp ), + .mst_req_o ( iresizer_cdc_req ), + .mst_resp_i ( iresizer_cdc_rsp ) + ); + + //////////////////////// + // Instiantiate CDC // + //////////////////////// + + if (cfg.EnCdc) begin : gen_cdc + axi_cdc #( + .aw_chan_t ( axi_dw_iw_aw_chan_t), + .w_chan_t ( axi_dw_iw_w_chan_t), + .b_chan_t ( axi_dw_iw_b_chan_t), + .ar_chan_t ( axi_dw_iw_ar_chan_t), + .r_chan_t ( axi_dw_iw_r_chan_t), + .axi_req_t ( axi_dw_iw_req_t), + .axi_resp_t ( axi_dw_iw_resp_t), + .LogDepth ( cfg.CdcLogDepth ) + ) i_axi_cdc_mig ( + .src_clk_i ( soc_clk_i ), + .src_rst_ni ( soc_resetn_i ), + .src_req_i ( iresizer_cdc_req ), + .src_resp_o ( iresizer_cdc_rsp ), + .dst_clk_i ( dram_axi_clk ), + .dst_rst_ni ( ~dram_rst_o ), + .dst_req_o ( cdc_dram_req ), + .dst_resp_i ( cdc_dram_rsp ) + ); + end else begin : gen_no_cdc + assign cdc_dram_req = iresizer_cdc_req; + assign iresizer_cdc_rsp = cdc_dram_rsp; + end + + //////////////////////////////// + // Map User, Resize Address // + //////////////////////////////// + + assign cdc_dram_rsp.b.user = '0; + assign cdc_dram_rsp.r.user = '0; + + logic [cfg.AddrWidth-1:0] cdc_dram_req_aw_addr; + logic [cfg.AddrWidth-1:0] cdc_dram_req_ar_addr; + + assign cdc_dram_req_aw_addr = cdc_dram_req.aw.addr[cfg.AddrWidth-1:0]; + assign cdc_dram_req_ar_addr = cdc_dram_req.ar.addr[cfg.AddrWidth-1:0]; + + ///////////////////////// + // Instiantiate DDR4 // + ///////////////////////// + +`ifdef USE_DDR4 + ddr4 i_dram ( + // Reset + .sys_rst ( sys_rst_i ), // Active high + .c0_sys_clk_i ( dram_clk_i ), + .c0_ddr4_aresetn ( soc_resetn_i ), + // Clock and reset out + .c0_ddr4_ui_clk ( dram_axi_clk ), + .c0_ddr4_ui_clk_sync_rst ( dram_rst_o ), + // AXI + .c0_ddr4_s_axi_awid ( cdc_dram_req.aw.id ), + .c0_ddr4_s_axi_awaddr ( cdc_dram_req_aw_addr ), + .c0_ddr4_s_axi_awlen ( cdc_dram_req.aw.len ), + .c0_ddr4_s_axi_awsize ( cdc_dram_req.aw.size ), + .c0_ddr4_s_axi_awburst ( cdc_dram_req.aw.burst ), + .c0_ddr4_s_axi_awlock ( cdc_dram_req.aw.lock ), + .c0_ddr4_s_axi_awcache ( cdc_dram_req.aw.cache ), + .c0_ddr4_s_axi_awprot ( cdc_dram_req.aw.prot ), + .c0_ddr4_s_axi_awqos ( cdc_dram_req.aw.qos ), + .c0_ddr4_s_axi_awvalid ( cdc_dram_req.aw_valid ), + .c0_ddr4_s_axi_awready ( cdc_dram_rsp.aw_ready ), + .c0_ddr4_s_axi_wdata ( cdc_dram_req.w.data ), + .c0_ddr4_s_axi_wstrb ( cdc_dram_req.w.strb ), + .c0_ddr4_s_axi_wlast ( cdc_dram_req.w.last ), + .c0_ddr4_s_axi_wvalid ( cdc_dram_req.w_valid ), + .c0_ddr4_s_axi_wready ( cdc_dram_rsp.w_ready ), + .c0_ddr4_s_axi_bready ( cdc_dram_req.b_ready ), + .c0_ddr4_s_axi_bid ( cdc_dram_rsp.b.id ), + .c0_ddr4_s_axi_bresp ( cdc_dram_rsp.b.resp ), + .c0_ddr4_s_axi_bvalid ( cdc_dram_rsp.b_valid ), + .c0_ddr4_s_axi_arid ( cdc_dram_req.ar.id ), + .c0_ddr4_s_axi_araddr ( cdc_dram_req_ar_addr ), + .c0_ddr4_s_axi_arlen ( cdc_dram_req.ar.len ), + .c0_ddr4_s_axi_arsize ( cdc_dram_req.ar.size ), + .c0_ddr4_s_axi_arburst ( cdc_dram_req.ar.burst ), + .c0_ddr4_s_axi_arlock ( cdc_dram_req.ar.lock ), + .c0_ddr4_s_axi_arcache ( cdc_dram_req.ar.cache ), + .c0_ddr4_s_axi_arprot ( cdc_dram_req.ar.prot ), + .c0_ddr4_s_axi_arqos ( cdc_dram_req.ar.qos ), + .c0_ddr4_s_axi_arvalid ( cdc_dram_req.ar_valid ), + .c0_ddr4_s_axi_arready ( cdc_dram_rsp.ar_ready ), + .c0_ddr4_s_axi_rready ( cdc_dram_req.r_ready ), + .c0_ddr4_s_axi_rid ( cdc_dram_rsp.r.id ), + .c0_ddr4_s_axi_rdata ( cdc_dram_rsp.r.data ), + .c0_ddr4_s_axi_rresp ( cdc_dram_rsp.r.resp ), + .c0_ddr4_s_axi_rlast ( cdc_dram_rsp.r.last ), + .c0_ddr4_s_axi_rvalid ( cdc_dram_rsp.r_valid ), + // TODO: Shouldn't we map this to an external reg port? + // AXI control + .c0_ddr4_s_axi_ctrl_awvalid ( '0 ), + .c0_ddr4_s_axi_ctrl_awready ( ), + .c0_ddr4_s_axi_ctrl_awaddr ( '0 ), + .c0_ddr4_s_axi_ctrl_wvalid ( '0 ), + .c0_ddr4_s_axi_ctrl_wready ( ), + .c0_ddr4_s_axi_ctrl_wdata ( '0 ), + .c0_ddr4_s_axi_ctrl_bvalid ( ), + .c0_ddr4_s_axi_ctrl_bready ( '0 ), + .c0_ddr4_s_axi_ctrl_bresp ( ), + .c0_ddr4_s_axi_ctrl_arvalid ( '0 ), + .c0_ddr4_s_axi_ctrl_arready ( ), + .c0_ddr4_s_axi_ctrl_araddr ( '0 ), + .c0_ddr4_s_axi_ctrl_rvalid ( ), + .c0_ddr4_s_axi_ctrl_rready ( '0 ), + .c0_ddr4_s_axi_ctrl_rdata ( ), + .c0_ddr4_s_axi_ctrl_rresp ( ), + .c0_ddr4_interrupt ( ), + // Others + .c0_init_calib_complete ( ), + .addn_ui_clkout1 ( dram_clk_o ), + .dbg_clk ( ), + .dbg_bus ( ), + // PHY + .* + ); +`endif + + ///////////////////////// + // Instiantiate DDR3 // + ///////////////////////// + +`ifdef USE_DDR3 + mig7s i_dram ( + .sys_rst ( sys_rst_i ), // Active high + .sys_clk_i ( dram_clk_i ), + .ui_clk ( dram_axi_clk ), + .ui_clk_sync_rst ( dram_rst_o ), + .mmcm_locked ( ), + .app_sr_req ( '0 ), + .app_ref_req ( '0 ), + .app_zq_req ( '0 ), + .app_sr_active ( ), + .app_ref_ack ( ), + .app_zq_ack ( ), + .aresetn ( soc_resetn_i ), + .s_axi_awid ( cdc_dram_req.aw.id ), + .s_axi_awaddr ( cdc_dram_req_aw_addr ), + .s_axi_awlen ( cdc_dram_req.aw.len ), + .s_axi_awsize ( cdc_dram_req.aw.size ), + .s_axi_awburst ( cdc_dram_req.aw.burst ), + .s_axi_awlock ( cdc_dram_req.aw.lock ), + .s_axi_awcache ( cdc_dram_req.aw.cache ), + .s_axi_awprot ( cdc_dram_req.aw.prot ), + .s_axi_awqos ( cdc_dram_req.aw.qos ), + .s_axi_awvalid ( cdc_dram_req.aw_valid ), + .s_axi_awready ( cdc_dram_rsp.aw_ready ), + .s_axi_wdata ( cdc_dram_req.w.data ), + .s_axi_wstrb ( cdc_dram_req.w.strb ), + .s_axi_wlast ( cdc_dram_req.w.last ), + .s_axi_wvalid ( cdc_dram_req.w_valid ), + .s_axi_wready ( cdc_dram_rsp.w_ready ), + .s_axi_bready ( cdc_dram_req.b_ready ), + .s_axi_bid ( cdc_dram_rsp.b.id ), + .s_axi_bresp ( cdc_dram_rsp.b.resp ), + .s_axi_bvalid ( cdc_dram_rsp.b_valid ), + .s_axi_arid ( cdc_dram_req.ar.id ), + .s_axi_araddr ( cdc_dram_req_ar_addr ), + .s_axi_arlen ( cdc_dram_req.ar.len ), + .s_axi_arsize ( cdc_dram_req.ar.size ), + .s_axi_arburst ( cdc_dram_req.ar.burst ), + .s_axi_arlock ( cdc_dram_req.ar.lock ), + .s_axi_arcache ( cdc_dram_req.ar.cache ), + .s_axi_arprot ( cdc_dram_req.ar.prot ), + .s_axi_arqos ( cdc_dram_req.ar.qos ), + .s_axi_arvalid ( cdc_dram_req.ar_valid ), + .s_axi_arready ( cdc_dram_rsp.ar_ready ), + .s_axi_rready ( cdc_dram_req.r_ready ), + .s_axi_rid ( cdc_dram_rsp.r.id ), + .s_axi_rdata ( cdc_dram_rsp.r.data ), + .s_axi_rresp ( cdc_dram_rsp.r.resp ), + .s_axi_rlast ( cdc_dram_rsp.r.last ), + .s_axi_rvalid ( cdc_dram_rsp.r_valid ), + .init_calib_complete ( ), + .device_temp ( ), + // PHY + .* + ); +`endif // USE_DDR3 + +endmodule diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/src/ips/genesys2.mig7s.prj old mode 100755 new mode 100644 similarity index 97% rename from target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj rename to target/xilinx/src/ips/genesys2.mig7s.prj index eca03782..a4991cd3 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj +++ b/target/xilinx/src/ips/genesys2.mig7s.prj @@ -1,7 +1,7 @@ - xlnx_mig_7_ddr3 + mig7s 1 1 OFF @@ -10,9 +10,9 @@ Enabled xc7k325t-ffg900/-2 4.1 - Differential + No Buffer Use System Clock - ACTIVE LOW + ACTIVE HIGH FALSE 0 50 Ohms @@ -116,9 +116,6 @@ - - - @@ -152,7 +149,7 @@ RD_PRI_REG 30 64 - 6 + 4 0 diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh new file mode 100644 index 00000000..a4d7798d --- /dev/null +++ b/target/xilinx/src/phy_definitions.svh @@ -0,0 +1,83 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Cyril Koenig + +`ifdef TARGET_VCU128 + `define USE_RESET + `define USE_JTAG + `define USE_JTAG_VDDGND + `define USE_DDR4 + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO +`endif + +`ifdef TARGET_GENESYS2 + `define USE_RESETN + `define USE_JTAG + `define USE_JTAG_TRSTN + `define USE_SD + `define USE_SWITCHES + `define USE_DDR3 + `define USE_FAN + `define USE_VIO + `define USE_I2C + `define USE_VGA +`endif + +`ifdef TARGET_ZCU102 + `define USE_RESET + `define USE_JTAG + `define USE_DDR4 + `define USE_VIO +`endif + +///////////////////// +// DRAM INTERFACES // +///////////////////// + +`ifdef USE_DDR4 +`define USE_DDR +`endif +`ifdef USE_DDR3 +`define USE_DDR +`endif + +`define DDR4_INTF \ + output c0_ddr4_reset_n, \ + output [0:0] c0_ddr4_ck_t, \ + output [0:0] c0_ddr4_ck_c, \ + output c0_ddr4_act_n, \ + output [16:0] c0_ddr4_adr, \ + output [1:0] c0_ddr4_ba, \ + output [0:0] c0_ddr4_bg, \ + output [0:0] c0_ddr4_cke, \ + output [0:0] c0_ddr4_odt, \ + output [1:0] c0_ddr4_cs_n, \ + inout [8:0] c0_ddr4_dm_dbi_n, \ + inout [71:0] c0_ddr4_dq, \ + inout [8:0] c0_ddr4_dqs_c, \ + inout [8:0] c0_ddr4_dqs_t, + +`define DDR3_INTF \ + output ddr3_ck_p, \ + output ddr3_ck_n, \ + inout [31:0] ddr3_dq, \ + inout [3:0] ddr3_dqs_n, \ + inout [3:0] ddr3_dqs_p, \ + output [14:0] ddr3_addr, \ + output [2:0] ddr3_ba, \ + output ddr3_ras_n, \ + output ddr3_cas_n, \ + output ddr3_we_n, \ + output ddr3_reset_n, \ + output [0:0] ddr3_cke, \ + output [0:0] ddr3_cs_n, \ + output [3:0] ddr3_dm, \ + output [0:0] ddr3_odt, + +`define ila(__name, __signal) \ + (* dont_touch = "yes" *) (* mark_debug = "true" *) logic [$bits(__signal)-1:0] __name; \ + assign __name = __signal; diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk new file mode 100644 index 00000000..be35b5a9 --- /dev/null +++ b/target/xilinx/xilinx.mk @@ -0,0 +1,91 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Nicole Narr +# Christopher Reinwardt +# Cyril Koenig +# Paul Scheffler + +VIVADO ?= vitis-2022.1 vivado + +CHS_XILINX_DIR ?= $(CHS_ROOT)/target/xilinx + +# Required to split stems +.SECONDEXPANSION: + +############## +# Xilinx IPs # +############## + +.PRECIOUS: $(CHS_XILINX_DIR)/build/%/ $(CHS_XILINX_DIR)/build/%/out.xci + +$(CHS_XILINX_DIR)/build/%/: + mkdir -p $@ + +# We split the stem into a board and an IP and resolve dependencies accordingly +$(CHS_XILINX_DIR)/build/%/out.xci: \ + $(CHS_XILINX_DIR)/scripts/impl_ip.tcl \ + $$(wildcard $(CHS_XILINX_DIR)/src/ips/$$*.prj) \ + | $(CHS_XILINX_DIR)/build/%/ + @rm -f $(CHS_XILINX_DIR)/build/$(*)*.log $(CHS_XILINX_DIR)/build/$(*)*.jou + cd $| && $(VIVADO) -mode batch -log ../$*.log -jou ../$*.jou -source $< -tclargs "$(subst ., ,$*)" + +############## +# Bitstreams # +############## + +CHS_XILINX_BOARDS := genesys2 vcu128 + +CHS_XILINX_IPS_genesys2 := clkwiz vio mig7s +CHS_XILINX_IPS_vcu128 := clkwiz vio ddr4 + +$(CHS_XILINX_DIR)/scripts/add_sources.%.tcl: $(CHS_ROOT)/Bender.yml + $(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t $* > $@ + +define chs_xilinx_bit_rule +$$(CHS_XILINX_DIR)/out/%.$(1).bit: \ + $$(CHS_XILINX_DIR)/scripts/impl_sys.tcl \ + $$(CHS_XILINX_DIR)/scripts/add_sources.$(1).tcl \ + $$(CHS_XILINX_IPS_$(1):%=$(CHS_XILINX_DIR)/build/$(1).%/out.xci) \ + $$(CHS_HW_ALL) \ + | $$(CHS_XILINX_DIR)/build/$(1).%/ + @rm -f $$(CHS_XILINX_DIR)/build/$$*.$(1)*.log $$(CHS_XILINX_DIR)/build/$$*.$(1)*.jou + cd $$| && $$(VIVADO) -mode batch -log ../$$*.$(1).log -jou ../$$*.$(1).jou -source $$< \ + -tclargs "$(1) $$* $$(CHS_XILINX_IPS_$(1):%=$$(CHS_XILINX_DIR)/build/$(1).%/out.xci)" + +.PHONY: chs-xilinx-$(1) +chs-xilinx-$(1): $$(CHS_XILINX_DIR)/out/cheshire.$(1).bit +endef + +$(foreach board,$(CHS_XILINX_BOARDS),$(eval $(call chs_xilinx_bit_rule,$(board)))) + +# Builds bitstreams for all available boards +CHS_XILINX_ALL = $(foreach board,$(CHS_XILINX_BOARDS),$$(CHS_XILINX_DIR)/out/cheshire.$(board).bit) + +############# +# Utilities # +############# + +# Parameters for HW server (defaults are for a unique board @ localhost). +# `CHS_XILINX_HWS_PATH_$(board)` overrides the device path for each board (default *). +CHS_XILINX_HWS_URL ?= localhost:3121 + +# We build the dependency file $(2) only if it does not exist; it must not be up to date. +define chs_xilinx_util_rule +chs-xilinx-$(1)-%: $$(CHS_XILINX_DIR)/scripts/util/$(1).tcl | $$(CHS_XILINX_DIR)/build/%.$(1)/ + [ -e $(subst %,$$*,$(2)) ] || $$(MAKE) $(subst %,$$*,$(2)) + @rm -f $$(CHS_XILINX_DIR)/build/$$(*)*.$(1).log $$(CHS_XILINX_DIR)/build/$$(*)*.$(1).jou + cd $$| && $$(VIVADO) -mode batch -log ../$$(*).$(1).log -jou ../$$(*).$(1).jou -source $$< \ + -tclargs "$$(CHS_XILINX_HWS_URL) $$(or $$(CHS_XILINX_HWS_PATH_$$*),*) $$* $(subst %,$$*,$(2)) 0" +endef + +# Program bitstream onto board +.PHONY: chs-xilinx-program-% +$(eval $(call chs_xilinx_util_rule,program,$(CHS_XILINX_DIR)/out/cheshire.%.bit)) + +# Flash onboard memory with the file `CHS_XILINX_FLASH_IMG` (only selected boards). +# `%` is substituted with the board name. The default is the Linux disk image for that board. +CHS_XILINX_FLASH_IMG ?= $(CHS_SW_DIR)/boot/linux.%.gpt.bin +.PHONY: chs-xilinx-flash-% +$(eval $(call chs_xilinx_util_rule,flash,$(CHS_XILINX_FLASH_IMG))) diff --git a/target/xilinx/xilinx/.gitignore b/target/xilinx/xilinx/.gitignore deleted file mode 100644 index 12ef7f9f..00000000 --- a/target/xilinx/xilinx/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -xlnx*/* -!xlnx*/tcl -!Makefile -!common.mk -!*.prj \ No newline at end of file diff --git a/target/xilinx/xilinx/common.mk b/target/xilinx/xilinx/common.mk deleted file mode 100644 index b75c9bfa..00000000 --- a/target/xilinx/xilinx/common.mk +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# select IIS-internal tool commands if we run on IIS machines -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2020.2 vivado -else - VIVADO ?= vivado -endif - -all: - $(VIVADO) -mode batch -source tcl/run.tcl - -gui: - $(VIVADO) -mode gui -source tcl/run.tcl & - -clean: - rm -rf ip/* - mkdir -p ip - rm -rf ${PROJECT}.* - rm -rf component.xml - rm -rf vivado*.jou - rm -rf vivado*.log - rm -rf vivado*.str - rm -rf xgui - rm -rf .Xil diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile b/target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile deleted file mode 100644 index 028b08d7..00000000 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_mig_7_ddr3 -include ../common.mk \ No newline at end of file diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj deleted file mode 100644 index a523f973..00000000 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj +++ /dev/null @@ -1,200 +0,0 @@ - - - - xlnx_mig_7_ddr3 - 1 - 1 - OFF - 1024 - ON - Enabled - xc7k325t-ffg900/-2 - 4.1 - Differential - Use System Clock - ACTIVE LOW - FALSE - 0 - 50 Ohms - 1 - - DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 - 1250 - 2.0V - 4:1 - 200 - 0 - 800 - 16 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - 4 - FALSE - - 14 - 10 - 3 - 1.5V - BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/7 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - AXI - - RD_PRI_REG - 30 - 64 - 4 - 0 - - - - diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj deleted file mode 100644 index fcf0bbe9..00000000 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj +++ /dev/null @@ -1,203 +0,0 @@ - - - - xlnx_mig_7_ddr3 - 1 - 1 - OFF - 1024 - ON - Enabled - xc7vx485t-ffg1761/-2 - 4.1 - Differential - Use System Clock - ACTIVE LOW - FALSE - 0 - 50 Ohms - 0 - - DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 - 1250 - 2.0V - 4:1 - 200 - 0 - 800 - 1.000 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - 4 - FALSE - - 14 - 10 - 3 - 1.5V - BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/7 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - AXI - - RD_PRI_REG - 30 - 64 - 5 - 0 - - - - diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl b/target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl deleted file mode 100644 index 9fc5f5cd..00000000 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# -# Author: Florian Zaruba - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) -set boardNameShort $::env(BOARD) - -set ipName xlnx_mig_7_ddr3 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName - -exec cp mig_$boardNameShort.prj ./$ipName.srcs/sources_1/ip/$ipName/mig_a.prj - -set_property -dict [list CONFIG.XML_INPUT_FILE {mig_a.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/target/xilinx/xilinx/xlnx_protocol_checker/Makefile b/target/xilinx/xilinx/xlnx_protocol_checker/Makefile deleted file mode 100644 index f67c6a7b..00000000 --- a/target/xilinx/xilinx/xlnx_protocol_checker/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -PROJECT:=xlnx_protocol_checker -include ../common.mk \ No newline at end of file diff --git a/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl b/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl deleted file mode 100644 index 2e6ebfcf..00000000 --- a/target/xilinx/xilinx/xlnx_protocol_checker/tcl/run.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# Copyright 2018 ETH Zurich and University of Bologna. -# Solderpad Hardware License, Version 0.51, see LICENSE for details. -# SPDX-License-Identifier: SHL-0.51 -# - -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -set ipName xlnx_protocol_checker - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_protocol_checker -vendor xilinx.com -library ip -version 2.0 -module_name $ipName - -set_property -dict [list CONFIG.ADDR_WIDTH {48} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {6} \ - CONFIG.AWUSER_WIDTH {1} \ - CONFIG.ARUSER_WIDTH {1} \ - CONFIG.RUSER_WIDTH {1} \ - CONFIG.WUSER_WIDTH {1} \ - CONFIG.BUSER_WIDTH {1} \ - CONFIG.MAX_AW_WAITS {1024} \ - CONFIG.MAX_AR_WAITS {1024} \ - CONFIG.MAX_W_WAITS {1024} \ - CONFIG.MAX_R_WAITS {1024} \ - CONFIG.MAX_B_WAITS {1024} \ - CONFIG.MAX_CONTINUOUS_WTRANSFERS_WAITS {1024} \ - CONFIG.MAX_WLAST_TO_AWVALID_WAITS {1024} \ - CONFIG.MAX_WRITE_TO_BVALID_WAITS {1024} \ - CONFIG.MAX_CONTINUOUS_RTRANSFERS_WAITS {1024} \ - ] [get_ips $ipName] - - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 \ No newline at end of file diff --git a/util/openocd.cfg b/util/openocd.common.tcl similarity index 61% rename from util/openocd.cfg rename to util/openocd.common.tcl index c57a9ef6..7474f015 100644 --- a/util/openocd.cfg +++ b/util/openocd.common.tcl @@ -1,26 +1,16 @@ -# Copyright 2022 ETH Zurich and University of Bologna. +# Copyright 2024 ETH Zurich and University of Bologna. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# Nicole Narr -# Christopher Reinwardt - -# TODO: This file should be reworked and harmonized between targets. - -adapter_khz 1000 - -# this supports JTAG-HS2 (and apparently Nexys4 as well) - -interface ftdi -ftdi_vid_pid 0x0403 0x6014 - -ftdi_channel 0 -ftdi_layout_init 0x00e8 0x60eb +# Common OpenOCD script for Cheshire. +transport select jtag +telnet_port disabled +tcl_port disabled reset_config none set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 +jtag newtap $_CHIPNAME cpu -irlen ${irlen} -expected-id 0x1c5e5db3 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 @@ -31,7 +21,6 @@ gdb_report_register_access_error enable riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 -# prefer to use sba for system bus access riscv set_prefer_sba off # Try enabling address translation (only works for newer versions) diff --git a/util/openocd.genesys2.tcl b/util/openocd.genesys2.tcl new file mode 100644 index 00000000..fc146048 --- /dev/null +++ b/util/openocd.genesys2.tcl @@ -0,0 +1,14 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# OpenOCD script for Cheshire on Genesys2. + +adapter_khz 2000 +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x00e8 0x60eb +ftdi_channel 0 +set irlen 5 + +source [file dirname [info script]]/openocd.common.tcl diff --git a/util/openocd.hs2.tcl b/util/openocd.hs2.tcl new file mode 100644 index 00000000..c0a83b56 --- /dev/null +++ b/util/openocd.hs2.tcl @@ -0,0 +1,14 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# OpenOCD script for Cheshire through Digilent HS2 adapter. + +adapter_khz 2000 +interface ftdi +ftdi_vid_pid 0x0403 0x6014 +ftdi_layout_init 0x00e8 0x60eb +ftdi_channel 0 +set irlen 5 + +source [file dirname [info script]]/openocd.common.tcl