From 3b7df55ed3a31febbcf670378ef980ea4f0ec39d Mon Sep 17 00:00:00 2001
From: Yvan Tortorella <ytortorella@lagrev3.ee.ethz.ch>
Date: Wed, 13 Dec 2023 13:35:36 +0100
Subject: [PATCH] Try to fix lint errors.

---
 sw/include/util.h    | 22 +++++++++++-----------
 sw/lib/cheshire_io.c | 14 +++++++-------
 sw/lib/dif/uart.c    |  2 +-
 sw/lib/init.c        |  4 ++--
 4 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/sw/include/util.h b/sw/include/util.h
index 4e595474c..40bcc3b90 100644
--- a/sw/include/util.h
+++ b/sw/include/util.h
@@ -83,30 +83,30 @@ static inline void *gprw(void *gp) {
 
 // Read hart ID
 static inline unsigned int hart_id() {
-  int hart_id;
-  asm volatile("csrr %0, mhartid" : "=r" (hart_id) : );
-  return hart_id;
+    int hart_id;
+    asm volatile("csrr %0, mhartid" : "=r" (hart_id) :);
+    return hart_id;
 }
 
 // Disable data caches
-static inline void disable_dcache(){
-  asm volatile("csrrwi x0, 0x701, 0x0 \n\t" : : : "memory");
+static inline void disable_dcache() {
+    asm volatile("csrrwi x0, 0x701, 0x0 \n\t" : : : "memory");
 }
 
 // Enable data caches
-static inline void enable_dcache(){
-  asm volatile("csrrwi x0, 0x701, 0x1 \n\t" : : : "memory");
+static inline void enable_dcache() {
+    asm volatile("csrrwi x0, 0x701, 0x1 \n\t" : : : "memory");
 }
 
 // The following is for future DMR support
 // Wake up sleeping hart using CLINT
 // static inline void wakeup_hart(unsigned int hart_id) {
-//   *reg32(&__base_clint, 0x4*hart_id) = 0x1;
-//   *reg32(&__base_clint, 0x4*hart_id) = 0x0;
+//     *reg32(&__base_clint, 0x4*hart_id) = 0x1;
+//     *reg32(&__base_clint, 0x4*hart_id) = 0x0;
 // }
 
 // Write synchronization request in dedicated register
 // static inline void sync_req(unsigned int hart_id){
-//   uint32_t sync_reg = *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET);
-//   *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET) = sync_reg | (0x1 << hart_id);
+//     uint32_t sync_reg = *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET);
+//     *reg32(&__base_regs, CHESHIRE_HARTS_SYNC_REG_OFFSET) = sync_reg | (0x1 << hart_id);
 // }
diff --git a/sw/lib/cheshire_io.c b/sw/lib/cheshire_io.c
index 45fe9aac8..1d7230326 100644
--- a/sw/lib/cheshire_io.c
+++ b/sw/lib/cheshire_io.c
@@ -9,11 +9,11 @@
 #include "cheshire_io.h"
 
 void cheshire_init_io() {
-  // Initialize UART first
-  uart_open();
-  
-  // Initialize other IOs
-  // .
-  // .
-  // .
+    // Initialize UART first
+    uart_open();
+
+    // Initialize other IOs
+    // .
+    // .
+    // .
 };
diff --git a/sw/lib/dif/uart.c b/sw/lib/dif/uart.c
index 7bac8e8ff..a190af0cb 100644
--- a/sw/lib/dif/uart.c
+++ b/sw/lib/dif/uart.c
@@ -66,7 +66,7 @@ void uart_read_str(void *uart_base, void *dst, uint64_t len) {
 }
 
 // Default UART provides console
-void uart_open(){
+void uart_open() {
     uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
     uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500);
     uart_init(&__base_uart, reset_freq, 115200);
diff --git a/sw/lib/init.c b/sw/lib/init.c
index 6960549e0..a0f5dc023 100644
--- a/sw/lib/init.c
+++ b/sw/lib/init.c
@@ -9,6 +9,6 @@
 #include "init.h"
 
 void soc_init() {
-  // IO initialization
-  cheshire_init_io();
+    // IO initialization
+    cheshire_init_io();
 };