From 299ece41d9f261ea99c0e280e5c35412d6014c6c Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 19 Sep 2023 10:39:17 +0200 Subject: [PATCH] UNBENT: Allow for custom Err bits on AXI user --- Bender.lock | 4 ++-- Bender.yml | 2 +- hw/cheshire_pkg.sv | 4 ++++ hw/cheshire_soc.sv | 12 ++++++------ 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/Bender.lock b/Bender.lock index f380b3b4..13c282b8 100644 --- a/Bender.lock +++ b/Bender.lock @@ -179,8 +179,8 @@ packages: dependencies: - common_verification unbent: - revision: 791420b326c6455595b4444c02f05f180b99dd06 - version: 0.1.1 + revision: 89ea12018002e6fae51f88e25320e79f57db8073 + version: 0.1.5 source: Git: https://github.com/pulp-platform/unbent.git dependencies: diff --git a/Bender.yml b/Bender.yml index b072d9b0..b5c9bc08 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,7 +29,7 @@ dependencies: serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 } clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", rev: d1d3135 } # TODO: master commit; use next release once out - unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.1 } + unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.5 } export_include_dirs: - hw/include diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 0b46c6db..461586a2 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -97,6 +97,8 @@ package cheshire_pkg; // A '0 user signal indicates no atomics. dw_bt AxiUserAmoMsb; dw_bt AxiUserAmoLsb; + dw_bt AxiUserErrBits; + dw_bt AxiUserErrLsb; doub_bt AxiUserDefault; // Default user assignment, adjusted by user features (AMO) // Reg parameters dw_bt RegMaxReadTxns; @@ -525,6 +527,8 @@ package cheshire_pkg; AxiMaxSlvTrans : 24, AxiUserAmoMsb : 1, // Convention: lower AMO bits for cores, MSB for serial link AxiUserAmoLsb : 0, // Convention: lower AMO bits for cores, MSB for serial link + AxiUserErrBits : 0, + AxiUserErrLsb : 0, AxiUserDefault : 0, RegMaxReadTxns : 8, RegMaxWriteTxns : 8, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 03566135..ba1516a5 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -634,8 +634,8 @@ module cheshire_soc import cheshire_pkg::*; #( axi_err_unit_wrap #( .AddrWidth ( Cfg.AddrWidth ), .IdWidth ( Cva6IdWidth ), - .UserErrBits ( 0 ), - .UserErrBitsOffset ( 0 ), + .UserErrBits ( Cfg.AxiUserErrBits ), + .UserErrBitsOffset ( Cfg.AxiUserErrLsb ), .NumOutstanding ( Cfg.CoreMaxTxns ), .NumStoredErrors ( 4 ), .DropOldest ( 1'b0 ), @@ -1447,8 +1447,8 @@ module cheshire_soc import cheshire_pkg::*; #( axi_err_unit_wrap #( .AddrWidth ( Cfg.AddrWidth ), .IdWidth ( Cfg.AxiMstIdWidth ), - .UserErrBits ( 0 ), - .UserErrBitsOffset ( 0 ), + .UserErrBits ( Cfg.AxiUserErrBits ), + .UserErrBitsOffset ( Cfg.AxiUserErrLsb ), .NumOutstanding ( Cfg.CoreMaxTxns ), .NumStoredErrors ( 4 ), .DropOldest ( 1'b0 ), @@ -1619,8 +1619,8 @@ module cheshire_soc import cheshire_pkg::*; #( axi_err_unit_wrap #( .AddrWidth ( Cfg.AddrWidth ), .IdWidth ( Cfg.AxiMstIdWidth ), - .UserErrBits ( 0 ), - .UserErrBitsOffset ( 0 ), + .UserErrBits ( Cfg.AxiUserErrBits ), + .UserErrBitsOffset ( Cfg.AxiUserErrLsb ), .NumOutstanding ( Cfg.CoreMaxTxns ), .NumStoredErrors ( 4 ), .DropOldest ( 1'b0 ),