From 20675b398e971901f8f5e8a696c6dc3e5275072a Mon Sep 17 00:00:00 2001 From: Zexin Fu Date: Mon, 15 Jan 2024 04:43:22 +0100 Subject: [PATCH] 1.Update pulp_c910 dependency, fix the amo access fault and timer interrupt bug. 2.Add trc port to c910 core. 3.Add 2 more preload binary files for simulation, to load fw_payload(opensbi+uboot), vmlinux, dtb resoectively. --- Bender.lock | 2 +- Bender.yml | 2 +- hw/cheshire_soc.sv | 14 +++--- target/sim/src/spike.sv | 59 ++++++++++++++++---------- target/sim/src/tb_cheshire_soc.sv | 6 ++- target/sim/src/vip_cheshire_soc.sv | 38 +++++++++++++---- target/sim/vsim/start.cheshire_soc.tcl | 17 +++++--- 7 files changed, 90 insertions(+), 48 deletions(-) diff --git a/Bender.lock b/Bender.lock index 9f1cf886..c77c7b9f 100644 --- a/Bender.lock +++ b/Bender.lock @@ -145,7 +145,7 @@ packages: - register_interface - tech_cells_generic pulp_c910: - revision: 546ceba4e4b445e29154b078a54425e40a8b877d + revision: 44f1bd325def3c43be06ef84ee69ce4880ab3b71 version: null source: Git: git@iis-git.ee.ethz.ch:nwistoff/pulp_c910.git diff --git a/Bender.yml b/Bender.yml index f3120ba4..a925f0ba 100644 --- a/Bender.yml +++ b/Bender.yml @@ -33,7 +33,7 @@ dependencies: # soc910: { git: "git@iis-git.ee.ethz.ch:nwistoff/soc910.git", rev: 7c218d05 } # register_interface: { path: vendor/pulp_register_interface } # soc910: { path: soc910/hw/system } - pulp_c910: { git: "git@iis-git.ee.ethz.ch:nwistoff/pulp_c910.git", rev: 546ceba4 } + pulp_c910: { git: "git@iis-git.ee.ethz.ch:nwistoff/pulp_c910.git", rev: 44f1bd32 } export_include_dirs: - hw/include diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index 9b9783bf..a4381ecc 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -145,8 +145,9 @@ module cheshire_soc cheshire_intr_t [NumRtdIntrTgts-1:0] intr_routed; // Interrupt requests to all interruptible harts - cheshire_xeip_t [NumIrqHarts-1:0] xeip; - logic [NumIrqHarts-1:0] mtip, msip; + (* mark_debug = "true" *) cheshire_xeip_t [NumIrqHarts-1:0] xeip; + (* mark_debug = "true" *) logic [NumIrqHarts-1:0] mtip; + (* mark_debug = "true" *) logic [NumIrqHarts-1:0] msip; // Interrupt 0 is hardwired to zero by convention. // Other internal interrupts are synchronous (for now) and need not be synced; @@ -671,6 +672,7 @@ module cheshire_soc ) i_c910_axi_wrap ( .clk_i, .rst_ni, + .rtc_i, // clint .ipi_i ( msip[i] ), .time_irq_i ( mtip[i] ), @@ -685,8 +687,8 @@ module cheshire_soc .jtag_tck_i ( jtag_tck_i ), .jtag_tdi_i ( jtag_tdi_i ), .jtag_tms_i ( jtag_tms_i ), - .jtag_tdo_o ( jtag_tdo_o ), - .jtag_tdo_en_o ( jtag_tdo_oe_o ), + .jtag_tdo_o ( /*jtag_tdo_o*/ ), + .jtag_tdo_en_o ( /*jtag_tdo_oe_o*/ ), .jtag_trst_ni ( jtag_trst_ni ), // AXI interface .axi_req_o ( c910_out_req_s1 ), @@ -1202,8 +1204,8 @@ module cheshire_soc .tms_i ( jtag_tms_i ), .trst_ni ( jtag_trst_ni ), .td_i ( jtag_tdi_i ), - .td_o ( /*jtag_tdo_o*/ ), - .tdo_oe_o ( /*jtag_tdo_oe_o*/ ) + .td_o ( jtag_tdo_o ), + .tdo_oe_o ( jtag_tdo_oe_o ) ); // end diff --git a/target/sim/src/spike.sv b/target/sim/src/spike.sv index ff18fb5e..01afc970 100644 --- a/target/sim/src/spike.sv +++ b/target/sim/src/spike.sv @@ -12,7 +12,7 @@ // Date: 3/11/2018 // Description: Wrapped Spike Model for Tandem Verification -// `define DEBUG_DISPLAY +`define DEBUG_DISPLAY import uvm_pkg::*; `include "uvm_macros.svh" @@ -51,7 +51,7 @@ module spike #( parameter int unsigned NR_RETIRE_PORTS_W = $clog2(NR_RETIRE_PORTS) > 0 ? $clog2(NR_RETIRE_PORTS) : 1, parameter int unsigned MaxInFlightInstrNum = 64 * 3, // 64 ROB entries * max 3 fold instructions per entry parameter int unsigned MaxInFlightInstrNum_W = $clog2(MaxInFlightInstrNum) > 0 ? $clog2(MaxInFlightInstrNum) : 1, // 64 ROB entries * max 3 fold instructions per entry - parameter int unsigned SpikeRunAheadInstMax = 512 + parameter int unsigned SpikeRunAheadInstMax = 16 )( input logic clk_i, input logic rst_ni, @@ -70,6 +70,8 @@ module spike #( static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); string binary = ""; + string binary2 = ""; + string binary3 = ""; logic fake_clk; @@ -77,6 +79,8 @@ module spike #( initial begin void'(uvcl.get_arg_value("+PRELOAD=", binary)); + void'(uvcl.get_arg_value("+PRELOAD2=", binary2)); + void'(uvcl.get_arg_value("+PRELOAD3=", binary3)); assert(binary != "") else $error("We need a preloaded binary for tandem verification"); void'(spike_create(binary, DramBase, Size)); end @@ -102,7 +106,8 @@ module spike #( // $display("[spike UART] counter end @ %t ps", $time); // end spike_tick(commit_log_tmp); - if(commit_log_tmp.pc[39:0] == 40'h80008e6a) begin + // if(commit_log_tmp.pc[39:0] == 40'h800003f8) begin + if(commit_log_tmp.pc[39:0] == 40'h8000372c) begin spike_single_step = 1; end if(spike_single_step) begin @@ -224,7 +229,7 @@ module spike #( $display("Spike priv_lvl: %2d", commit_log_last_inst.priv); $display("TC910 priv_lvl: %2d", priv_lvl_i); $display("=========================================="); - $stop; + // $stop; end // check the csr @@ -252,26 +257,34 @@ module spike #( for(int k = 0; k < 32; k++) begin // check the register value $display("\x1B[x%d %h vs %h\x1B]", k, areg_value_i[k], commit_log_last_inst.areg_value[k]); - - if(^areg_value_i[k] !== 1'bx) begin - assert (areg_value_i[k] === commit_log_last_inst.areg_value[k]) else begin - $warning("\x1B[[Tandem] x%d register mismatches\x1B]", k); - $display("@ PC %h", commit_log_last_inst.pc); - $display("Spike x%d: %h", k, commit_log_last_inst.areg_value[k]); - $display("TC910 x%d: %h", k, areg_value_i[k]); - $display("=========================================="); - // $stop; - end - end else begin - assert (commit_log_last_inst.areg_value[k] === '0) else begin - $warning("\x1B[[Tandem] x%d register mismatches\x1B]", k); - $display("@ PC %h", commit_log_last_inst.pc); - $display("Spike x%d: %h", k, commit_log_last_inst.areg_value[k]); - $display("TC910 x%d: %h", k, areg_value_i[k]); - $display("=========================================="); - // $stop; - end + assert (areg_value_i[k] === commit_log_last_inst.areg_value[k]) else begin + $warning("\x1B[[Tandem] x%d register mismatches\x1B]", k); + $display("@ PC %h", commit_log_last_inst.pc); + $display("Spike x%d: %h", k, commit_log_last_inst.areg_value[k]); + $display("TC910 x%d: %h", k, areg_value_i[k]); + $display("=========================================="); + // $stop; end + + // if(^areg_value_i[k] !== 1'bx) begin + // assert (areg_value_i[k] === commit_log_last_inst.areg_value[k]) else begin + // $warning("\x1B[[Tandem] x%d register mismatches\x1B]", k); + // $display("@ PC %h", commit_log_last_inst.pc); + // $display("Spike x%d: %h", k, commit_log_last_inst.areg_value[k]); + // $display("TC910 x%d: %h", k, areg_value_i[k]); + // $display("=========================================="); + // // $stop; + // end + // end else begin + // assert (commit_log_last_inst.areg_value[k] === '0) else begin + // $warning("\x1B[[Tandem] x%d register mismatches\x1B]", k); + // $display("@ PC %h", commit_log_last_inst.pc); + // $display("Spike x%d: %h", k, commit_log_last_inst.areg_value[k]); + // $display("TC910 x%d: %h", k, areg_value_i[k]); + // $display("=========================================="); + // // $stop; + // end + // end end `endif break; diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index 56e446ee..a94b5b7c 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -13,6 +13,8 @@ module tb_cheshire_soc #( fixture_cheshire_soc #(.SelectedCfg(SelectedCfg)) fix(); string preload_elf; + string preload_elf2; + string preload_elf3; string boot_hex; logic [1:0] boot_mode; logic [1:0] preload_mode; @@ -23,6 +25,8 @@ module tb_cheshire_soc #( if (!$value$plusargs("BOOTMODE=%d", boot_mode)) boot_mode = 0; if (!$value$plusargs("PRELMODE=%d", preload_mode)) preload_mode = 0; if (!$value$plusargs("BINARY=%s", preload_elf)) preload_elf = ""; + if (!$value$plusargs("BINARY2=%s", preload_elf2)) preload_elf2 = ""; + if (!$value$plusargs("BINARY3=%s", preload_elf3)) preload_elf3 = ""; if (!$value$plusargs("IMAGE=%s", boot_hex)) boot_hex = ""; // Set boot mode and preload boot image if there is one @@ -47,7 +51,7 @@ module tb_cheshire_soc #( end 2: begin // UART fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code); end 3 : begin // MEM for simulation debug - fix.vip.memory_elf_run(preload_elf); + fix.vip.memory_elf_run(preload_elf, preload_elf2, preload_elf3); fix.vip.slink_wait_for_eoc(exit_code); end default: begin $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index f180563e..6759a444 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -94,26 +94,40 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // Preload function called by testbench task automatic memory_preload(string image); - // We overlay the entire memory with an alternating pattern - for (int k = 0; k < $size(i_dram_sim_mem.mem); ++k) - i_dram_sim_mem.mem[k] = 'h9a; + // // We overlay the entire memory with an alternating pattern + // for (int k = 0; k < $size(i_dram_sim_mem.mem); ++k) + // i_dram_sim_mem.mem[k] = 'h9a; // We load an image into chip 0 only if it exists if (image != "") begin $readmemh(image, i_dram_sim_mem.mem); $display("rtl load image: %s", image); end - - for(longint unsigned i = 'h80000000; i < 'h80000000+64; i++) begin - $display("%h, 0x%h", i, i_dram_sim_mem.mem[i]); - end endtask // Run a binary - task automatic memory_elf_run(input string binary); + task automatic memory_elf_run(input string binary, input string binary2, input string binary3); doub_bt entry; entry = DutCfg.LlcOutRegionStart; // Preload + // We overlay the entire memory with an alternating pattern + for (int k = 0; k < $size(i_dram_sim_mem.mem); ++k) + i_dram_sim_mem.mem[k] = 'h9a; + memory_preload(binary); + $stop(); + memory_preload(binary2); + $stop(); + memory_preload(binary3); + $stop(); + for(longint unsigned i = 'h80000000; i < 'h80000000+8; i++) begin + $display("%h, 0x%h", i, i_dram_sim_mem.mem[i]); + end + for(longint unsigned i = 'h80200000; i < 'h80200000+8; i++) begin + $display("%h, 0x%h", i, i_dram_sim_mem.mem[i]); + end + for(longint unsigned i = 'h81000000; i < 'h81000000+8; i++) begin + $display("%h, 0x%h", i, i_dram_sim_mem.mem[i]); + end // Write entry point slink_write_32(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_1_OFFSET, entry[63:32]); slink_write_32(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_0_OFFSET, entry[32:0]); @@ -431,7 +445,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( wait_for_reset(); forever begin uart_read_byte(bite); - $display("[UART] byte: %s", bite); + // $display("[UART] byte: %s", bite); if (uart_boot_ena) begin uart_boot_byte = bite; uart_boot_ena = 0; @@ -555,6 +569,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // We load an image into chip 0 only if it exists if (image != "") $readmemh(image, gen_i2c_eeproms[0].i_i2c_eeprom.MemoryBlock); + for(longint unsigned i = 'h0; i < 'h0+8; i++) begin + $display("i_i2c_eeprom %h, 0x%h", i, gen_i2c_eeproms[0].i_i2c_eeprom.MemoryBlock[i]); + end endtask //////////////// @@ -581,6 +598,9 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // We load an image into chip 0 only if it exists if (image != "") $readmemh(image, i_spi_norflash.Mem); + for(longint unsigned i = 'h0; i < 'h0+8; i++) begin + $display("i_spi_norflash %h, 0x%h", i, i_spi_norflash.Mem[i]); + end endtask /////////////////// diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index 61aea96f..0c0be233 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -11,14 +11,14 @@ set TESTBENCH tb_cheshire_soc # Set voptargs only if not already set to make overridable. # Default on fast simulation flags. -# if {![info exists VOPTARGS]} { -# set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" -# } - if {![info exists VOPTARGS]} { - set VOPTARGS "+acc" + set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar" } +# if {![info exists VOPTARGS]} { +# set VOPTARGS "+acc" +# } + set flags "-permissive -suppress 3009 -suppress 8386 -error 7 " if {[info exists SELCFG]} { append flags "-GSelectedCfg=${SELCFG} " } @@ -27,9 +27,12 @@ set pargs "" if {[info exists BOOTMODE]} { append pargs "+BOOTMODE=${BOOTMODE} " } if {[info exists PRELMODE]} { append pargs "+PRELMODE=${PRELMODE} " } if {[info exists BINARY]} { append pargs "+BINARY=${BINARY} " } +if {[info exists BINARY2]} { append pargs "+BINARY2=${BINARY2} " } +if {[info exists BINARY3]} { append pargs "+BINARY3=${BINARY3} " } if {[info exists IMAGE]} { append pargs "+IMAGE=${IMAGE} " } - -set questa-cmd "+PRELOAD=/scratch/zexifu/c910_sw/cheshire_2/sw/deps/cva6-sdk/install64/opensbi_alone.elf \ +# +PRELOAD=/scratch/zexifu/c910_sw/cheshire_3/sw/deps/cva6-sdk/install64/spike_fw_payload.elf +# +PRELOAD=/scratch/zexifu/c910_pulp/merge_with_cyril/cheshire_with_c910/hw/riscv-tests/isa/rv64ua-p-amoor_d_aqrl +set questa-cmd "+PRELOAD=/scratch/zexifu/c910_sw/cheshire_3/sw/deps/cva6-sdk/install64/spike_fw_payload.elf \ -gblso ../src/riscv-isa-sim/install/lib/libriscv.so \ -gblso /usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0/lib/libfesvr.so \ -sv_lib ../../../work-dpi/ariane_dpi"