From 166b0355e299fc292d6f4fbe10035d04b7219130 Mon Sep 17 00:00:00 2001 From: Diyou Shen Date: Mon, 18 Sep 2023 17:17:34 +0200 Subject: [PATCH] Tagger adjustments: 1. Adjust user Maxpartition and user bits of tagger to be consistent with LLC. 2. Adjust bootrom tagger part correspondingly. 3. Add register compilation in `cheshire.mk` for tagger. 4. Fix a problem of wrong place of tagger module. --- Bender.lock | 2 +- Bender.yml | 2 +- cheshire.mk | 7 +++++++ hw/bootrom/cheshire_bootrom.S | 8 ++++---- hw/bootrom/cheshire_bootrom.sv | 6 +++--- hw/cheshire_pkg.sv | 2 +- hw/cheshire_soc.sv | 19 ++++++++----------- 7 files changed, 25 insertions(+), 21 deletions(-) diff --git a/Bender.lock b/Bender.lock index 7cbcd2b7..5d65202a 100644 --- a/Bender.lock +++ b/Bender.lock @@ -180,7 +180,7 @@ packages: - common_cells - register_interface tagger: - revision: 8df2d026e0ad435ea2761dd2f172771c30520e93 + revision: 044d92c17728e7c608cd6678d01ec2d749c7ab83 version: null source: Git: git@iis-git.ee.ethz.ch:dishen/tagger.git diff --git a/Bender.yml b/Bender.yml index 4ee47324..e5a96ea0 100644 --- a/Bender.yml +++ b/Bender.yml @@ -30,7 +30,7 @@ dependencies: clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 } irq_router: { git: "https://github.com/pulp-platform/irq_router.git", rev: d1d3135 } # TODO: master commit; use next release once out bus_err_unit: { git: "git@iis-git.ee.ethz.ch:carfield/bus_err_unit.git", rev: "47a6436" } # branch: main - tagger: { git: "git@iis-git.ee.ethz.ch:dishen/tagger.git", rev: 8df2d02 } + tagger: { git: "git@iis-git.ee.ethz.ch:dishen/tagger.git", rev: 044d92c } export_include_dirs: - hw/include diff --git a/cheshire.mk b/cheshire.mk index 8eb8993c..17c6fcc5 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -20,6 +20,7 @@ CHS_ROOT ?= $(shell $(BENDER) path cheshire) CHS_REG_DIR := $(shell $(BENDER) path register_interface) CHS_SLINK_DIR := $(shell $(BENDER) path serial_link) CHS_LLC_DIR := $(shell $(BENDER) path axi_llc) +CHS_TAGGER_DIR := $(shell $(BENDER) path tagger) # Define paths used in dependencies OTPROOT := $(shell $(BENDER) path opentitan_peripherals) @@ -111,6 +112,11 @@ $(CHS_LLC_DIR)/.generated: $(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs @touch $@ +# Tagger configuration +$(CHS_TAGGER_DIR)/.generated: + $(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs + @touch $@ + CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv CHS_HW_ALL += $(CLINTROOT)/.generated CHS_HW_ALL += $(OTPROOT)/.generated @@ -118,6 +124,7 @@ CHS_HW_ALL += $(AXIRTROOT)/.generated CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated CHS_HW_ALL += $(CHS_LLC_DIR)/.generated +CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated ##################### # Generate Boot ROM # diff --git a/hw/bootrom/cheshire_bootrom.S b/hw/bootrom/cheshire_bootrom.S index 2dd432c6..a3b13397 100644 --- a/hw/bootrom/cheshire_bootrom.S +++ b/hw/bootrom/cheshire_bootrom.S @@ -80,13 +80,13 @@ _wait_llc_bist: lui t1, 0xFFFFF // 0xFFFF_F000 sw t1, 4(t0) - // set patid to 2 - li t1, 2 - sw t1, 36(t0) + // set patid to 0 + li t1, 0 + sw t1, 68(t0) // 0x44 // set mode to TOR li t1, 0x1 - sw t1, 40(t0) + sw t1, 80(t0) // 0x50 // commit changes li t1, 0x1 diff --git a/hw/bootrom/cheshire_bootrom.sv b/hw/bootrom/cheshire_bootrom.sv index 4b1520c2..e4ad5a43 100644 --- a/hw/bootrom/cheshire_bootrom.sv +++ b/hw/bootrom/cheshire_bootrom.sv @@ -63,9 +63,9 @@ module cheshire_bootrom #( 031: data_o = 32'h6325fe03 /* 0x007c */; 032: data_o = 32'h737d929a /* 0x0080 */; 033: data_o = 32'h0062a223 /* 0x0084 */; - 034: data_o = 32'ha2234309 /* 0x0088 */; - 035: data_o = 32'h43050262 /* 0x008c */; - 036: data_o = 32'h0262a423 /* 0x0090 */; + 034: data_o = 32'ha2234301 /* 0x0088 */; + 035: data_o = 32'h43050462 /* 0x008c */; + 036: data_o = 32'h0462a823 /* 0x0090 */; 037: data_o = 32'ha0234305 /* 0x0094 */; 038: data_o = 32'h12970062 /* 0x0098 */; 039: data_o = 32'h82930100 /* 0x009c */; diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index b0862455..776a40a3 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -494,7 +494,7 @@ package cheshire_pkg; // Interconnect AddrWidth : 48, AxiDataWidth : 64, - AxiUserWidth : 10, // Convention: bit 0 for core(s), bit 1 for serial link TODO: add more bits for llc + AxiUserWidth : 8, // Convention: bit 0 for core(s), bit 1 for serial link TODO: add more bits for llc AxiMstIdWidth : 2, AxiMaxMstTrans : 8, AxiMaxSlvTrans : 8, diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index a3390397..3d0af4d8 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -788,17 +788,15 @@ module cheshire_soc import cheshire_pkg::*; #( // .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), // .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] ) ); - end - generate if (Cfg.LlcCachePartition) begin : gen_tagger tagger #( .DATA_WIDTH ( Cfg.AxiDataWidth ), .ADDR_WIDTH ( Cfg.AddrWidth ), - .MAXPARTITION ( 8 ), - .AXI_USER_ID_MSB ( 5 ), - .AXI_USER_ID_LSB ( 2 ), + .MAXPARTITION ( Cfg.LlcMaxPartition ), + .AXI_USER_ID_MSB ( Cfg.LlcUserAmoMsb ), + .AXI_USER_ID_LSB ( Cfg.LlcUserAmoLsb ), .TAGGER_GRAN ( 3 ), .axi_req_t ( axi_mst_req_t ), .axi_rsp_t ( axi_mst_rsp_t ), @@ -809,17 +807,16 @@ module cheshire_soc import cheshire_pkg::*; #( .rst_ni, .slv_req_i ( tagger_req ), .slv_rsp_o ( tagger_rsp ), - .mst_req_o ( axi_in_req[AxiIn.cores] ), - .mst_rsp_i ( axi_in_rsp[AxiIn.cores] ), + .mst_req_o ( axi_in_req[AxiIn.cores[i]] ), + .mst_rsp_i ( axi_in_rsp[AxiIn.cores[i]] ), .cfg_req_i ( reg_out_req[RegOut.tagger] ), .cfg_rsp_o ( reg_out_rsp[RegOut.tagger] ) ); end else begin - assign axi_in_req[AxiIn.cores] = tagger_req; - assign tagger_rsp = axi_in_rsp[AxiIn.cores]; + assign axi_in_req[AxiIn.cores[i]] = tagger_req; + assign tagger_rsp = axi_in_rsp[AxiIn.cores[i]]; end - - endgenerate + end ///////////////////////// // JTAG Debug Module //