diff --git a/.gitignore b/.gitignore
index db20a918..69693199 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,6 +38,17 @@ target/sim/vsim/transcript
 target/sim/vsim/vsim.wlf
 target/sim/vsim/work/
 
+# VCS generated files
+target/sim/vcs/compile.*.sh
+target/sim/vcs/*.log
+target/sim/vcs/AN.DB
+target/sim/vcs/simv*
+target/sim/vcs/csrc
+target/sim/vcs/ucli.key
+target/sim/vcs/work*
+target/sim/vcs/vc_hdrs.h
+
+
 # Xilinx generated files
 target/xilinx/build
 target/xilinx/out
diff --git a/Bender.lock b/Bender.lock
index 2cc73bbf..94673bfb 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -15,7 +15,7 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 68795181b410406a54247075430f622e22220da3
+    revision: d864a8ac8237675e946e5aef22e6105eebcac6ed
     version: null
     source:
       Git: https://github.com/pulp-platform/axi.git
diff --git a/Bender.yml b/Bender.yml
index 35172e4c..935a7168 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -13,7 +13,7 @@ package:
 
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
-  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    rev: 68795181b410406a54247075430f622e22220da3 } # branch: ck/vcs
+  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    rev: d864a8ac8237675e946e5aef22e6105eebcac6ed } # branch: ck/vcs
   axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.2  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.7 }
diff --git a/cheshire.mk b/cheshire.mk
index 72001610..09e1d549 100644
--- a/cheshire.mk
+++ b/cheshire.mk
@@ -14,7 +14,7 @@ VLOGAN_BIN ?= vlogan
 CXX_PATH := $(shell which $(CXX))
 
 VLOG_ARGS   ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps
-VLOGAN_ARGS ?= -kdb -assert svaext +v2k -timescale=1ns/1ps
+VLOGAN_ARGS ?= -kdb -nc -assert svaext +v2k -timescale=1ns/1ps
 
 # Define used paths (prefixed to avoid name conflicts)
 CHS_ROOT      ?= $(shell $(BENDER) path cheshire)
@@ -61,7 +61,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= f731b17
+CHS_NONFREE_COMMIT ?= d446ed8
 
 CHS_PHONY += chs-nonfree-init
 chs-nonfree-init:
@@ -167,6 +167,7 @@ $(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/t
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
+CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh
 
 ###########
 # DRAMSys #
diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
index 41ca4b44..35948f7e 100644
--- a/target/sim/src/vip_cheshire_soc.sv
+++ b/target/sim/src/vip_cheshire_soc.sv
@@ -228,7 +228,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   assign jtag.tdo     = jtag_tdo;
 
   initial begin
-    wait_for_reset();
+    wait (!rst_n);
     jtag_dbg.reset_master();
   end
 
@@ -790,7 +790,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   slink_axi_driver_t slink_axi_driver = new (slink_mst_vip_dv);
 
   initial begin
-    wait_for_reset();
+    wait (!rst_n);
     slink_axi_driver.reset_master();
   end
 
diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh
index 6ce37229..930a6e10 100755
--- a/target/sim/vcs/start.cheshire_soc.sh
+++ b/target/sim/vcs/start.cheshire_soc.sh
@@ -18,16 +18,15 @@ fi
 [[ -z "${VERDI_VERSION}" ]] && VERDI_VERSION=""
 [[ -z "${VCS_VERSION}" ]]   && VCS_VERSION=""
 [[ -z "${VCS_BIN}" ]]       && VCS_BIN="${VCS_VERSION} vcs"
-[[ -z "${VERDI_HOME}" ]]    && echo "Please set \$VERDI_HOME" && exit 1
-[[ -z "${VCS_HOME}" ]]      && echo "Please set \$VCS_HOME"   && exit 1
 
 flags="-full64 -kdb "
 # Set default to fast simulation flags.
 if [ -z "${VCSARGS}" ]; then
-    flags+="-O2 -debug_access+all "
+    # Use -debug_access+all for waveform debugging
+    flags+="-O2 -debug_access=r -debug_region=1,${TESTBENCH} "
 fi
 
-# flags+="-cpp ${CXX_PATH} "
+flags+="-cpp ${CXX_PATH} "
 [[ -n "${SELCFG}" ]]   && flags+="-pvalue+SelectedCfg=${SELCFG} "
 
 pargs=""
@@ -42,13 +41,16 @@ if [ -n "${USE_DRAMSYS}" ]; then
     if [[ "${USE_DRAMSYS}" == 1 ]]; then
         DRAMSYS_ROOT="../dramsys"
         DRAMSYS_LIB="${DRAMSYS_ROOT}/build/lib"
-        flags+="-y ${DRAMSYS_LIB}/libsystemc "
-        flags+="-y ${DRAMSYS_LIB}/libDRAMSys_Simulator "
         pargs+="+DRAMSYS_RES=${DRAMSYS_ROOT}/configs "
+        pargs+=" -sv_lib ${DRAMSYS_LIB}/libDRAMSys_Simulator"
     fi
 fi
 
-${VERDI_VERSION} ${VCS_BIN} ${flags} ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log
+COLOR_NC='\e[0m'
+COLOR_BLUE='\e[0;34m'
 
-echo "${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"
-${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}
+${VCS_BIN} ${flags} ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log
+
+# Start simulation
+printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n"
+${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs} | tee simulate.log