diff --git a/Bender.yml b/Bender.yml index 293ece73..17957858 100644 --- a/Bender.yml +++ b/Bender.yml @@ -47,7 +47,7 @@ sources: - target/sim/src/fixture_cheshire_soc.sv - target/sim/src/tb_cheshire_soc.sv - - target: all(fpga, xilinx) + - target: any(fpga, xilinx) files: - target/xilinx/src/fan_ctrl.sv - target/xilinx/src/dram_wrapper.sv diff --git a/cheshire.mk b/cheshire.mk index acbde4b7..0cafc948 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -55,7 +55,7 @@ chs-clean-deps: ###################### CHS_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/cheshire-nonfree.git -CHS_NONFREE_COMMIT ?= e702b4ce754c3b7c9a864a2ce8e2d2fa013056ea +CHS_NONFREE_COMMIT ?= b11f9e5fbc97209da75e77c93a1e4e0460dddf6c chs-nonfree-init: git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree @@ -158,3 +158,4 @@ chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl ############# include $(CHS_ROOT)/target/xilinx/xilinx.mk +include $(CHS_XIL_DIR)/sim/simulate.mk diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc index 1eeda34e..b53845ee 100644 --- a/target/xilinx/constraints/cheshire.xdc +++ b/target/xilinx/constraints/cheshire.xdc @@ -13,21 +13,12 @@ set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux] # The net of which we get the 200 MHz single ended clock from the MIG -set MIG_CLK_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_clock_out]] -set MIG_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_sync_reset]] - set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]] ##################### # Timing Parameters # ##################### -# 333 MHz (max) DRAM Axi clock -set FPGA_TCK 3.0 - -# 200 MHz DRAM Generated clock -set DRAM_TCK 5.0 - # 50 MHz SoC clock set SOC_TCK 20.0 @@ -44,25 +35,40 @@ set UART_IO_SPEED 200.0 # Clocks # ########## +# Clk_wiz clocks +create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10] +create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20] +create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50] +create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100] + # System Clock -create_generated_clock -name clk_soc -source $MIG_CLK_SRC -divide_by 4 [get_nets soc_clk] +# [see in board.xdc] + # JTAG Clock create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i] set_input_jitter clk_jtag 1.000 +########## +# BUFG # +########## + +# JTAG are on non clock capable GPIOs (if not using BSCANE) +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]] +set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]] + +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + ################ # Clock Groups # ################ # JTAG Clock is asynchronous to all other clocks -set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag] - -####################### -# Placement Overrides # -####################### - -# Accept suboptimal BUFG-BUFG cascades -set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i] +set_clock_groups -name jtag_async -asynchronous -group {clk_jtag} ######## # JTAG # @@ -77,13 +83,6 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td set_max_delay -from [get_ports jtag_trst_ni] $JTAG_TCK set_false_path -hold -from [get_ports jtag_trst_ni] -####### -# MIG # -####### - -set_max_delay -from $MIG_RST_SRC $FPGA_TCK -set_false_path -hold -from $MIG_RST_SRC - ######## # UART # ######## @@ -101,15 +100,6 @@ set_false_path -hold -to [get_ports uart_tx_o] # cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew set_property KEEP_HIERARCHY SOFT [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync] set_false_path -hold -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK -set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK - -################### -# Reset Generator # -################### - -set_max_delay -from $SOC_RST_SRC $SOC_TCK -set_false_path -hold -from $SOC_RST_SRC -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_xlnx_clk_wiz/inst/clkin1_ibufds/O] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}] +set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}] diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc index df3b7b1f..8387ec19 100644 --- a/target/xilinx/constraints/genesys2.xdc +++ b/target/xilinx/constraints/genesys2.xdc @@ -5,6 +5,29 @@ # Testmode is set to 0 during normal use set_case_analysis 0 [get_ports testmode_i] + +set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]] +set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux +set_property CLOCK_BUFFER_TYPE NONE $all_in_mux + +############# +# Sys clock # +############# + +create_clock -period 5 -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + + +############# +# Mig clock # +############# + +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period 5 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST 5 + ####### # VGA # ####### @@ -54,8 +77,8 @@ set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}] ############### ## Clock Signal -# set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n -# set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p +set_property -dict { PACKAGE_PIN AD11 IOSTANDARD LVDS } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n +set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p ## Buttons #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc index ce24bce9..6458d0cb 100644 --- a/target/xilinx/constraints/vcu128.xdc +++ b/target/xilinx/constraints/vcu128.xdc @@ -2,9 +2,27 @@ # BOARD SPECIFIC CONSTRAINTS # ############################## -# JTAG are on non clock capable GPIOs (if not using BSCANE) -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]] -set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]] +############# +# Sys clock # +############# + +create_clock -period 10 -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +#create_clock -period 10 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST 10 + +set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK +set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK + + ################################################################################# diff --git a/target/xilinx/constraints/zcu102.xdc b/target/xilinx/constraints/zcu102.xdc index 1a2a1562..955d7720 100644 --- a/target/xilinx/constraints/zcu102.xdc +++ b/target/xilinx/constraints/zcu102.xdc @@ -1,3 +1,31 @@ +############################## +# BOARD SPECIFIC CONSTRAINTS # +############################## + +############# +# Sys clock # +############# + +create_clock -period 3.333 -name sys_clk [get_pins u_ibufg_sys_clk/O] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O] +set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk} + +############# +# Mig clock # +############# + +set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] +create_clock -period 3.333 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk] +set_false_path -hold -through $MIG_RST +set_max_delay -through $MIG_RST 3.333 + + +################################################################################# + +############### +# ASSIGN PINS # +############### + ################################################# ### ZCU102 Rev1.0 Master XDC file 09-15-2016 #### ################################################# @@ -155,8 +183,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC #set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 #set_property PACKAGE_PIN H18 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 #set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 -set_property PACKAGE_PIN A20 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property PACKAGE_PIN A20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 set_property PACKAGE_PIN B20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 set_property PACKAGE_PIN A22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 @@ -183,10 +211,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VC #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 #set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 -#set_property PACKAGE_PIN F21 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_N"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -#set_property PACKAGE_PIN G21 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -#set_property IOSTANDARD LVDS_25 [get_ports "CLK_125_P"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 +#set_property PACKAGE_PIN F21 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -> CLK_125_N +#set_property IOSTANDARD LVDS_25 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 -> CLK_125_N +#set_property PACKAGE_PIN G21 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -> CLK_125_P +#set_property IOSTANDARD LVDS_25 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 -> CLK_125_P #set_property PACKAGE_PIN J20 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L4N_AD8N_47 #set_property PACKAGE_PIN J19 [get_ports "PMOD1_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L4P_AD8P_47 @@ -618,11 +646,11 @@ set_property IOSTANDARD LVCMOS33 [get_ports "cpu_reset"] ;# Bank 44 VCCO - VCC #set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_64 #set_property PACKAGE_PIN AL6 [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 #set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"] ;# Bank 64 VCCO - VCC1V2 - IO_L13P_T2L_N0_GC_QBC_64 -#set_property PACKAGE_PIN AL7 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 -#set_property PACKAGE_PIN AL8 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 -#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 +set_property PACKAGE_PIN AL7 [get_ports "sys_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 => USER_SI570_N +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 => USER_SI570_N +set_property PACKAGE_PIN AL8 [get_ports "sys_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 => USER_SI570_P +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 => USER_SI570_P +#set_property PACKAGE_PIN AK7 [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 #set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"] ;# Bank 64 VCCO - VCC1V2 - IO_L11N_T1U_N9_GC_64 #set_property PACKAGE_PIN AK8 [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 #set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"] ;# Bank 64 VCCO - VCC1V2 - IO_L11P_T1U_N8_GC_64 diff --git a/target/xilinx/scripts/flash.tcl b/target/xilinx/scripts/flash.tcl new file mode 100644 index 00000000..f8c5113f --- /dev/null +++ b/target/xilinx/scripts/flash.tcl @@ -0,0 +1,50 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Nils Wistoff +# Noah Huetter +# + +set mcs_file flash_img.mcs +set file $::env(FILE) +set offset $::env(OFFSET) + +# Create flash configuration file +write_cfgmem -force -format mcs -size 256 -interface SPIx4 \ + -loaddata "up $offset $file" \ + -checksum \ + -file $mcs_file + +# Open and connect HW manager +open_hw_manager +connect_hw_server -url $::env(HOST):$::env(PORT) -allow_non_jtag +current_hw_target [get_hw_targets $::env(HOST):$::env(PORT)/$::env(FPGA_PATH)] +set_property PARAM.FREQUENCY 15000000 [get_hw_targets $::env(HOST):$::env(PORT)/$::env(FPGA_PATH)] +open_hw_target +current_hw_device [get_hw_devices xcvu37p_0] + +# Add the SPI flash as configuration memory +set hw_device [get_hw_devices xcvu37p_0] +create_hw_cfgmem -hw_device $hw_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0] +set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device] +set_property PROGRAM.ADDRESS_RANGE {use_file} $hw_cfgmem +set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem +set_property PROGRAM.PRM_FILE {} $hw_cfgmem +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem +set_property PROGRAM.BLANK_CHECK 0 $hw_cfgmem +set_property PROGRAM.ERASE 0 $hw_cfgmem +set_property PROGRAM.CFG_PROGRAM 1 $hw_cfgmem +set_property PROGRAM.VERIFY 0 $hw_cfgmem +set_property PROGRAM.CHECKSUM 0 $hw_cfgmem + +# Create bitstream to access SPI flash +create_hw_bitstream -hw_device $hw_device [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_device]; +program_hw_devices $hw_device; +refresh_hw_device $hw_device; + +# Program SPI flash +program_hw_cfgmem -hw_cfgmem $hw_cfgmem + +# Close connection +close_hw_manager \ No newline at end of file diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl index b274a61f..db064783 100644 --- a/target/xilinx/scripts/run.tcl +++ b/target/xilinx/scripts/run.tcl @@ -16,27 +16,7 @@ switch $::env(BOARD) { } # Ips selection -switch $::env(BOARD) { - "genesys2" - "kc705" - "vc707" { - set ips { "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \ - "xilinx/xlnx_vio/xlnx_vio.srcs/sources_1/ip/xlnx_vio/xlnx_vio.xci" \ - "xilinx/xlnx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci"} - } - "vcu128" { - set ips { "xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \ - "xilinx/xlnx_vio/xlnx_vio.srcs/sources_1/ip/xlnx_vio/xlnx_vio.xci" \ - "xilinx/xlnx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci"} - } - "zcu102" { - set ips { "xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \ - "xilinx/xlnx_vio/xlnx_vio.srcs/sources_1/ip/xlnx_vio/xlnx_vio.xci" \ - "xilinx/xlnx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci"} - } - default { - set ips {} - } -} - +set ips $::env(IP_PATHS) read_ip $ips source scripts/add_sources.tcl @@ -72,6 +52,7 @@ report_clock_interaction -file re # Instantiate ILA set DEBUG [llength [get_nets -hier -filter {MARK_DEBUG == 1}]] if ($DEBUG) { + remove_cell [get_cells -hier -filter {ORIG_REF_NAME == "unread" || REF_NAME == "unread"}] # Create core puts "Creating debug core..." create_debug_core u_ila_0 ila @@ -120,11 +101,12 @@ launch_runs impl_1 -to_step write_bitstream wait_on_run impl_1 # Check timing constraints -open_run impl_1 set timingrep [report_timing_summary -no_header -no_detailed_paths -return_string] -if {! [string match -nocase {*timing constraints are met*} $timingrep]} { - send_msg_id {USER 1-1} ERROR {Timing constraints were not met.} - return -code error +if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} { + if {! [string match -nocase {*timing constraints are met*} $timingrep]} { + send_msg_id {USER 1-1} ERROR {Timing constraints were not met.} + return -code error + } } # Output Verilog netlist + SDC for timing simulation diff --git a/target/xilinx/sim/run_simulation.tcl b/target/xilinx/sim/run_simulation.tcl index d73f4119..b0260460 100644 --- a/target/xilinx/sim/run_simulation.tcl +++ b/target/xilinx/sim/run_simulation.tcl @@ -4,16 +4,26 @@ # # Cyril Koenig -#source ips/xlnx_mig_7_ddr3_ex/questa/compile.do -#source ips/xlnx_mig_7_ddr3/questa/compile.do -source ips/xlnx_mig_ddr4_ex/questa/compile.do -source ips/xlnx_mig_ddr4/questa/compile.do source ../scripts/add_sources_vsim.tcl +if {[string first "xlnx_clk_wiz" $::env(IPS)] != -1} { + source ips/xlnx_clk_wiz/questa/compile.do -vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv" -#vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v" +if {[string first "xlnx_vio" $::env(IPS)] != -1} { + source ips/xlnx_vio/questa/compile.do +}} +if {[string first "xlnx_mig_7_ddr3" $::env(IPS)] != -1} { + source ips/xlnx_mig_7_ddr3_ex/questa/compile.do + source ips/xlnx_mig_7_ddr3/questa/compile.do + vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_7_ddr3_ex/questa/srcs/sim_tb_top.v" +} + +if {[string first "xlnx_mig_ddr4" $::env(IPS)] != -1} { + source ips/xlnx_mig_ddr4_ex/questa/compile.do + source ips/xlnx_mig_ddr4/questa/compile.do + vlog -work work -L xil_defaultlib -64 -incr -sv "./ips/xlnx_mig_ddr4_ex/questa/srcs/sim_tb_top.sv" +} # Note : this testbench does not implenent the ddr4 memory model set TESTBENCH "work.sim_tb_top xil_defaultlib.glbl" diff --git a/target/xilinx/sim/simulate.mk b/target/xilinx/sim/simulate.mk index 4230d058..1005fe30 100644 --- a/target/xilinx/sim/simulate.mk +++ b/target/xilinx/sim/simulate.mk @@ -4,21 +4,23 @@ # # Cyril Koenig +CHS_XIL_SIM_DIR ?= $(CHS_XIL_DIR)/sim + XILINX_SIMLIB_PATH ?= ~/xlib_questa-2022.3_vivado-2022.1 SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin -ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ips-names))) +ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names))) # Pre-generated/modified example projects (contain the simulation top level) -ifeq ($(BOARD),vcu128) +ifneq ($(filter xlnx_mig_ddr4,$(ips-names)),) ip-example-projects := xlnx_mig_ddr4_ex endif -ifeq ($(BOARD),genesys2) +ifneq ($(filter xlnx_mig_7_ddr3,$(ips-names)),) ip-example-projects := xlnx_mig_7_ddr3_ex endif -ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ip-example-projects))) +ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects))) VIVADOENV_SIM := $(VIVADOENV) \ XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \ @@ -28,27 +30,29 @@ VIVADOENV_SIM := $(VIVADOENV) \ VLOG_ARGS := -suppress 2583 -suppress 13314 # Fetch example projects at IIS (containing SRAM behavioral models) -sim/ips/%_ex/questa/compile.do: - tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C sim/ips +$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips # Generate simulation libraries $(XILINX_SIMLIB_PATH)/modelsim.ini: - cd sim && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib" # -sim/ips/%/questa/compile.do: - cd sim && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" +$(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do: + mkdir -p $(CHS_XIL_SIM_DIR)/ips + cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation" -scripts/add_sources_vsim.tcl: - $(BENDER) script vsim -t sim -t test -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 $(bender-targets) --vlog-arg="$(VLOG_ARGS)" > $@ +$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl: + $(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@ -sim: ${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) scripts/add_sources_vsim.tcl - mkdir -p sim/questa_lib - cp $(XILINX_SIMLIB_PATH)/modelsim.ini sim - chmod +w sim/modelsim.ini - cd sim && questa-2022.3 vsim -work work -do "run_simulation.tcl" +chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl + mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib + cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR) + chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini + cd $(CHS_XIL_SIM_DIR) && IPS="$(ips-names)" questa-2022.3 vsim -work work -do "run_simulation.tcl" -clean-sim: - rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini +chs-xil-clean-sim: + cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini .PHONY: clean-sim sim diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv index c6acf86e..574eb61a 100644 --- a/target/xilinx/src/cheshire_top_xilinx.sv +++ b/target/xilinx/src/cheshire_top_xilinx.sv @@ -203,6 +203,28 @@ module cheshire_top_xilinx (* dont_touch = "yes" *) wire soc_clk; (* dont_touch = "yes" *) wire rst_n; + /////////////////// + // GPIOs // + /////////////////// + + // Tie off signals if no switches on the board +`ifndef USE_SWITCHES + logic testmode_i; + logic [1:0] boot_mode_i; + assign testmode_i = '0; + assign boot_mode_i = 2'b00; +`endif + + // Give VDD and GND to JTAG dongle +`ifdef USE_JTAG_VDDGND + assign jtag_vdd_o = '1; + assign jtag_gnd_o = '0; +`endif +`ifndef USE_JTAG_TRSTN + logic jtag_trst_ni; + assign jtag_trst_ni = '1; +`endif + ////////////////// // Clock Wizard // ////////////////// @@ -239,7 +261,7 @@ module cheshire_top_xilinx rstgen i_rstgen_main ( .clk_i ( soc_clk ), .rst_ni ( ~sys_rst ), - .test_mode_i ( test_mode_i ), + .test_mode_i ( testmode_i ), .rst_no ( rst_n ), .init_no ( ) // keep open ); @@ -249,38 +271,23 @@ module cheshire_top_xilinx /////////////////// logic vio_reset, vio_boot_mode_sel; - logic [1:0] vio_boot_mode; + logic [1:0] boot_mode, vio_boot_mode; +`ifdef USE_VIO xlnx_vio i_xlnx_vio ( .clk(soc_clk), .probe_out0(vio_reset), .probe_out1(vio_boot_mode), .probe_out2(vio_boot_mode_sel) ); - assign sys_rst = ~cpu_resetn | vio_reset; - assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; - - /////////////////// - // GPIOs // - /////////////////// - - // Tie off signals if no switches on the board -`ifndef USE_SWITCHES - logic testmode_i; - logic [1:0] boot_mode_i; - assign testmode_i = '0; - assign boot_mode_i = 2'b00; +`else + assign vio_reset = '0; + assign vio_boot_mode = '0; + assign vio_boot_mode_sel = '0; `endif - // Give VDD and GND to JTAG dongle -`ifdef USE_JTAG_VDDGND - assign jtag_vdd_o = '1; - assign jtag_gnd_o = '0; -`endif -`ifndef USE_JTAG_TRSTN - logic jtag_trst_ni; - assign jtag_trst_ni = '1; -`endif + assign sys_rst = ~cpu_resetn | vio_reset; + assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i; ////////////// // DRAM MIG // @@ -289,12 +296,12 @@ module cheshire_top_xilinx `ifdef USE_DDR dram_wrapper #( .axi_soc_aw_chan_t ( axi_llc_aw_chan_t ), - .axi_soc_w_chan_t ( axi_llc_w_chan_t ), - .axi_soc_b_chan_t ( axi_llc_b_chan_t ), + .axi_soc_w_chan_t ( axi_llc_w_chan_t ), + .axi_soc_b_chan_t ( axi_llc_b_chan_t ), .axi_soc_ar_chan_t ( axi_llc_ar_chan_t ), - .axi_soc_r_chan_t ( axi_llc_r_chan_t ), - .axi_soc_req_t (axi_llc_req_t), - .axi_soc_resp_t (axi_llc_rsp_t) + .axi_soc_r_chan_t ( axi_llc_r_chan_t ), + .axi_soc_req_t ( axi_llc_req_t ), + .axi_soc_resp_t ( axi_llc_rsp_t ) ) i_dram_wrapper ( // Rst .sys_rst_i ( sys_rst ), @@ -400,7 +407,7 @@ module cheshire_top_xilinx logic [3:0] qspi_dqo_ts; logic [3:0] qspi_dqo; logic [SpihNumCs-1:0] qspi_cs_b; -logic [SpihNumCs-1:0] qspi_cs_b_ts; + logic [SpihNumCs-1:0] qspi_cs_b_ts; assign qspi_clk = spi_sck_soc; assign qspi_cs_b = spi_cs_soc; @@ -472,7 +479,6 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts; end end - ///////////////// // Fan Control // ///////////////// @@ -503,7 +509,6 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts; .rsp_o ( ext_rsp ) ); - ////////////////// // Cheshire SoC // ////////////////// diff --git a/target/xilinx/src/dram_wrapper.sv b/target/xilinx/src/dram_wrapper.sv index d5cbc964..2c7fb4d3 100644 --- a/target/xilinx/src/dram_wrapper.sv +++ b/target/xilinx/src/dram_wrapper.sv @@ -32,8 +32,8 @@ module dram_wrapper #( `DDR3_INTF `endif // Dram axi interface - input axi_soc_req_t soc_req_i, - output axi_soc_resp_t soc_rsp_o + (* mark_debug = "true" *) input axi_soc_req_t soc_req_i, + (* mark_debug = "true" *) output axi_soc_resp_t soc_rsp_o ); //////////////////////////////////// @@ -51,22 +51,35 @@ module dram_wrapper #( integer StrobeWidth; } dram_cfg_t; -`ifdef USE_DDR4 +`ifdef TARGET_VCU128 localparam dram_cfg_t cfg = '{ EnSpill0 : 1, EnResizer : 1, EnCDC : 1, // 333 MHz axi EnSpill1 : 1, - IdWidth : 4, + IdWidth : 6, AddrWidth : 32, DataWidth : 512, StrobeWidth : 64 }; `endif -`ifdef USE_DDR3 +`ifdef TARGET_ZCU102 localparam dram_cfg_t cfg = '{ - EnSpill0 : 0, + EnSpill0 : 1, + EnResizer : 1, + EnCDC : 1, // ??? MHz axi + EnSpill1 : 1, + IdWidth : 6, + AddrWidth : 29, + DataWidth : 128, + StrobeWidth : 16 + }; +`endif + +`ifdef TARGET_GENESYS2 + localparam dram_cfg_t cfg = '{ + EnSpill0 : 1, EnResizer : 0, EnCDC : 1, // 200 MHz axi EnSpill1 : 1, @@ -90,8 +103,10 @@ module dram_wrapper #( axi_soc_resp_t soc_spill_rsp, spill_resizer_rsp; // Signals after resizing - axi_ddr_req_t resizer_cdc_req, cdc_spill_req, spill_dram_req; - axi_ddr_resp_t resizer_cdc_rsp, cdc_spill_rsp, spill_dram_rsp; + axi_ddr_req_t resizer_cdc_req, cdc_spill_req; + axi_ddr_req_t spill_dram_req; + axi_ddr_resp_t resizer_cdc_rsp, cdc_spill_rsp; + axi_ddr_resp_t spill_dram_rsp; // Entry signals assign soc_spill_req = soc_req_i; @@ -255,8 +270,8 @@ module dram_wrapper #( end else begin : gen_upsize_ids // Forward arid awid rid bid to and from DDR - assign spill_dram_req_arid = spill_dram_req.ar.id; - assign spill_dram_req_awid = spill_dram_req.aw.id; + assign spill_dram_req_arid = {{-IdPadding{1'b0}}, spill_dram_req.ar.id}; + assign spill_dram_req_awid = {{-IdPadding{1'b0}}, spill_dram_req.aw.id}; assign spill_dram_rsp.r.id = spill_dram_rsp_rid; assign spill_dram_rsp.b.id = spill_dram_rsp_bid; end @@ -423,4 +438,4 @@ module dram_wrapper #( ); `endif // USE_DDR3 -endmodule \ No newline at end of file +endmodule diff --git a/target/xilinx/src/phy_definitions.svh b/target/xilinx/src/phy_definitions.svh index 9e333bf7..adb3988c 100644 --- a/target/xilinx/src/phy_definitions.svh +++ b/target/xilinx/src/phy_definitions.svh @@ -8,12 +8,10 @@ `define USE_RESET `define USE_JTAG `define USE_JTAG_VDDGND - `define USE_VIO `define USE_DDR4 `define USE_QSPI `define USE_STARTUPE3 - // DRAM runs at 200MHz - `define DDR_CLK_DIVIDER 4'h4 + `define USE_VIO `endif `ifdef TARGET_GENESYS2 @@ -23,17 +21,17 @@ `define USE_SD `define USE_SWITCHES `define USE_DDR3 - // DRAM runs at 200MHz - `define DDR_CLK_DIVIDER 4'h4 `define USE_FAN + `define USE_VIO `endif `ifdef TARGET_ZCU102 `define USE_RESET `define USE_JTAG `define USE_DDR4 - // DRAM runs at 100MHz - `define DDR_CLK_DIVIDER 4'h2 + `define USE_QSPI + `define USE_STARTUPE3 + `define USE_VIO `endif ///////////////////// @@ -74,8 +72,8 @@ `endif `define DDR3_INTF \ - output ddr3_ck_p, - output ddr3_ck_n, + output ddr3_ck_p, \ + output ddr3_ck_n, \ inout [31:0] ddr3_dq, \ inout [3:0] ddr3_dqs_n, \ inout [3:0] ddr3_dqs_p, \ diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 92ebe550..bd048cf6 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -10,7 +10,7 @@ CHS_XIL_DIR ?= $(CHS_ROOT)/target/xilinx VIVADO ?= vitis-2020.2 vivado PROJECT ?= cheshire -BOARD ?= genesys2 +BOARD ?= vcu128 ip-dir := $(CHS_XIL_DIR)/xilinx # Select board specific variables @@ -54,7 +54,8 @@ VIVADOENV ?= PROJECT=$(PROJECT) \ PORT=$(XILINX_PORT) \ HOST=$(XILINX_HOST) \ FPGA_PATH=$(FPGA_PATH) \ - BIT=$(bit) + BIT=$(bit) \ + IP_PATHS="$(foreach ip-name,$(ips-names),xilinx/$(ip-name)/$(ip-name).srcs/sources_1/ip/$(ip-name)/$(ip-name).xci)" MODE ?= gui VIVADOFLAGS ?= -nojournal -mode $(MODE) @@ -69,7 +70,8 @@ $(mcs): $(bit) $(bit): $(ips) $(CHS_XIL_DIR)/scripts/add_sources.tcl @mkdir -p $(out) cd $(CHS_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/prologue.tcl -source scripts/run.tcl - cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/$(PROJECT)* $(out) + cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.bit $(out) + cp $(CHS_XIL_DIR)/$(PROJECT).runs/impl_1/*.ltx $(out) # Generate ips %.xci: @@ -96,6 +98,9 @@ chs-xil-rebuild-top: find $(CHS_XIL_DIR)/xilinx -wholename "**/*.srcs/**/*.xci" | xargs -n 1 -I {} cp {} $(CHS_XIL_DIR) ${MAKE} $(bit) +chs-xil-flash: $(CHS_SW_DIR)/boot/linux.gpt.bin + $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) FILE=$(CHS_SW_DIR)/boot/linux.gpt.bin OFFSET=0 -source $(CHS_XIL_DIR)/scripts/program.tcl + # Bender script $(CHS_XIL_DIR)/scripts/add_sources.tcl: Bender.yml $(BENDER) script vivado $(xilinx_targs) > $@ diff --git a/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl b/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl index 135e4553..44b269a1 100644 --- a/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl +++ b/target/xilinx/xilinx/xlnx_clk_wiz/tcl/run.tcl @@ -40,8 +40,10 @@ if {$::env(BOARD) eq "vcu128"} { CONFIG.CLKOUT4_PHASE_ERROR {87.180} \ ] [get_ips $ipName] } + if {$::env(BOARD) eq "zcu102"} { - set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {300.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ @@ -52,7 +54,6 @@ if {$::env(BOARD) eq "zcu102"} { CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ - CONFIG.PRIM_SOURCE {No_buffer} \ CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ @@ -71,8 +72,10 @@ if {$::env(BOARD) eq "zcu102"} { CONFIG.CLKOUT4_PHASE_ERROR {77.836} \ ] [get_ips $ipName] } + if {$::env(BOARD) eq "genesys2"} { - set_property -dict [list CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {200.000} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ @@ -80,10 +83,9 @@ if {$::env(BOARD) eq "genesys2"} { CONFIG.CLK_OUT2_PORT {clk_50} \ CONFIG.CLK_OUT3_PORT {clk_20} \ CONFIG.CLK_OUT4_PORT {clk_10} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ - CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10} \ - CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \ CONFIG.CLKIN1_JITTER_PS {50.0} \ CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ diff --git a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj index d4b7ff63..3dbebfc3 100755 --- a/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj +++ b/target/xilinx/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj @@ -22,7 +22,7 @@ 1250 2.0V 4:1 - 100 + 200 0 800 1.000 diff --git a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl index c7393959..aef051e4 100644 --- a/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl +++ b/target/xilinx/xilinx/xlnx_mig_ddr4/tcl/run.tcl @@ -19,6 +19,7 @@ if {$::env(BOARD) eq "vcu128"} { set_property -dict [list CONFIG.C0.DDR4_Clamshell {true} \ CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ CONFIG.C0.DDR4_InputClockPeriod {10000} \ CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \ CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ @@ -27,15 +28,15 @@ if {$::env(BOARD) eq "vcu128"} { CONFIG.C0.DDR4_Ecc {true} \ CONFIG.C0.DDR4_AxiDataWidth {512} \ CONFIG.C0.DDR4_AxiAddressWidth {32} \ + CONFIG.C0.DDR4_AxiIDWidth {6} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ CONFIG.C0.BANK_GROUP_WIDTH {1} \ CONFIG.C0.CS_WIDTH {2} \ CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $ipName] + } elseif {$::env(BOARD) eq "zcu102"} { - set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset} \ - CONFIG.C0_CLOCK_BOARD_INTERFACE {user_si570_sysclk} \ - CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ + set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \ CONFIG.C0.DDR4_TimePeriod {833} \ CONFIG.C0.DDR4_InputClockPeriod {3332} \ CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \ @@ -44,12 +45,16 @@ if {$::env(BOARD) eq "vcu128"} { CONFIG.C0.DDR4_CasWriteLatency {12} \ CONFIG.C0.DDR4_AxiDataWidth {128} \ CONFIG.C0.DDR4_AxiAddressWidth {29} \ + CONFIG.C0.DDR4_AxiIDWidth {6} \ CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.Reference_Clock {No_Buffer} \ CONFIG.C0.BANK_GROUP_WIDTH {1} \ CONFIG.C0.DDR4_AxiSelection {true} \ ] [get_ips $ipName] } + generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]