From 6844d4b62ae0b9c4bacc270b3247241d1fd12ff8 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 22 Jul 2023 19:06:03 +0200 Subject: [PATCH 01/10] hw/regs: Generate missing isolate and isolate status regs --- hw/regs/carfield_reg_pkg.sv | 294 +++++++++++------------ hw/regs/carfield_reg_top.sv | 455 +++++++++++++++++------------------- hw/regs/carfield_regs.csv | 7 +- hw/regs/carfield_regs.hjson | 43 ++-- sw/include/regs/soc_ctrl.h | 135 +++++------ 5 files changed, 440 insertions(+), 494 deletions(-) diff --git a/hw/regs/carfield_reg_pkg.sv b/hw/regs/carfield_reg_pkg.sv index 0d3476f4..c1f4cd72 100644 --- a/hw/regs/carfield_reg_pkg.sv +++ b/hw/regs/carfield_reg_pkg.sv @@ -13,10 +13,6 @@ package carfield_reg_pkg; // Typedefs for registers // //////////////////////////// - typedef struct packed { - logic [2:0] q; - } carfield_reg2hw_boot_mode_reg_t; - typedef struct packed { logic [31:0] q; } carfield_reg2hw_generic_scratch0_reg_t; @@ -53,10 +49,6 @@ package carfield_reg_pkg; logic q; } carfield_reg2hw_l2_rst_reg_t; - typedef struct packed { - logic q; - } carfield_reg2hw_host_isolate_reg_t; - typedef struct packed { logic q; } carfield_reg2hw_periph_isolate_reg_t; @@ -77,6 +69,10 @@ package carfield_reg_pkg; logic q; } carfield_reg2hw_spatz_cluster_isolate_reg_t; + typedef struct packed { + logic q; + } carfield_reg2hw_l2_isolate_reg_t; + typedef struct packed { logic q; } carfield_reg2hw_periph_clk_en_reg_t; @@ -227,11 +223,6 @@ package carfield_reg_pkg; logic [31:0] q; } carfield_reg2hw_l2_sram_config3_reg_t; - typedef struct packed { - logic [2:0] d; - logic de; - } carfield_hw2reg_boot_mode_reg_t; - typedef struct packed { logic [31:0] d; logic de; @@ -242,11 +233,6 @@ package carfield_reg_pkg; logic de; } carfield_hw2reg_generic_scratch1_reg_t; - typedef struct packed { - logic d; - logic de; - } carfield_hw2reg_host_isolate_status_reg_t; - typedef struct packed { logic d; logic de; @@ -272,6 +258,11 @@ package carfield_reg_pkg; logic de; } carfield_hw2reg_spatz_cluster_isolate_status_reg_t; + typedef struct packed { + logic d; + logic de; + } carfield_hw2reg_l2_isolate_status_reg_t; + typedef struct packed { logic d; logic de; @@ -289,7 +280,6 @@ package carfield_reg_pkg; // Register -> HW type typedef struct packed { - carfield_reg2hw_boot_mode_reg_t boot_mode; // [544:542] carfield_reg2hw_generic_scratch0_reg_t generic_scratch0; // [541:510] carfield_reg2hw_generic_scratch1_reg_t generic_scratch1; // [509:478] carfield_reg2hw_host_rst_reg_t host_rst; // [477:477] @@ -299,12 +289,12 @@ package carfield_reg_pkg; carfield_reg2hw_pulp_cluster_rst_reg_t pulp_cluster_rst; // [473:473] carfield_reg2hw_spatz_cluster_rst_reg_t spatz_cluster_rst; // [472:472] carfield_reg2hw_l2_rst_reg_t l2_rst; // [471:471] - carfield_reg2hw_host_isolate_reg_t host_isolate; // [470:470] - carfield_reg2hw_periph_isolate_reg_t periph_isolate; // [469:469] - carfield_reg2hw_safety_island_isolate_reg_t safety_island_isolate; // [468:468] - carfield_reg2hw_security_island_isolate_reg_t security_island_isolate; // [467:467] - carfield_reg2hw_pulp_cluster_isolate_reg_t pulp_cluster_isolate; // [466:466] - carfield_reg2hw_spatz_cluster_isolate_reg_t spatz_cluster_isolate; // [465:465] + carfield_reg2hw_periph_isolate_reg_t periph_isolate; // [470:470] + carfield_reg2hw_safety_island_isolate_reg_t safety_island_isolate; // [469:469] + carfield_reg2hw_security_island_isolate_reg_t security_island_isolate; // [468:468] + carfield_reg2hw_pulp_cluster_isolate_reg_t pulp_cluster_isolate; // [467:467] + carfield_reg2hw_spatz_cluster_isolate_reg_t spatz_cluster_isolate; // [466:466] + carfield_reg2hw_l2_isolate_reg_t l2_isolate; // [465:465] carfield_reg2hw_periph_clk_en_reg_t periph_clk_en; // [464:464] carfield_reg2hw_safety_island_clk_en_reg_t safety_island_clk_en; // [463:463] carfield_reg2hw_security_island_clk_en_reg_t security_island_clk_en; // [462:462] @@ -345,15 +335,14 @@ package carfield_reg_pkg; // HW -> register type typedef struct packed { - carfield_hw2reg_boot_mode_reg_t boot_mode; // [87:84] carfield_hw2reg_generic_scratch0_reg_t generic_scratch0; // [83:51] carfield_hw2reg_generic_scratch1_reg_t generic_scratch1; // [50:18] - carfield_hw2reg_host_isolate_status_reg_t host_isolate_status; // [17:16] - carfield_hw2reg_periph_isolate_status_reg_t periph_isolate_status; // [15:14] - carfield_hw2reg_safety_island_isolate_status_reg_t safety_island_isolate_status; // [13:12] - carfield_hw2reg_security_island_isolate_status_reg_t security_island_isolate_status; // [11:10] - carfield_hw2reg_pulp_cluster_isolate_status_reg_t pulp_cluster_isolate_status; // [9:8] - carfield_hw2reg_spatz_cluster_isolate_status_reg_t spatz_cluster_isolate_status; // [7:6] + carfield_hw2reg_periph_isolate_status_reg_t periph_isolate_status; // [17:16] + carfield_hw2reg_safety_island_isolate_status_reg_t safety_island_isolate_status; // [15:14] + carfield_hw2reg_security_island_isolate_status_reg_t security_island_isolate_status; // [13:12] + carfield_hw2reg_pulp_cluster_isolate_status_reg_t pulp_cluster_isolate_status; // [11:10] + carfield_hw2reg_spatz_cluster_isolate_status_reg_t spatz_cluster_isolate_status; // [9:8] + carfield_hw2reg_l2_isolate_status_reg_t l2_isolate_status; // [7:6] carfield_hw2reg_spatz_cluster_busy_reg_t spatz_cluster_busy; // [5:4] carfield_hw2reg_pulp_cluster_busy_reg_t pulp_cluster_busy; // [3:2] carfield_hw2reg_pulp_cluster_eoc_reg_t pulp_cluster_eoc; // [1:0] @@ -365,65 +354,64 @@ package carfield_reg_pkg; parameter logic [BlockAw-1:0] CARFIELD_VERSION2_OFFSET = 8'h 8; parameter logic [BlockAw-1:0] CARFIELD_VERSION3_OFFSET = 8'h c; parameter logic [BlockAw-1:0] CARFIELD_VERSION4_OFFSET = 8'h 10; - parameter logic [BlockAw-1:0] CARFIELD_BOOT_MODE_OFFSET = 8'h 14; - parameter logic [BlockAw-1:0] CARFIELD_JEDEC_IDCODE_OFFSET = 8'h 18; - parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH0_OFFSET = 8'h 1c; - parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH1_OFFSET = 8'h 20; - parameter logic [BlockAw-1:0] CARFIELD_HOST_RST_OFFSET = 8'h 24; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_RST_OFFSET = 8'h 28; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_RST_OFFSET = 8'h 2c; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_RST_OFFSET = 8'h 30; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_RST_OFFSET = 8'h 34; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_RST_OFFSET = 8'h 38; - parameter logic [BlockAw-1:0] CARFIELD_L2_RST_OFFSET = 8'h 3c; - parameter logic [BlockAw-1:0] CARFIELD_HOST_ISOLATE_OFFSET = 8'h 40; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_OFFSET = 8'h 44; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET = 8'h 48; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET = 8'h 4c; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET = 8'h 50; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET = 8'h 54; - parameter logic [BlockAw-1:0] CARFIELD_HOST_ISOLATE_STATUS_OFFSET = 8'h 58; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET = 8'h 5c; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 60; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 64; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 68; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 6c; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_EN_OFFSET = 8'h 70; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET = 8'h 74; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET = 8'h 78; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET = 8'h 7c; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET = 8'h 80; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_EN_OFFSET = 8'h 84; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_SEL_OFFSET = 8'h 88; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET = 8'h 8c; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET = 8'h 90; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET = 8'h 94; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET = 8'h 98; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_SEL_OFFSET = 8'h 9c; - parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET = 8'h a0; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a4; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a8; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h ac; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h b0; - parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_DIV_VALUE_OFFSET = 8'h b4; - parameter logic [BlockAw-1:0] CARFIELD_HOST_FETCH_ENABLE_OFFSET = 8'h b8; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET = 8'h bc; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET = 8'h c0; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET = 8'h c4; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_OFFSET = 8'h c8; - parameter logic [BlockAw-1:0] CARFIELD_HOST_BOOT_ADDR_OFFSET = 8'h cc; - parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET = 8'h d0; - parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET = 8'h d4; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET = 8'h d8; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET = 8'h dc; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET = 8'h e0; - parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET = 8'h e4; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BUSY_OFFSET = 8'h e8; - parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_EOC_OFFSET = 8'h ec; - parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG0_OFFSET = 8'h f0; - parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG1_OFFSET = 8'h f4; - parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG2_OFFSET = 8'h f8; - parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG3_OFFSET = 8'h fc; + parameter logic [BlockAw-1:0] CARFIELD_JEDEC_IDCODE_OFFSET = 8'h 14; + parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH0_OFFSET = 8'h 18; + parameter logic [BlockAw-1:0] CARFIELD_GENERIC_SCRATCH1_OFFSET = 8'h 1c; + parameter logic [BlockAw-1:0] CARFIELD_HOST_RST_OFFSET = 8'h 20; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_RST_OFFSET = 8'h 24; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_RST_OFFSET = 8'h 28; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_RST_OFFSET = 8'h 2c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_RST_OFFSET = 8'h 30; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_RST_OFFSET = 8'h 34; + parameter logic [BlockAw-1:0] CARFIELD_L2_RST_OFFSET = 8'h 38; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_OFFSET = 8'h 3c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET = 8'h 40; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET = 8'h 44; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET = 8'h 48; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET = 8'h 4c; + parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_OFFSET = 8'h 50; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET = 8'h 54; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 58; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET = 8'h 5c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 60; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET = 8'h 64; + parameter logic [BlockAw-1:0] CARFIELD_L2_ISOLATE_STATUS_OFFSET = 8'h 68; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_EN_OFFSET = 8'h 6c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET = 8'h 70; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET = 8'h 74; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET = 8'h 78; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET = 8'h 7c; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_EN_OFFSET = 8'h 80; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_SEL_OFFSET = 8'h 84; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET = 8'h 88; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET = 8'h 8c; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET = 8'h 90; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET = 8'h 94; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_SEL_OFFSET = 8'h 98; + parameter logic [BlockAw-1:0] CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET = 8'h 9c; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a0; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET = 8'h a4; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h a8; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET = 8'h ac; + parameter logic [BlockAw-1:0] CARFIELD_L2_CLK_DIV_VALUE_OFFSET = 8'h b0; + parameter logic [BlockAw-1:0] CARFIELD_HOST_FETCH_ENABLE_OFFSET = 8'h b4; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET = 8'h b8; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET = 8'h bc; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET = 8'h c0; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_OFFSET = 8'h c4; + parameter logic [BlockAw-1:0] CARFIELD_HOST_BOOT_ADDR_OFFSET = 8'h c8; + parameter logic [BlockAw-1:0] CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET = 8'h cc; + parameter logic [BlockAw-1:0] CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET = 8'h d0; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET = 8'h d4; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET = 8'h d8; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET = 8'h dc; + parameter logic [BlockAw-1:0] CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET = 8'h e0; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_BUSY_OFFSET = 8'h e4; + parameter logic [BlockAw-1:0] CARFIELD_PULP_CLUSTER_EOC_OFFSET = 8'h e8; + parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG0_OFFSET = 8'h ec; + parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG1_OFFSET = 8'h f0; + parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG2_OFFSET = 8'h f4; + parameter logic [BlockAw-1:0] CARFIELD_L2_SRAM_CONFIG3_OFFSET = 8'h f8; // Register index typedef enum int { @@ -432,7 +420,6 @@ package carfield_reg_pkg; CARFIELD_VERSION2, CARFIELD_VERSION3, CARFIELD_VERSION4, - CARFIELD_BOOT_MODE, CARFIELD_JEDEC_IDCODE, CARFIELD_GENERIC_SCRATCH0, CARFIELD_GENERIC_SCRATCH1, @@ -443,18 +430,18 @@ package carfield_reg_pkg; CARFIELD_PULP_CLUSTER_RST, CARFIELD_SPATZ_CLUSTER_RST, CARFIELD_L2_RST, - CARFIELD_HOST_ISOLATE, CARFIELD_PERIPH_ISOLATE, CARFIELD_SAFETY_ISLAND_ISOLATE, CARFIELD_SECURITY_ISLAND_ISOLATE, CARFIELD_PULP_CLUSTER_ISOLATE, CARFIELD_SPATZ_CLUSTER_ISOLATE, - CARFIELD_HOST_ISOLATE_STATUS, + CARFIELD_L2_ISOLATE, CARFIELD_PERIPH_ISOLATE_STATUS, CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS, CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS, CARFIELD_PULP_CLUSTER_ISOLATE_STATUS, CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS, + CARFIELD_L2_ISOLATE_STATUS, CARFIELD_PERIPH_CLK_EN, CARFIELD_SAFETY_ISLAND_CLK_EN, CARFIELD_SECURITY_ISLAND_CLK_EN, @@ -494,71 +481,70 @@ package carfield_reg_pkg; } carfield_id_e; // Register width information to check illegal writes - parameter logic [3:0] CARFIELD_PERMIT [64] = '{ + parameter logic [3:0] CARFIELD_PERMIT [63] = '{ 4'b 1111, // index[ 0] CARFIELD_VERSION0 4'b 1111, // index[ 1] CARFIELD_VERSION1 4'b 1111, // index[ 2] CARFIELD_VERSION2 4'b 1111, // index[ 3] CARFIELD_VERSION3 4'b 1111, // index[ 4] CARFIELD_VERSION4 - 4'b 0001, // index[ 5] CARFIELD_BOOT_MODE - 4'b 1111, // index[ 6] CARFIELD_JEDEC_IDCODE - 4'b 1111, // index[ 7] CARFIELD_GENERIC_SCRATCH0 - 4'b 1111, // index[ 8] CARFIELD_GENERIC_SCRATCH1 - 4'b 0001, // index[ 9] CARFIELD_HOST_RST - 4'b 0001, // index[10] CARFIELD_PERIPH_RST - 4'b 0001, // index[11] CARFIELD_SAFETY_ISLAND_RST - 4'b 0001, // index[12] CARFIELD_SECURITY_ISLAND_RST - 4'b 0001, // index[13] CARFIELD_PULP_CLUSTER_RST - 4'b 0001, // index[14] CARFIELD_SPATZ_CLUSTER_RST - 4'b 0001, // index[15] CARFIELD_L2_RST - 4'b 0001, // index[16] CARFIELD_HOST_ISOLATE - 4'b 0001, // index[17] CARFIELD_PERIPH_ISOLATE - 4'b 0001, // index[18] CARFIELD_SAFETY_ISLAND_ISOLATE - 4'b 0001, // index[19] CARFIELD_SECURITY_ISLAND_ISOLATE - 4'b 0001, // index[20] CARFIELD_PULP_CLUSTER_ISOLATE - 4'b 0001, // index[21] CARFIELD_SPATZ_CLUSTER_ISOLATE - 4'b 0001, // index[22] CARFIELD_HOST_ISOLATE_STATUS - 4'b 0001, // index[23] CARFIELD_PERIPH_ISOLATE_STATUS - 4'b 0001, // index[24] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS - 4'b 0001, // index[25] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS - 4'b 0001, // index[26] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS - 4'b 0001, // index[27] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS - 4'b 0001, // index[28] CARFIELD_PERIPH_CLK_EN - 4'b 0001, // index[29] CARFIELD_SAFETY_ISLAND_CLK_EN - 4'b 0001, // index[30] CARFIELD_SECURITY_ISLAND_CLK_EN - 4'b 0001, // index[31] CARFIELD_PULP_CLUSTER_CLK_EN - 4'b 0001, // index[32] CARFIELD_SPATZ_CLUSTER_CLK_EN - 4'b 0001, // index[33] CARFIELD_L2_CLK_EN - 4'b 0001, // index[34] CARFIELD_PERIPH_CLK_SEL - 4'b 0001, // index[35] CARFIELD_SAFETY_ISLAND_CLK_SEL - 4'b 0001, // index[36] CARFIELD_SECURITY_ISLAND_CLK_SEL - 4'b 0001, // index[37] CARFIELD_PULP_CLUSTER_CLK_SEL - 4'b 0001, // index[38] CARFIELD_SPATZ_CLUSTER_CLK_SEL - 4'b 0001, // index[39] CARFIELD_L2_CLK_SEL - 4'b 0111, // index[40] CARFIELD_PERIPH_CLK_DIV_VALUE - 4'b 0111, // index[41] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE - 4'b 0111, // index[42] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE - 4'b 0111, // index[43] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE - 4'b 0111, // index[44] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE - 4'b 0111, // index[45] CARFIELD_L2_CLK_DIV_VALUE - 4'b 0001, // index[46] CARFIELD_HOST_FETCH_ENABLE - 4'b 0001, // index[47] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE - 4'b 0001, // index[48] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE - 4'b 0001, // index[49] CARFIELD_PULP_CLUSTER_FETCH_ENABLE - 4'b 0001, // index[50] CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE - 4'b 1111, // index[51] CARFIELD_HOST_BOOT_ADDR - 4'b 1111, // index[52] CARFIELD_SAFETY_ISLAND_BOOT_ADDR - 4'b 1111, // index[53] CARFIELD_SECURITY_ISLAND_BOOT_ADDR - 4'b 1111, // index[54] CARFIELD_PULP_CLUSTER_BOOT_ADDR - 4'b 1111, // index[55] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR - 4'b 0001, // index[56] CARFIELD_PULP_CLUSTER_BOOT_ENABLE - 4'b 0001, // index[57] CARFIELD_SPATZ_CLUSTER_BUSY - 4'b 0001, // index[58] CARFIELD_PULP_CLUSTER_BUSY - 4'b 0001, // index[59] CARFIELD_PULP_CLUSTER_EOC - 4'b 1111, // index[60] CARFIELD_L2_SRAM_CONFIG0 - 4'b 1111, // index[61] CARFIELD_L2_SRAM_CONFIG1 - 4'b 1111, // index[62] CARFIELD_L2_SRAM_CONFIG2 - 4'b 1111 // index[63] CARFIELD_L2_SRAM_CONFIG3 + 4'b 1111, // index[ 5] CARFIELD_JEDEC_IDCODE + 4'b 1111, // index[ 6] CARFIELD_GENERIC_SCRATCH0 + 4'b 1111, // index[ 7] CARFIELD_GENERIC_SCRATCH1 + 4'b 0001, // index[ 8] CARFIELD_HOST_RST + 4'b 0001, // index[ 9] CARFIELD_PERIPH_RST + 4'b 0001, // index[10] CARFIELD_SAFETY_ISLAND_RST + 4'b 0001, // index[11] CARFIELD_SECURITY_ISLAND_RST + 4'b 0001, // index[12] CARFIELD_PULP_CLUSTER_RST + 4'b 0001, // index[13] CARFIELD_SPATZ_CLUSTER_RST + 4'b 0001, // index[14] CARFIELD_L2_RST + 4'b 0001, // index[15] CARFIELD_PERIPH_ISOLATE + 4'b 0001, // index[16] CARFIELD_SAFETY_ISLAND_ISOLATE + 4'b 0001, // index[17] CARFIELD_SECURITY_ISLAND_ISOLATE + 4'b 0001, // index[18] CARFIELD_PULP_CLUSTER_ISOLATE + 4'b 0001, // index[19] CARFIELD_SPATZ_CLUSTER_ISOLATE + 4'b 0001, // index[20] CARFIELD_L2_ISOLATE + 4'b 0001, // index[21] CARFIELD_PERIPH_ISOLATE_STATUS + 4'b 0001, // index[22] CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS + 4'b 0001, // index[23] CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS + 4'b 0001, // index[24] CARFIELD_PULP_CLUSTER_ISOLATE_STATUS + 4'b 0001, // index[25] CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS + 4'b 0001, // index[26] CARFIELD_L2_ISOLATE_STATUS + 4'b 0001, // index[27] CARFIELD_PERIPH_CLK_EN + 4'b 0001, // index[28] CARFIELD_SAFETY_ISLAND_CLK_EN + 4'b 0001, // index[29] CARFIELD_SECURITY_ISLAND_CLK_EN + 4'b 0001, // index[30] CARFIELD_PULP_CLUSTER_CLK_EN + 4'b 0001, // index[31] CARFIELD_SPATZ_CLUSTER_CLK_EN + 4'b 0001, // index[32] CARFIELD_L2_CLK_EN + 4'b 0001, // index[33] CARFIELD_PERIPH_CLK_SEL + 4'b 0001, // index[34] CARFIELD_SAFETY_ISLAND_CLK_SEL + 4'b 0001, // index[35] CARFIELD_SECURITY_ISLAND_CLK_SEL + 4'b 0001, // index[36] CARFIELD_PULP_CLUSTER_CLK_SEL + 4'b 0001, // index[37] CARFIELD_SPATZ_CLUSTER_CLK_SEL + 4'b 0001, // index[38] CARFIELD_L2_CLK_SEL + 4'b 0111, // index[39] CARFIELD_PERIPH_CLK_DIV_VALUE + 4'b 0111, // index[40] CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE + 4'b 0111, // index[41] CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE + 4'b 0111, // index[42] CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE + 4'b 0111, // index[43] CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE + 4'b 0111, // index[44] CARFIELD_L2_CLK_DIV_VALUE + 4'b 0001, // index[45] CARFIELD_HOST_FETCH_ENABLE + 4'b 0001, // index[46] CARFIELD_SAFETY_ISLAND_FETCH_ENABLE + 4'b 0001, // index[47] CARFIELD_SECURITY_ISLAND_FETCH_ENABLE + 4'b 0001, // index[48] CARFIELD_PULP_CLUSTER_FETCH_ENABLE + 4'b 0001, // index[49] CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE + 4'b 1111, // index[50] CARFIELD_HOST_BOOT_ADDR + 4'b 1111, // index[51] CARFIELD_SAFETY_ISLAND_BOOT_ADDR + 4'b 1111, // index[52] CARFIELD_SECURITY_ISLAND_BOOT_ADDR + 4'b 1111, // index[53] CARFIELD_PULP_CLUSTER_BOOT_ADDR + 4'b 1111, // index[54] CARFIELD_SPATZ_CLUSTER_BOOT_ADDR + 4'b 0001, // index[55] CARFIELD_PULP_CLUSTER_BOOT_ENABLE + 4'b 0001, // index[56] CARFIELD_SPATZ_CLUSTER_BUSY + 4'b 0001, // index[57] CARFIELD_PULP_CLUSTER_BUSY + 4'b 0001, // index[58] CARFIELD_PULP_CLUSTER_EOC + 4'b 1111, // index[59] CARFIELD_L2_SRAM_CONFIG0 + 4'b 1111, // index[60] CARFIELD_L2_SRAM_CONFIG1 + 4'b 1111, // index[61] CARFIELD_L2_SRAM_CONFIG2 + 4'b 1111 // index[62] CARFIELD_L2_SRAM_CONFIG3 }; endpackage diff --git a/hw/regs/carfield_reg_top.sv b/hw/regs/carfield_reg_top.sv index 06c3e7cc..72d1dc00 100644 --- a/hw/regs/carfield_reg_top.sv +++ b/hw/regs/carfield_reg_top.sv @@ -73,7 +73,6 @@ module carfield_reg_top #( logic [31:0] version2_qs; logic [31:0] version3_qs; logic [31:0] version4_qs; - logic [2:0] boot_mode_qs; logic [31:0] jedec_idcode_qs; logic [31:0] jedec_idcode_wd; logic jedec_idcode_we; @@ -102,7 +101,6 @@ module carfield_reg_top #( logic l2_rst_qs; logic l2_rst_wd; logic l2_rst_we; - logic host_isolate_qs; logic periph_isolate_qs; logic periph_isolate_wd; logic periph_isolate_we; @@ -118,7 +116,9 @@ module carfield_reg_top #( logic spatz_cluster_isolate_qs; logic spatz_cluster_isolate_wd; logic spatz_cluster_isolate_we; - logic host_isolate_status_qs; + logic l2_isolate_qs; + logic l2_isolate_wd; + logic l2_isolate_we; logic periph_isolate_status_qs; logic periph_isolate_status_wd; logic periph_isolate_status_we; @@ -134,6 +134,9 @@ module carfield_reg_top #( logic spatz_cluster_isolate_status_qs; logic spatz_cluster_isolate_status_wd; logic spatz_cluster_isolate_status_we; + logic l2_isolate_status_qs; + logic l2_isolate_status_wd; + logic l2_isolate_status_we; logic periph_clk_en_qs; logic periph_clk_en_wd; logic periph_clk_en_we; @@ -266,32 +269,6 @@ module carfield_reg_top #( assign version4_qs = 32'h0; - // R[boot_mode]: V(False) - - prim_subreg #( - .DW (3), - .SWACCESS("RO"), - .RESVAL (3'h0) - ) u_boot_mode ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (hw2reg.boot_mode.de), - .d (hw2reg.boot_mode.d ), - - // to internal hardware - .qe (), - .q (reg2hw.boot_mode.q ), - - // to register interface (read) - .qs (boot_mode_qs) - ); - - // R[jedec_idcode]: V(False) prim_subreg #( @@ -561,32 +538,6 @@ module carfield_reg_top #( ); - // R[host_isolate]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RO"), - .RESVAL (1'h0) - ) u_host_isolate ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - .we (1'b0), - .wd ('0 ), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.host_isolate.q ), - - // to register interface (read) - .qs (host_isolate_qs) - ); - - // R[periph_isolate]: V(False) prim_subreg #( @@ -722,29 +673,30 @@ module carfield_reg_top #( ); - // R[host_isolate_status]: V(False) + // R[l2_isolate]: V(False) prim_subreg #( .DW (1), - .SWACCESS("RO"), + .SWACCESS("RW"), .RESVAL (1'h0) - ) u_host_isolate_status ( + ) u_l2_isolate ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .we (1'b0), - .wd ('0 ), + // from register interface + .we (l2_isolate_we), + .wd (l2_isolate_wd), // from internal hardware - .de (hw2reg.host_isolate_status.de), - .d (hw2reg.host_isolate_status.d ), + .de (1'b0), + .d ('0 ), // to internal hardware .qe (), - .q (), + .q (reg2hw.l2_isolate.q ), // to register interface (read) - .qs (host_isolate_status_qs) + .qs (l2_isolate_qs) ); @@ -883,6 +835,33 @@ module carfield_reg_top #( ); + // R[l2_isolate_status]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_l2_isolate_status ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (l2_isolate_status_we), + .wd (l2_isolate_status_wd), + + // from internal hardware + .de (hw2reg.l2_isolate_status.de), + .d (hw2reg.l2_isolate_status.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (l2_isolate_status_qs) + ); + + // R[periph_clk_en]: V(False) prim_subreg #( @@ -1853,7 +1832,7 @@ module carfield_reg_top #( - logic [63:0] addr_hit; + logic [62:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CARFIELD_VERSION0_OFFSET); @@ -1861,65 +1840,64 @@ module carfield_reg_top #( addr_hit[ 2] = (reg_addr == CARFIELD_VERSION2_OFFSET); addr_hit[ 3] = (reg_addr == CARFIELD_VERSION3_OFFSET); addr_hit[ 4] = (reg_addr == CARFIELD_VERSION4_OFFSET); - addr_hit[ 5] = (reg_addr == CARFIELD_BOOT_MODE_OFFSET); - addr_hit[ 6] = (reg_addr == CARFIELD_JEDEC_IDCODE_OFFSET); - addr_hit[ 7] = (reg_addr == CARFIELD_GENERIC_SCRATCH0_OFFSET); - addr_hit[ 8] = (reg_addr == CARFIELD_GENERIC_SCRATCH1_OFFSET); - addr_hit[ 9] = (reg_addr == CARFIELD_HOST_RST_OFFSET); - addr_hit[10] = (reg_addr == CARFIELD_PERIPH_RST_OFFSET); - addr_hit[11] = (reg_addr == CARFIELD_SAFETY_ISLAND_RST_OFFSET); - addr_hit[12] = (reg_addr == CARFIELD_SECURITY_ISLAND_RST_OFFSET); - addr_hit[13] = (reg_addr == CARFIELD_PULP_CLUSTER_RST_OFFSET); - addr_hit[14] = (reg_addr == CARFIELD_SPATZ_CLUSTER_RST_OFFSET); - addr_hit[15] = (reg_addr == CARFIELD_L2_RST_OFFSET); - addr_hit[16] = (reg_addr == CARFIELD_HOST_ISOLATE_OFFSET); - addr_hit[17] = (reg_addr == CARFIELD_PERIPH_ISOLATE_OFFSET); - addr_hit[18] = (reg_addr == CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET); - addr_hit[19] = (reg_addr == CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET); - addr_hit[20] = (reg_addr == CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET); - addr_hit[21] = (reg_addr == CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET); - addr_hit[22] = (reg_addr == CARFIELD_HOST_ISOLATE_STATUS_OFFSET); - addr_hit[23] = (reg_addr == CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET); - addr_hit[24] = (reg_addr == CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET); - addr_hit[25] = (reg_addr == CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET); - addr_hit[26] = (reg_addr == CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET); - addr_hit[27] = (reg_addr == CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET); - addr_hit[28] = (reg_addr == CARFIELD_PERIPH_CLK_EN_OFFSET); - addr_hit[29] = (reg_addr == CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET); - addr_hit[30] = (reg_addr == CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET); - addr_hit[31] = (reg_addr == CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET); - addr_hit[32] = (reg_addr == CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET); - addr_hit[33] = (reg_addr == CARFIELD_L2_CLK_EN_OFFSET); - addr_hit[34] = (reg_addr == CARFIELD_PERIPH_CLK_SEL_OFFSET); - addr_hit[35] = (reg_addr == CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET); - addr_hit[36] = (reg_addr == CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET); - addr_hit[37] = (reg_addr == CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET); - addr_hit[38] = (reg_addr == CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET); - addr_hit[39] = (reg_addr == CARFIELD_L2_CLK_SEL_OFFSET); - addr_hit[40] = (reg_addr == CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET); - addr_hit[41] = (reg_addr == CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET); - addr_hit[42] = (reg_addr == CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET); - addr_hit[43] = (reg_addr == CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET); - addr_hit[44] = (reg_addr == CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET); - addr_hit[45] = (reg_addr == CARFIELD_L2_CLK_DIV_VALUE_OFFSET); - addr_hit[46] = (reg_addr == CARFIELD_HOST_FETCH_ENABLE_OFFSET); - addr_hit[47] = (reg_addr == CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET); - addr_hit[48] = (reg_addr == CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET); - addr_hit[49] = (reg_addr == CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET); - addr_hit[50] = (reg_addr == CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_OFFSET); - addr_hit[51] = (reg_addr == CARFIELD_HOST_BOOT_ADDR_OFFSET); - addr_hit[52] = (reg_addr == CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET); - addr_hit[53] = (reg_addr == CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET); - addr_hit[54] = (reg_addr == CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET); - addr_hit[55] = (reg_addr == CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET); - addr_hit[56] = (reg_addr == CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET); - addr_hit[57] = (reg_addr == CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET); - addr_hit[58] = (reg_addr == CARFIELD_PULP_CLUSTER_BUSY_OFFSET); - addr_hit[59] = (reg_addr == CARFIELD_PULP_CLUSTER_EOC_OFFSET); - addr_hit[60] = (reg_addr == CARFIELD_L2_SRAM_CONFIG0_OFFSET); - addr_hit[61] = (reg_addr == CARFIELD_L2_SRAM_CONFIG1_OFFSET); - addr_hit[62] = (reg_addr == CARFIELD_L2_SRAM_CONFIG2_OFFSET); - addr_hit[63] = (reg_addr == CARFIELD_L2_SRAM_CONFIG3_OFFSET); + addr_hit[ 5] = (reg_addr == CARFIELD_JEDEC_IDCODE_OFFSET); + addr_hit[ 6] = (reg_addr == CARFIELD_GENERIC_SCRATCH0_OFFSET); + addr_hit[ 7] = (reg_addr == CARFIELD_GENERIC_SCRATCH1_OFFSET); + addr_hit[ 8] = (reg_addr == CARFIELD_HOST_RST_OFFSET); + addr_hit[ 9] = (reg_addr == CARFIELD_PERIPH_RST_OFFSET); + addr_hit[10] = (reg_addr == CARFIELD_SAFETY_ISLAND_RST_OFFSET); + addr_hit[11] = (reg_addr == CARFIELD_SECURITY_ISLAND_RST_OFFSET); + addr_hit[12] = (reg_addr == CARFIELD_PULP_CLUSTER_RST_OFFSET); + addr_hit[13] = (reg_addr == CARFIELD_SPATZ_CLUSTER_RST_OFFSET); + addr_hit[14] = (reg_addr == CARFIELD_L2_RST_OFFSET); + addr_hit[15] = (reg_addr == CARFIELD_PERIPH_ISOLATE_OFFSET); + addr_hit[16] = (reg_addr == CARFIELD_SAFETY_ISLAND_ISOLATE_OFFSET); + addr_hit[17] = (reg_addr == CARFIELD_SECURITY_ISLAND_ISOLATE_OFFSET); + addr_hit[18] = (reg_addr == CARFIELD_PULP_CLUSTER_ISOLATE_OFFSET); + addr_hit[19] = (reg_addr == CARFIELD_SPATZ_CLUSTER_ISOLATE_OFFSET); + addr_hit[20] = (reg_addr == CARFIELD_L2_ISOLATE_OFFSET); + addr_hit[21] = (reg_addr == CARFIELD_PERIPH_ISOLATE_STATUS_OFFSET); + addr_hit[22] = (reg_addr == CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_OFFSET); + addr_hit[23] = (reg_addr == CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_OFFSET); + addr_hit[24] = (reg_addr == CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_OFFSET); + addr_hit[25] = (reg_addr == CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_OFFSET); + addr_hit[26] = (reg_addr == CARFIELD_L2_ISOLATE_STATUS_OFFSET); + addr_hit[27] = (reg_addr == CARFIELD_PERIPH_CLK_EN_OFFSET); + addr_hit[28] = (reg_addr == CARFIELD_SAFETY_ISLAND_CLK_EN_OFFSET); + addr_hit[29] = (reg_addr == CARFIELD_SECURITY_ISLAND_CLK_EN_OFFSET); + addr_hit[30] = (reg_addr == CARFIELD_PULP_CLUSTER_CLK_EN_OFFSET); + addr_hit[31] = (reg_addr == CARFIELD_SPATZ_CLUSTER_CLK_EN_OFFSET); + addr_hit[32] = (reg_addr == CARFIELD_L2_CLK_EN_OFFSET); + addr_hit[33] = (reg_addr == CARFIELD_PERIPH_CLK_SEL_OFFSET); + addr_hit[34] = (reg_addr == CARFIELD_SAFETY_ISLAND_CLK_SEL_OFFSET); + addr_hit[35] = (reg_addr == CARFIELD_SECURITY_ISLAND_CLK_SEL_OFFSET); + addr_hit[36] = (reg_addr == CARFIELD_PULP_CLUSTER_CLK_SEL_OFFSET); + addr_hit[37] = (reg_addr == CARFIELD_SPATZ_CLUSTER_CLK_SEL_OFFSET); + addr_hit[38] = (reg_addr == CARFIELD_L2_CLK_SEL_OFFSET); + addr_hit[39] = (reg_addr == CARFIELD_PERIPH_CLK_DIV_VALUE_OFFSET); + addr_hit[40] = (reg_addr == CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET); + addr_hit[41] = (reg_addr == CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET); + addr_hit[42] = (reg_addr == CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET); + addr_hit[43] = (reg_addr == CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET); + addr_hit[44] = (reg_addr == CARFIELD_L2_CLK_DIV_VALUE_OFFSET); + addr_hit[45] = (reg_addr == CARFIELD_HOST_FETCH_ENABLE_OFFSET); + addr_hit[46] = (reg_addr == CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_OFFSET); + addr_hit[47] = (reg_addr == CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_OFFSET); + addr_hit[48] = (reg_addr == CARFIELD_PULP_CLUSTER_FETCH_ENABLE_OFFSET); + addr_hit[49] = (reg_addr == CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_OFFSET); + addr_hit[50] = (reg_addr == CARFIELD_HOST_BOOT_ADDR_OFFSET); + addr_hit[51] = (reg_addr == CARFIELD_SAFETY_ISLAND_BOOT_ADDR_OFFSET); + addr_hit[52] = (reg_addr == CARFIELD_SECURITY_ISLAND_BOOT_ADDR_OFFSET); + addr_hit[53] = (reg_addr == CARFIELD_PULP_CLUSTER_BOOT_ADDR_OFFSET); + addr_hit[54] = (reg_addr == CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_OFFSET); + addr_hit[55] = (reg_addr == CARFIELD_PULP_CLUSTER_BOOT_ENABLE_OFFSET); + addr_hit[56] = (reg_addr == CARFIELD_SPATZ_CLUSTER_BUSY_OFFSET); + addr_hit[57] = (reg_addr == CARFIELD_PULP_CLUSTER_BUSY_OFFSET); + addr_hit[58] = (reg_addr == CARFIELD_PULP_CLUSTER_EOC_OFFSET); + addr_hit[59] = (reg_addr == CARFIELD_L2_SRAM_CONFIG0_OFFSET); + addr_hit[60] = (reg_addr == CARFIELD_L2_SRAM_CONFIG1_OFFSET); + addr_hit[61] = (reg_addr == CARFIELD_L2_SRAM_CONFIG2_OFFSET); + addr_hit[62] = (reg_addr == CARFIELD_L2_SRAM_CONFIG3_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -1989,161 +1967,166 @@ module carfield_reg_top #( (addr_hit[59] & (|(CARFIELD_PERMIT[59] & ~reg_be))) | (addr_hit[60] & (|(CARFIELD_PERMIT[60] & ~reg_be))) | (addr_hit[61] & (|(CARFIELD_PERMIT[61] & ~reg_be))) | - (addr_hit[62] & (|(CARFIELD_PERMIT[62] & ~reg_be))) | - (addr_hit[63] & (|(CARFIELD_PERMIT[63] & ~reg_be))))); + (addr_hit[62] & (|(CARFIELD_PERMIT[62] & ~reg_be))))); end - assign jedec_idcode_we = addr_hit[6] & reg_we & !reg_error; + assign jedec_idcode_we = addr_hit[5] & reg_we & !reg_error; assign jedec_idcode_wd = reg_wdata[31:0]; - assign generic_scratch0_we = addr_hit[7] & reg_we & !reg_error; + assign generic_scratch0_we = addr_hit[6] & reg_we & !reg_error; assign generic_scratch0_wd = reg_wdata[31:0]; - assign generic_scratch1_we = addr_hit[8] & reg_we & !reg_error; + assign generic_scratch1_we = addr_hit[7] & reg_we & !reg_error; assign generic_scratch1_wd = reg_wdata[31:0]; - assign periph_rst_we = addr_hit[10] & reg_we & !reg_error; + assign periph_rst_we = addr_hit[9] & reg_we & !reg_error; assign periph_rst_wd = reg_wdata[0]; - assign safety_island_rst_we = addr_hit[11] & reg_we & !reg_error; + assign safety_island_rst_we = addr_hit[10] & reg_we & !reg_error; assign safety_island_rst_wd = reg_wdata[0]; - assign security_island_rst_we = addr_hit[12] & reg_we & !reg_error; + assign security_island_rst_we = addr_hit[11] & reg_we & !reg_error; assign security_island_rst_wd = reg_wdata[0]; - assign pulp_cluster_rst_we = addr_hit[13] & reg_we & !reg_error; + assign pulp_cluster_rst_we = addr_hit[12] & reg_we & !reg_error; assign pulp_cluster_rst_wd = reg_wdata[0]; - assign spatz_cluster_rst_we = addr_hit[14] & reg_we & !reg_error; + assign spatz_cluster_rst_we = addr_hit[13] & reg_we & !reg_error; assign spatz_cluster_rst_wd = reg_wdata[0]; - assign l2_rst_we = addr_hit[15] & reg_we & !reg_error; + assign l2_rst_we = addr_hit[14] & reg_we & !reg_error; assign l2_rst_wd = reg_wdata[0]; - assign periph_isolate_we = addr_hit[17] & reg_we & !reg_error; + assign periph_isolate_we = addr_hit[15] & reg_we & !reg_error; assign periph_isolate_wd = reg_wdata[0]; - assign safety_island_isolate_we = addr_hit[18] & reg_we & !reg_error; + assign safety_island_isolate_we = addr_hit[16] & reg_we & !reg_error; assign safety_island_isolate_wd = reg_wdata[0]; - assign security_island_isolate_we = addr_hit[19] & reg_we & !reg_error; + assign security_island_isolate_we = addr_hit[17] & reg_we & !reg_error; assign security_island_isolate_wd = reg_wdata[0]; - assign pulp_cluster_isolate_we = addr_hit[20] & reg_we & !reg_error; + assign pulp_cluster_isolate_we = addr_hit[18] & reg_we & !reg_error; assign pulp_cluster_isolate_wd = reg_wdata[0]; - assign spatz_cluster_isolate_we = addr_hit[21] & reg_we & !reg_error; + assign spatz_cluster_isolate_we = addr_hit[19] & reg_we & !reg_error; assign spatz_cluster_isolate_wd = reg_wdata[0]; - assign periph_isolate_status_we = addr_hit[23] & reg_we & !reg_error; + assign l2_isolate_we = addr_hit[20] & reg_we & !reg_error; + assign l2_isolate_wd = reg_wdata[0]; + + assign periph_isolate_status_we = addr_hit[21] & reg_we & !reg_error; assign periph_isolate_status_wd = reg_wdata[0]; - assign safety_island_isolate_status_we = addr_hit[24] & reg_we & !reg_error; + assign safety_island_isolate_status_we = addr_hit[22] & reg_we & !reg_error; assign safety_island_isolate_status_wd = reg_wdata[0]; - assign security_island_isolate_status_we = addr_hit[25] & reg_we & !reg_error; + assign security_island_isolate_status_we = addr_hit[23] & reg_we & !reg_error; assign security_island_isolate_status_wd = reg_wdata[0]; - assign pulp_cluster_isolate_status_we = addr_hit[26] & reg_we & !reg_error; + assign pulp_cluster_isolate_status_we = addr_hit[24] & reg_we & !reg_error; assign pulp_cluster_isolate_status_wd = reg_wdata[0]; - assign spatz_cluster_isolate_status_we = addr_hit[27] & reg_we & !reg_error; + assign spatz_cluster_isolate_status_we = addr_hit[25] & reg_we & !reg_error; assign spatz_cluster_isolate_status_wd = reg_wdata[0]; - assign periph_clk_en_we = addr_hit[28] & reg_we & !reg_error; + assign l2_isolate_status_we = addr_hit[26] & reg_we & !reg_error; + assign l2_isolate_status_wd = reg_wdata[0]; + + assign periph_clk_en_we = addr_hit[27] & reg_we & !reg_error; assign periph_clk_en_wd = reg_wdata[0]; - assign safety_island_clk_en_we = addr_hit[29] & reg_we & !reg_error; + assign safety_island_clk_en_we = addr_hit[28] & reg_we & !reg_error; assign safety_island_clk_en_wd = reg_wdata[0]; - assign security_island_clk_en_we = addr_hit[30] & reg_we & !reg_error; + assign security_island_clk_en_we = addr_hit[29] & reg_we & !reg_error; assign security_island_clk_en_wd = reg_wdata[0]; - assign pulp_cluster_clk_en_we = addr_hit[31] & reg_we & !reg_error; + assign pulp_cluster_clk_en_we = addr_hit[30] & reg_we & !reg_error; assign pulp_cluster_clk_en_wd = reg_wdata[0]; - assign spatz_cluster_clk_en_we = addr_hit[32] & reg_we & !reg_error; + assign spatz_cluster_clk_en_we = addr_hit[31] & reg_we & !reg_error; assign spatz_cluster_clk_en_wd = reg_wdata[0]; - assign l2_clk_en_we = addr_hit[33] & reg_we & !reg_error; + assign l2_clk_en_we = addr_hit[32] & reg_we & !reg_error; assign l2_clk_en_wd = reg_wdata[0]; - assign periph_clk_sel_we = addr_hit[34] & reg_we & !reg_error; + assign periph_clk_sel_we = addr_hit[33] & reg_we & !reg_error; assign periph_clk_sel_wd = reg_wdata[1:0]; - assign safety_island_clk_sel_we = addr_hit[35] & reg_we & !reg_error; + assign safety_island_clk_sel_we = addr_hit[34] & reg_we & !reg_error; assign safety_island_clk_sel_wd = reg_wdata[1:0]; - assign security_island_clk_sel_we = addr_hit[36] & reg_we & !reg_error; + assign security_island_clk_sel_we = addr_hit[35] & reg_we & !reg_error; assign security_island_clk_sel_wd = reg_wdata[1:0]; - assign pulp_cluster_clk_sel_we = addr_hit[37] & reg_we & !reg_error; + assign pulp_cluster_clk_sel_we = addr_hit[36] & reg_we & !reg_error; assign pulp_cluster_clk_sel_wd = reg_wdata[1:0]; - assign spatz_cluster_clk_sel_we = addr_hit[38] & reg_we & !reg_error; + assign spatz_cluster_clk_sel_we = addr_hit[37] & reg_we & !reg_error; assign spatz_cluster_clk_sel_wd = reg_wdata[1:0]; - assign l2_clk_sel_we = addr_hit[39] & reg_we & !reg_error; + assign l2_clk_sel_we = addr_hit[38] & reg_we & !reg_error; assign l2_clk_sel_wd = reg_wdata[1:0]; - assign periph_clk_div_value_we = addr_hit[40] & reg_we & !reg_error; + assign periph_clk_div_value_we = addr_hit[39] & reg_we & !reg_error; assign periph_clk_div_value_wd = reg_wdata[23:0]; - assign safety_island_clk_div_value_we = addr_hit[41] & reg_we & !reg_error; + assign safety_island_clk_div_value_we = addr_hit[40] & reg_we & !reg_error; assign safety_island_clk_div_value_wd = reg_wdata[23:0]; - assign security_island_clk_div_value_we = addr_hit[42] & reg_we & !reg_error; + assign security_island_clk_div_value_we = addr_hit[41] & reg_we & !reg_error; assign security_island_clk_div_value_wd = reg_wdata[23:0]; - assign pulp_cluster_clk_div_value_we = addr_hit[43] & reg_we & !reg_error; + assign pulp_cluster_clk_div_value_we = addr_hit[42] & reg_we & !reg_error; assign pulp_cluster_clk_div_value_wd = reg_wdata[23:0]; - assign spatz_cluster_clk_div_value_we = addr_hit[44] & reg_we & !reg_error; + assign spatz_cluster_clk_div_value_we = addr_hit[43] & reg_we & !reg_error; assign spatz_cluster_clk_div_value_wd = reg_wdata[23:0]; - assign l2_clk_div_value_we = addr_hit[45] & reg_we & !reg_error; + assign l2_clk_div_value_we = addr_hit[44] & reg_we & !reg_error; assign l2_clk_div_value_wd = reg_wdata[23:0]; - assign safety_island_fetch_enable_we = addr_hit[47] & reg_we & !reg_error; + assign safety_island_fetch_enable_we = addr_hit[46] & reg_we & !reg_error; assign safety_island_fetch_enable_wd = reg_wdata[0]; - assign security_island_fetch_enable_we = addr_hit[48] & reg_we & !reg_error; + assign security_island_fetch_enable_we = addr_hit[47] & reg_we & !reg_error; assign security_island_fetch_enable_wd = reg_wdata[0]; - assign pulp_cluster_fetch_enable_we = addr_hit[49] & reg_we & !reg_error; + assign pulp_cluster_fetch_enable_we = addr_hit[48] & reg_we & !reg_error; assign pulp_cluster_fetch_enable_wd = reg_wdata[0]; - assign spatz_cluster_fetch_enable_we = addr_hit[50] & reg_we & !reg_error; + assign spatz_cluster_fetch_enable_we = addr_hit[49] & reg_we & !reg_error; assign spatz_cluster_fetch_enable_wd = reg_wdata[0]; - assign host_boot_addr_we = addr_hit[51] & reg_we & !reg_error; + assign host_boot_addr_we = addr_hit[50] & reg_we & !reg_error; assign host_boot_addr_wd = reg_wdata[31:0]; - assign safety_island_boot_addr_we = addr_hit[52] & reg_we & !reg_error; + assign safety_island_boot_addr_we = addr_hit[51] & reg_we & !reg_error; assign safety_island_boot_addr_wd = reg_wdata[31:0]; - assign security_island_boot_addr_we = addr_hit[53] & reg_we & !reg_error; + assign security_island_boot_addr_we = addr_hit[52] & reg_we & !reg_error; assign security_island_boot_addr_wd = reg_wdata[31:0]; - assign pulp_cluster_boot_addr_we = addr_hit[54] & reg_we & !reg_error; + assign pulp_cluster_boot_addr_we = addr_hit[53] & reg_we & !reg_error; assign pulp_cluster_boot_addr_wd = reg_wdata[31:0]; - assign spatz_cluster_boot_addr_we = addr_hit[55] & reg_we & !reg_error; + assign spatz_cluster_boot_addr_we = addr_hit[54] & reg_we & !reg_error; assign spatz_cluster_boot_addr_wd = reg_wdata[31:0]; - assign pulp_cluster_boot_enable_we = addr_hit[56] & reg_we & !reg_error; + assign pulp_cluster_boot_enable_we = addr_hit[55] & reg_we & !reg_error; assign pulp_cluster_boot_enable_wd = reg_wdata[0]; - assign l2_sram_config0_we = addr_hit[60] & reg_we & !reg_error; + assign l2_sram_config0_we = addr_hit[59] & reg_we & !reg_error; assign l2_sram_config0_wd = reg_wdata[31:0]; - assign l2_sram_config1_we = addr_hit[61] & reg_we & !reg_error; + assign l2_sram_config1_we = addr_hit[60] & reg_we & !reg_error; assign l2_sram_config1_wd = reg_wdata[31:0]; - assign l2_sram_config2_we = addr_hit[62] & reg_we & !reg_error; + assign l2_sram_config2_we = addr_hit[61] & reg_we & !reg_error; assign l2_sram_config2_wd = reg_wdata[31:0]; - assign l2_sram_config3_we = addr_hit[63] & reg_we & !reg_error; + assign l2_sram_config3_we = addr_hit[62] & reg_we & !reg_error; assign l2_sram_config3_wd = reg_wdata[31:0]; // Read data return @@ -2171,238 +2154,234 @@ module carfield_reg_top #( end addr_hit[5]: begin - reg_rdata_next[2:0] = boot_mode_qs; + reg_rdata_next[31:0] = jedec_idcode_qs; end addr_hit[6]: begin - reg_rdata_next[31:0] = jedec_idcode_qs; + reg_rdata_next[31:0] = generic_scratch0_qs; end addr_hit[7]: begin - reg_rdata_next[31:0] = generic_scratch0_qs; + reg_rdata_next[31:0] = generic_scratch1_qs; end addr_hit[8]: begin - reg_rdata_next[31:0] = generic_scratch1_qs; + reg_rdata_next[0] = host_rst_qs; end addr_hit[9]: begin - reg_rdata_next[0] = host_rst_qs; + reg_rdata_next[0] = periph_rst_qs; end addr_hit[10]: begin - reg_rdata_next[0] = periph_rst_qs; + reg_rdata_next[0] = safety_island_rst_qs; end addr_hit[11]: begin - reg_rdata_next[0] = safety_island_rst_qs; + reg_rdata_next[0] = security_island_rst_qs; end addr_hit[12]: begin - reg_rdata_next[0] = security_island_rst_qs; + reg_rdata_next[0] = pulp_cluster_rst_qs; end addr_hit[13]: begin - reg_rdata_next[0] = pulp_cluster_rst_qs; + reg_rdata_next[0] = spatz_cluster_rst_qs; end addr_hit[14]: begin - reg_rdata_next[0] = spatz_cluster_rst_qs; + reg_rdata_next[0] = l2_rst_qs; end addr_hit[15]: begin - reg_rdata_next[0] = l2_rst_qs; + reg_rdata_next[0] = periph_isolate_qs; end addr_hit[16]: begin - reg_rdata_next[0] = host_isolate_qs; + reg_rdata_next[0] = safety_island_isolate_qs; end addr_hit[17]: begin - reg_rdata_next[0] = periph_isolate_qs; + reg_rdata_next[0] = security_island_isolate_qs; end addr_hit[18]: begin - reg_rdata_next[0] = safety_island_isolate_qs; + reg_rdata_next[0] = pulp_cluster_isolate_qs; end addr_hit[19]: begin - reg_rdata_next[0] = security_island_isolate_qs; + reg_rdata_next[0] = spatz_cluster_isolate_qs; end addr_hit[20]: begin - reg_rdata_next[0] = pulp_cluster_isolate_qs; + reg_rdata_next[0] = l2_isolate_qs; end addr_hit[21]: begin - reg_rdata_next[0] = spatz_cluster_isolate_qs; + reg_rdata_next[0] = periph_isolate_status_qs; end addr_hit[22]: begin - reg_rdata_next[0] = host_isolate_status_qs; + reg_rdata_next[0] = safety_island_isolate_status_qs; end addr_hit[23]: begin - reg_rdata_next[0] = periph_isolate_status_qs; + reg_rdata_next[0] = security_island_isolate_status_qs; end addr_hit[24]: begin - reg_rdata_next[0] = safety_island_isolate_status_qs; + reg_rdata_next[0] = pulp_cluster_isolate_status_qs; end addr_hit[25]: begin - reg_rdata_next[0] = security_island_isolate_status_qs; + reg_rdata_next[0] = spatz_cluster_isolate_status_qs; end addr_hit[26]: begin - reg_rdata_next[0] = pulp_cluster_isolate_status_qs; + reg_rdata_next[0] = l2_isolate_status_qs; end addr_hit[27]: begin - reg_rdata_next[0] = spatz_cluster_isolate_status_qs; - end - - addr_hit[28]: begin reg_rdata_next[0] = periph_clk_en_qs; end - addr_hit[29]: begin + addr_hit[28]: begin reg_rdata_next[0] = safety_island_clk_en_qs; end - addr_hit[30]: begin + addr_hit[29]: begin reg_rdata_next[0] = security_island_clk_en_qs; end - addr_hit[31]: begin + addr_hit[30]: begin reg_rdata_next[0] = pulp_cluster_clk_en_qs; end - addr_hit[32]: begin + addr_hit[31]: begin reg_rdata_next[0] = spatz_cluster_clk_en_qs; end - addr_hit[33]: begin + addr_hit[32]: begin reg_rdata_next[0] = l2_clk_en_qs; end - addr_hit[34]: begin + addr_hit[33]: begin reg_rdata_next[1:0] = periph_clk_sel_qs; end - addr_hit[35]: begin + addr_hit[34]: begin reg_rdata_next[1:0] = safety_island_clk_sel_qs; end - addr_hit[36]: begin + addr_hit[35]: begin reg_rdata_next[1:0] = security_island_clk_sel_qs; end - addr_hit[37]: begin + addr_hit[36]: begin reg_rdata_next[1:0] = pulp_cluster_clk_sel_qs; end - addr_hit[38]: begin + addr_hit[37]: begin reg_rdata_next[1:0] = spatz_cluster_clk_sel_qs; end - addr_hit[39]: begin + addr_hit[38]: begin reg_rdata_next[1:0] = l2_clk_sel_qs; end - addr_hit[40]: begin + addr_hit[39]: begin reg_rdata_next[23:0] = periph_clk_div_value_qs; end - addr_hit[41]: begin + addr_hit[40]: begin reg_rdata_next[23:0] = safety_island_clk_div_value_qs; end - addr_hit[42]: begin + addr_hit[41]: begin reg_rdata_next[23:0] = security_island_clk_div_value_qs; end - addr_hit[43]: begin + addr_hit[42]: begin reg_rdata_next[23:0] = pulp_cluster_clk_div_value_qs; end - addr_hit[44]: begin + addr_hit[43]: begin reg_rdata_next[23:0] = spatz_cluster_clk_div_value_qs; end - addr_hit[45]: begin + addr_hit[44]: begin reg_rdata_next[23:0] = l2_clk_div_value_qs; end - addr_hit[46]: begin + addr_hit[45]: begin reg_rdata_next[0] = host_fetch_enable_qs; end - addr_hit[47]: begin + addr_hit[46]: begin reg_rdata_next[0] = safety_island_fetch_enable_qs; end - addr_hit[48]: begin + addr_hit[47]: begin reg_rdata_next[0] = security_island_fetch_enable_qs; end - addr_hit[49]: begin + addr_hit[48]: begin reg_rdata_next[0] = pulp_cluster_fetch_enable_qs; end - addr_hit[50]: begin + addr_hit[49]: begin reg_rdata_next[0] = spatz_cluster_fetch_enable_qs; end - addr_hit[51]: begin + addr_hit[50]: begin reg_rdata_next[31:0] = host_boot_addr_qs; end - addr_hit[52]: begin + addr_hit[51]: begin reg_rdata_next[31:0] = safety_island_boot_addr_qs; end - addr_hit[53]: begin + addr_hit[52]: begin reg_rdata_next[31:0] = security_island_boot_addr_qs; end - addr_hit[54]: begin + addr_hit[53]: begin reg_rdata_next[31:0] = pulp_cluster_boot_addr_qs; end - addr_hit[55]: begin + addr_hit[54]: begin reg_rdata_next[31:0] = spatz_cluster_boot_addr_qs; end - addr_hit[56]: begin + addr_hit[55]: begin reg_rdata_next[0] = pulp_cluster_boot_enable_qs; end - addr_hit[57]: begin + addr_hit[56]: begin reg_rdata_next[0] = spatz_cluster_busy_qs; end - addr_hit[58]: begin + addr_hit[57]: begin reg_rdata_next[0] = pulp_cluster_busy_qs; end - addr_hit[59]: begin + addr_hit[58]: begin reg_rdata_next[0] = pulp_cluster_eoc_qs; end - addr_hit[60]: begin + addr_hit[59]: begin reg_rdata_next[31:0] = l2_sram_config0_qs; end - addr_hit[61]: begin + addr_hit[60]: begin reg_rdata_next[31:0] = l2_sram_config1_qs; end - addr_hit[62]: begin + addr_hit[61]: begin reg_rdata_next[31:0] = l2_sram_config2_qs; end - addr_hit[63]: begin + addr_hit[62]: begin reg_rdata_next[31:0] = l2_sram_config3_qs; end diff --git a/hw/regs/carfield_regs.csv b/hw/regs/carfield_regs.csv index cfdf3b00..58114b9e 100644 --- a/hw/regs/carfield_regs.csv +++ b/hw/regs/carfield_regs.csv @@ -4,7 +4,6 @@ VERSION1,32,ro,none,0,0,Safety Island sha256 commit VERSION2,32,ro,none,0,0,Security Island sha256 commit VERSION3,32,ro,none,0,0,PULP Cluster sha256 commit VERSION4,32,ro,none,0,0,Spatz CLuster sha256 commit -BOOT_MODE,3,ro,hrw,0,0,Boot mode JEDEC_IDCODE,32,rw,none,0,0,JEDEC ID CODE -TODO assign- GENERIC_SCRATCH0,32,rw,hrw,0,0,Scratch GENERIC_SCRATCH1,32,rw,hrw,0,0,Scratch @@ -15,18 +14,18 @@ SECURITY_ISLAND_RST,1,rw,hro,0,0,"Security Island reset -active high, inverted i PULP_CLUSTER_RST,1,rw,hro,0,0,"PULP Cluster reset -active high, inverted in HW-" SPATZ_CLUSTER_RST,1,rw,hro,0,0,"Spatz Cluster reset -active high, inverted in HW-" L2_RST,1,rw,hro,0,0,"L2 reset -active high, inverted in HW-" -HOST_ISOLATE,1,ro,hro,0,0,Host Domain AXI isolate PERIPH_ISOLATE,1,rw,hro,0,0,Periph Domain AXI isolate SAFETY_ISLAND_ISOLATE,1,rw,hro,0,0,Safety Island AXI isolate SECURITY_ISLAND_ISOLATE,1,rw,hro,0,0,Security Island AXI isolate PULP_CLUSTER_ISOLATE,1,rw,hro,0,0,PULP Cluster AXI isolate -SPATZ_CLUSTER_ISOLATE,1,rw,hro,0,0,Spatz Cluster AXI isolate -HOST_ISOLATE_STATUS,1,ro,hwo,0,0,Host Domain AXI isolate status +SPATZ_CLUSTER_ISOLATE,1,rw,hro,0,0,Spatz Cluster AXI isolate +L2_ISOLATE,1,rw,hro,0,0,L2 AXI isolate PERIPH_ISOLATE_STATUS,1,rw,hwo,0,0,Periph Domain AXI isolate status SAFETY_ISLAND_ISOLATE_STATUS,1,rw,hwo,0,0,Safety Island AXI isolate status SECURITY_ISLAND_ISOLATE_STATUS,1,rw,hwo,0,0,Security Island AXI isolate status PULP_CLUSTER_ISOLATE_STATUS,1,rw,hwo,0,0,PULP Cluster AXI isolate status SPATZ_CLUSTER_ISOLATE_STATUS,1,rw,hwo,0,0,Spatz Cluster AXI isolate status +L2_ISOLATE_STATUS,1,rw,hwo,0,0,L2 AXI isolate status PERIPH_CLK_EN,1,rw,hro,0,1,Periph Domain clk gate enable SAFETY_ISLAND_CLK_EN,1,rw,hro,0,1,Safety Island clk gate enable SECURITY_ISLAND_CLK_EN,1,rw,hro,0,1,Security Island clk gate enable diff --git a/hw/regs/carfield_regs.hjson b/hw/regs/carfield_regs.hjson index 13c80e71..218ad443 100644 --- a/hw/regs/carfield_regs.hjson +++ b/hw/regs/carfield_regs.hjson @@ -67,17 +67,6 @@ ], } - { name: "BOOT_MODE", - desc: "Boot mode", - swaccess: "ro", - hwaccess: "hrw", - resval: "0", - hwqe: "0", - fields: [ - { bits: "2:0" } - ], - } - { name: "JEDEC_IDCODE", desc: "JEDEC ID CODE -TODO assign-", swaccess: "rw", @@ -188,17 +177,6 @@ ], } - { name: "HOST_ISOLATE", - desc: "Host Domain AXI isolate", - swaccess: "ro", - hwaccess: "hro", - resval: "0", - hwqe: "0", - fields: [ - { bits: "0:0" } - ], - } - { name: "PERIPH_ISOLATE", desc: "Periph Domain AXI isolate", swaccess: "rw", @@ -244,7 +222,7 @@ } { name: "SPATZ_CLUSTER_ISOLATE", - desc: "Spatz Cluster AXI isolate", + desc: "Spatz Cluster AXI isolate", swaccess: "rw", hwaccess: "hro", resval: "0", @@ -254,10 +232,10 @@ ], } - { name: "HOST_ISOLATE_STATUS", - desc: "Host Domain AXI isolate status", - swaccess: "ro", - hwaccess: "hwo", + { name: "L2_ISOLATE", + desc: "L2 AXI isolate", + swaccess: "rw", + hwaccess: "hro", resval: "0", hwqe: "0", fields: [ @@ -320,6 +298,17 @@ ], } + { name: "L2_ISOLATE_STATUS", + desc: "L2 AXI isolate status", + swaccess: "rw", + hwaccess: "hwo", + resval: "0", + hwqe: "0", + fields: [ + { bits: "0:0" } + ], + } + { name: "PERIPH_CLK_EN", desc: "Periph Domain clk gate enable", swaccess: "rw", diff --git a/sw/include/regs/soc_ctrl.h b/sw/include/regs/soc_ctrl.h index c1d864e9..719701bd 100644 --- a/sw/include/regs/soc_ctrl.h +++ b/sw/include/regs/soc_ctrl.h @@ -31,174 +31,167 @@ extern "C" { // Spatz CLuster sha256 commit #define CARFIELD_VERSION4_REG_OFFSET 0x10 -// Boot mode -#define CARFIELD_BOOT_MODE_REG_OFFSET 0x14 -#define CARFIELD_BOOT_MODE_BOOT_MODE_MASK 0x7 -#define CARFIELD_BOOT_MODE_BOOT_MODE_OFFSET 0 -#define CARFIELD_BOOT_MODE_BOOT_MODE_FIELD \ - ((bitfield_field32_t) { .mask = CARFIELD_BOOT_MODE_BOOT_MODE_MASK, .index = CARFIELD_BOOT_MODE_BOOT_MODE_OFFSET }) - // JEDEC ID CODE -TODO assign- -#define CARFIELD_JEDEC_IDCODE_REG_OFFSET 0x18 +#define CARFIELD_JEDEC_IDCODE_REG_OFFSET 0x14 // Scratch -#define CARFIELD_GENERIC_SCRATCH0_REG_OFFSET 0x1c +#define CARFIELD_GENERIC_SCRATCH0_REG_OFFSET 0x18 // Scratch -#define CARFIELD_GENERIC_SCRATCH1_REG_OFFSET 0x20 +#define CARFIELD_GENERIC_SCRATCH1_REG_OFFSET 0x1c // Host Domain reset -active high, inverted in HW- -#define CARFIELD_HOST_RST_REG_OFFSET 0x24 +#define CARFIELD_HOST_RST_REG_OFFSET 0x20 #define CARFIELD_HOST_RST_HOST_RST_BIT 0 // Periph Domain reset -active high, inverted in HW- -#define CARFIELD_PERIPH_RST_REG_OFFSET 0x28 +#define CARFIELD_PERIPH_RST_REG_OFFSET 0x24 #define CARFIELD_PERIPH_RST_PERIPH_RST_BIT 0 // Safety Island reset -active high, inverted in HW- -#define CARFIELD_SAFETY_ISLAND_RST_REG_OFFSET 0x2c +#define CARFIELD_SAFETY_ISLAND_RST_REG_OFFSET 0x28 #define CARFIELD_SAFETY_ISLAND_RST_SAFETY_ISLAND_RST_BIT 0 // Security Island reset -active high, inverted in HW- -#define CARFIELD_SECURITY_ISLAND_RST_REG_OFFSET 0x30 +#define CARFIELD_SECURITY_ISLAND_RST_REG_OFFSET 0x2c #define CARFIELD_SECURITY_ISLAND_RST_SECURITY_ISLAND_RST_BIT 0 // PULP Cluster reset -active high, inverted in HW- -#define CARFIELD_PULP_CLUSTER_RST_REG_OFFSET 0x34 +#define CARFIELD_PULP_CLUSTER_RST_REG_OFFSET 0x30 #define CARFIELD_PULP_CLUSTER_RST_PULP_CLUSTER_RST_BIT 0 // Spatz Cluster reset -active high, inverted in HW- -#define CARFIELD_SPATZ_CLUSTER_RST_REG_OFFSET 0x38 +#define CARFIELD_SPATZ_CLUSTER_RST_REG_OFFSET 0x34 #define CARFIELD_SPATZ_CLUSTER_RST_SPATZ_CLUSTER_RST_BIT 0 // L2 reset -active high, inverted in HW- -#define CARFIELD_L2_RST_REG_OFFSET 0x3c +#define CARFIELD_L2_RST_REG_OFFSET 0x38 #define CARFIELD_L2_RST_L2_RST_BIT 0 -// Host Domain AXI isolate -#define CARFIELD_HOST_ISOLATE_REG_OFFSET 0x40 -#define CARFIELD_HOST_ISOLATE_HOST_ISOLATE_BIT 0 - // Periph Domain AXI isolate -#define CARFIELD_PERIPH_ISOLATE_REG_OFFSET 0x44 +#define CARFIELD_PERIPH_ISOLATE_REG_OFFSET 0x3c #define CARFIELD_PERIPH_ISOLATE_PERIPH_ISOLATE_BIT 0 // Safety Island AXI isolate -#define CARFIELD_SAFETY_ISLAND_ISOLATE_REG_OFFSET 0x48 +#define CARFIELD_SAFETY_ISLAND_ISOLATE_REG_OFFSET 0x40 #define CARFIELD_SAFETY_ISLAND_ISOLATE_SAFETY_ISLAND_ISOLATE_BIT 0 // Security Island AXI isolate -#define CARFIELD_SECURITY_ISLAND_ISOLATE_REG_OFFSET 0x4c +#define CARFIELD_SECURITY_ISLAND_ISOLATE_REG_OFFSET 0x44 #define CARFIELD_SECURITY_ISLAND_ISOLATE_SECURITY_ISLAND_ISOLATE_BIT 0 // PULP Cluster AXI isolate -#define CARFIELD_PULP_CLUSTER_ISOLATE_REG_OFFSET 0x50 +#define CARFIELD_PULP_CLUSTER_ISOLATE_REG_OFFSET 0x48 #define CARFIELD_PULP_CLUSTER_ISOLATE_PULP_CLUSTER_ISOLATE_BIT 0 -// Spatz Cluster AXI isolate -#define CARFIELD_SPATZ_CLUSTER_ISOLATE_REG_OFFSET 0x54 +// Spatz Cluster AXI isolate +#define CARFIELD_SPATZ_CLUSTER_ISOLATE_REG_OFFSET 0x4c #define CARFIELD_SPATZ_CLUSTER_ISOLATE_SPATZ_CLUSTER_ISOLATE_BIT 0 -// Host Domain AXI isolate status -#define CARFIELD_HOST_ISOLATE_STATUS_REG_OFFSET 0x58 -#define CARFIELD_HOST_ISOLATE_STATUS_HOST_ISOLATE_STATUS_BIT 0 +// L2 AXI isolate +#define CARFIELD_L2_ISOLATE_REG_OFFSET 0x50 +#define CARFIELD_L2_ISOLATE_L2_ISOLATE_BIT 0 // Periph Domain AXI isolate status -#define CARFIELD_PERIPH_ISOLATE_STATUS_REG_OFFSET 0x5c +#define CARFIELD_PERIPH_ISOLATE_STATUS_REG_OFFSET 0x54 #define CARFIELD_PERIPH_ISOLATE_STATUS_PERIPH_ISOLATE_STATUS_BIT 0 // Safety Island AXI isolate status -#define CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_REG_OFFSET 0x60 +#define CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_REG_OFFSET 0x58 #define CARFIELD_SAFETY_ISLAND_ISOLATE_STATUS_SAFETY_ISLAND_ISOLATE_STATUS_BIT 0 // Security Island AXI isolate status -#define CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_REG_OFFSET 0x64 +#define CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_REG_OFFSET 0x5c #define CARFIELD_SECURITY_ISLAND_ISOLATE_STATUS_SECURITY_ISLAND_ISOLATE_STATUS_BIT \ 0 // PULP Cluster AXI isolate status -#define CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_REG_OFFSET 0x68 +#define CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_REG_OFFSET 0x60 #define CARFIELD_PULP_CLUSTER_ISOLATE_STATUS_PULP_CLUSTER_ISOLATE_STATUS_BIT 0 // Spatz Cluster AXI isolate status -#define CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_REG_OFFSET 0x6c +#define CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_REG_OFFSET 0x64 #define CARFIELD_SPATZ_CLUSTER_ISOLATE_STATUS_SPATZ_CLUSTER_ISOLATE_STATUS_BIT 0 +// L2 AXI isolate status +#define CARFIELD_L2_ISOLATE_STATUS_REG_OFFSET 0x68 +#define CARFIELD_L2_ISOLATE_STATUS_L2_ISOLATE_STATUS_BIT 0 + // Periph Domain clk gate enable -#define CARFIELD_PERIPH_CLK_EN_REG_OFFSET 0x70 +#define CARFIELD_PERIPH_CLK_EN_REG_OFFSET 0x6c #define CARFIELD_PERIPH_CLK_EN_PERIPH_CLK_EN_BIT 0 // Safety Island clk gate enable -#define CARFIELD_SAFETY_ISLAND_CLK_EN_REG_OFFSET 0x74 +#define CARFIELD_SAFETY_ISLAND_CLK_EN_REG_OFFSET 0x70 #define CARFIELD_SAFETY_ISLAND_CLK_EN_SAFETY_ISLAND_CLK_EN_BIT 0 // Security Island clk gate enable -#define CARFIELD_SECURITY_ISLAND_CLK_EN_REG_OFFSET 0x78 +#define CARFIELD_SECURITY_ISLAND_CLK_EN_REG_OFFSET 0x74 #define CARFIELD_SECURITY_ISLAND_CLK_EN_SECURITY_ISLAND_CLK_EN_BIT 0 // PULP Cluster clk gate enable -#define CARFIELD_PULP_CLUSTER_CLK_EN_REG_OFFSET 0x7c +#define CARFIELD_PULP_CLUSTER_CLK_EN_REG_OFFSET 0x78 #define CARFIELD_PULP_CLUSTER_CLK_EN_PULP_CLUSTER_CLK_EN_BIT 0 // Spatz Cluster clk gate enable -#define CARFIELD_SPATZ_CLUSTER_CLK_EN_REG_OFFSET 0x80 +#define CARFIELD_SPATZ_CLUSTER_CLK_EN_REG_OFFSET 0x7c #define CARFIELD_SPATZ_CLUSTER_CLK_EN_SPATZ_CLUSTER_CLK_EN_BIT 0 // Shared L2 memory clk gate enable -#define CARFIELD_L2_CLK_EN_REG_OFFSET 0x84 +#define CARFIELD_L2_CLK_EN_REG_OFFSET 0x80 #define CARFIELD_L2_CLK_EN_L2_CLK_EN_BIT 0 // Periph Domain pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) -#define CARFIELD_PERIPH_CLK_SEL_REG_OFFSET 0x88 +#define CARFIELD_PERIPH_CLK_SEL_REG_OFFSET 0x84 #define CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_MASK 0x3 #define CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_OFFSET 0 #define CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_MASK, .index = CARFIELD_PERIPH_CLK_SEL_PERIPH_CLK_SEL_OFFSET }) // Safety Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) -#define CARFIELD_SAFETY_ISLAND_CLK_SEL_REG_OFFSET 0x8c +#define CARFIELD_SAFETY_ISLAND_CLK_SEL_REG_OFFSET 0x88 #define CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_MASK 0x3 #define CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_OFFSET 0 #define CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_MASK, .index = CARFIELD_SAFETY_ISLAND_CLK_SEL_SAFETY_ISLAND_CLK_SEL_OFFSET }) // Security Island pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) -#define CARFIELD_SECURITY_ISLAND_CLK_SEL_REG_OFFSET 0x90 +#define CARFIELD_SECURITY_ISLAND_CLK_SEL_REG_OFFSET 0x8c #define CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_MASK 0x3 #define CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_OFFSET 0 #define CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_MASK, .index = CARFIELD_SECURITY_ISLAND_CLK_SEL_SECURITY_ISLAND_CLK_SEL_OFFSET }) // PULP Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) -#define CARFIELD_PULP_CLUSTER_CLK_SEL_REG_OFFSET 0x94 +#define CARFIELD_PULP_CLUSTER_CLK_SEL_REG_OFFSET 0x90 #define CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_MASK 0x3 #define CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_OFFSET 0 #define CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_MASK, .index = CARFIELD_PULP_CLUSTER_CLK_SEL_PULP_CLUSTER_CLK_SEL_OFFSET }) // Spatz Cluster pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) -#define CARFIELD_SPATZ_CLUSTER_CLK_SEL_REG_OFFSET 0x98 +#define CARFIELD_SPATZ_CLUSTER_CLK_SEL_REG_OFFSET 0x94 #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_MASK 0x3 #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_OFFSET 0 #define CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_MASK, .index = CARFIELD_SPATZ_CLUSTER_CLK_SEL_SPATZ_CLUSTER_CLK_SEL_OFFSET }) // L2 Memory pll select (0 -> host pll, 1 -> alt PLL, 2 -> per pll) -#define CARFIELD_L2_CLK_SEL_REG_OFFSET 0x9c +#define CARFIELD_L2_CLK_SEL_REG_OFFSET 0x98 #define CARFIELD_L2_CLK_SEL_L2_CLK_SEL_MASK 0x3 #define CARFIELD_L2_CLK_SEL_L2_CLK_SEL_OFFSET 0 #define CARFIELD_L2_CLK_SEL_L2_CLK_SEL_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_L2_CLK_SEL_L2_CLK_SEL_MASK, .index = CARFIELD_L2_CLK_SEL_L2_CLK_SEL_OFFSET }) // Periph Domain clk divider value -#define CARFIELD_PERIPH_CLK_DIV_VALUE_REG_OFFSET 0xa0 +#define CARFIELD_PERIPH_CLK_DIV_VALUE_REG_OFFSET 0x9c #define CARFIELD_PERIPH_CLK_DIV_VALUE_PERIPH_CLK_DIV_VALUE_MASK 0xffffff #define CARFIELD_PERIPH_CLK_DIV_VALUE_PERIPH_CLK_DIV_VALUE_OFFSET 0 #define CARFIELD_PERIPH_CLK_DIV_VALUE_PERIPH_CLK_DIV_VALUE_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_PERIPH_CLK_DIV_VALUE_PERIPH_CLK_DIV_VALUE_MASK, .index = CARFIELD_PERIPH_CLK_DIV_VALUE_PERIPH_CLK_DIV_VALUE_OFFSET }) // Safety Island clk divider value -#define CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_REG_OFFSET 0xa4 +#define CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_REG_OFFSET 0xa0 #define CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_SAFETY_ISLAND_CLK_DIV_VALUE_MASK \ 0xffffff #define CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET \ @@ -207,7 +200,7 @@ extern "C" { ((bitfield_field32_t) { .mask = CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_SAFETY_ISLAND_CLK_DIV_VALUE_MASK, .index = CARFIELD_SAFETY_ISLAND_CLK_DIV_VALUE_SAFETY_ISLAND_CLK_DIV_VALUE_OFFSET }) // Security Island clk divider value -#define CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_REG_OFFSET 0xa8 +#define CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_REG_OFFSET 0xa4 #define CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_SECURITY_ISLAND_CLK_DIV_VALUE_MASK \ 0xffffff #define CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET \ @@ -216,7 +209,7 @@ extern "C" { ((bitfield_field32_t) { .mask = CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_SECURITY_ISLAND_CLK_DIV_VALUE_MASK, .index = CARFIELD_SECURITY_ISLAND_CLK_DIV_VALUE_SECURITY_ISLAND_CLK_DIV_VALUE_OFFSET }) // PULP Cluster clk divider value -#define CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_REG_OFFSET 0xac +#define CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_REG_OFFSET 0xa8 #define CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_PULP_CLUSTER_CLK_DIV_VALUE_MASK \ 0xffffff #define CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET 0 @@ -224,7 +217,7 @@ extern "C" { ((bitfield_field32_t) { .mask = CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_PULP_CLUSTER_CLK_DIV_VALUE_MASK, .index = CARFIELD_PULP_CLUSTER_CLK_DIV_VALUE_PULP_CLUSTER_CLK_DIV_VALUE_OFFSET }) // Spatz Cluster clk divider value -#define CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_REG_OFFSET 0xb0 +#define CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_REG_OFFSET 0xac #define CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_SPATZ_CLUSTER_CLK_DIV_VALUE_MASK \ 0xffffff #define CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET \ @@ -233,74 +226,74 @@ extern "C" { ((bitfield_field32_t) { .mask = CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_SPATZ_CLUSTER_CLK_DIV_VALUE_MASK, .index = CARFIELD_SPATZ_CLUSTER_CLK_DIV_VALUE_SPATZ_CLUSTER_CLK_DIV_VALUE_OFFSET }) // L2 Memory clk divider value -#define CARFIELD_L2_CLK_DIV_VALUE_REG_OFFSET 0xb4 +#define CARFIELD_L2_CLK_DIV_VALUE_REG_OFFSET 0xb0 #define CARFIELD_L2_CLK_DIV_VALUE_L2_CLK_DIV_VALUE_MASK 0xffffff #define CARFIELD_L2_CLK_DIV_VALUE_L2_CLK_DIV_VALUE_OFFSET 0 #define CARFIELD_L2_CLK_DIV_VALUE_L2_CLK_DIV_VALUE_FIELD \ ((bitfield_field32_t) { .mask = CARFIELD_L2_CLK_DIV_VALUE_L2_CLK_DIV_VALUE_MASK, .index = CARFIELD_L2_CLK_DIV_VALUE_L2_CLK_DIV_VALUE_OFFSET }) // Host Domain fetch enable -#define CARFIELD_HOST_FETCH_ENABLE_REG_OFFSET 0xb8 +#define CARFIELD_HOST_FETCH_ENABLE_REG_OFFSET 0xb4 #define CARFIELD_HOST_FETCH_ENABLE_HOST_FETCH_ENABLE_BIT 0 // Safety Island fetch enable -#define CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_REG_OFFSET 0xbc +#define CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_REG_OFFSET 0xb8 #define CARFIELD_SAFETY_ISLAND_FETCH_ENABLE_SAFETY_ISLAND_FETCH_ENABLE_BIT 0 // Security Island fetch enable -#define CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_REG_OFFSET 0xc0 +#define CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_REG_OFFSET 0xbc #define CARFIELD_SECURITY_ISLAND_FETCH_ENABLE_SECURITY_ISLAND_FETCH_ENABLE_BIT 0 // PULP Cluster fetch enable -#define CARFIELD_PULP_CLUSTER_FETCH_ENABLE_REG_OFFSET 0xc4 +#define CARFIELD_PULP_CLUSTER_FETCH_ENABLE_REG_OFFSET 0xc0 #define CARFIELD_PULP_CLUSTER_FETCH_ENABLE_PULP_CLUSTER_FETCH_ENABLE_BIT 0 // Spatz Cluster fetch enable -#define CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_REG_OFFSET 0xc8 +#define CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_REG_OFFSET 0xc4 #define CARFIELD_SPATZ_CLUSTER_FETCH_ENABLE_SPATZ_CLUSTER_FETCH_ENABLE_BIT 0 // Host boot address -#define CARFIELD_HOST_BOOT_ADDR_REG_OFFSET 0xcc +#define CARFIELD_HOST_BOOT_ADDR_REG_OFFSET 0xc8 // Safety Island boot address -#define CARFIELD_SAFETY_ISLAND_BOOT_ADDR_REG_OFFSET 0xd0 +#define CARFIELD_SAFETY_ISLAND_BOOT_ADDR_REG_OFFSET 0xcc // Security Island boot address -#define CARFIELD_SECURITY_ISLAND_BOOT_ADDR_REG_OFFSET 0xd4 +#define CARFIELD_SECURITY_ISLAND_BOOT_ADDR_REG_OFFSET 0xd0 // PULP Cluster boot address -#define CARFIELD_PULP_CLUSTER_BOOT_ADDR_REG_OFFSET 0xd8 +#define CARFIELD_PULP_CLUSTER_BOOT_ADDR_REG_OFFSET 0xd4 // Spatz Cluster boot address -#define CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_REG_OFFSET 0xdc +#define CARFIELD_SPATZ_CLUSTER_BOOT_ADDR_REG_OFFSET 0xd8 // PULP Cluster boot enable -#define CARFIELD_PULP_CLUSTER_BOOT_ENABLE_REG_OFFSET 0xe0 +#define CARFIELD_PULP_CLUSTER_BOOT_ENABLE_REG_OFFSET 0xdc #define CARFIELD_PULP_CLUSTER_BOOT_ENABLE_PULP_CLUSTER_BOOT_ENABLE_BIT 0 // Spatz Cluster busy -#define CARFIELD_SPATZ_CLUSTER_BUSY_REG_OFFSET 0xe4 +#define CARFIELD_SPATZ_CLUSTER_BUSY_REG_OFFSET 0xe0 #define CARFIELD_SPATZ_CLUSTER_BUSY_SPATZ_CLUSTER_BUSY_BIT 0 // PULP Cluster busy -#define CARFIELD_PULP_CLUSTER_BUSY_REG_OFFSET 0xe8 +#define CARFIELD_PULP_CLUSTER_BUSY_REG_OFFSET 0xe4 #define CARFIELD_PULP_CLUSTER_BUSY_PULP_CLUSTER_BUSY_BIT 0 // PULP Cluster end of computation -#define CARFIELD_PULP_CLUSTER_EOC_REG_OFFSET 0xec +#define CARFIELD_PULP_CLUSTER_EOC_REG_OFFSET 0xe8 #define CARFIELD_PULP_CLUSTER_EOC_PULP_CLUSTER_EOC_BIT 0 // L2 RAM cfg pins -margin adjustments- -#define CARFIELD_L2_SRAM_CONFIG0_REG_OFFSET 0xf0 +#define CARFIELD_L2_SRAM_CONFIG0_REG_OFFSET 0xec // L2 RAM cfg pins -margin adjustments- -#define CARFIELD_L2_SRAM_CONFIG1_REG_OFFSET 0xf4 +#define CARFIELD_L2_SRAM_CONFIG1_REG_OFFSET 0xf0 // L2 RAM cfg pins -margin adjustments- -#define CARFIELD_L2_SRAM_CONFIG2_REG_OFFSET 0xf8 +#define CARFIELD_L2_SRAM_CONFIG2_REG_OFFSET 0xf4 // L2 RAM cfg pins -margin adjustments- -#define CARFIELD_L2_SRAM_CONFIG3_REG_OFFSET 0xfc +#define CARFIELD_L2_SRAM_CONFIG3_REG_OFFSET 0xf8 #ifdef __cplusplus } // extern "C" From d03c8314861e9bed43a50638b9b027a6a8203a43 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 22 Jul 2023 19:06:25 +0200 Subject: [PATCH 02/10] hw: Wire missing isolate and isolate status regs --- hw/carfield.sv | 96 ++++++++++++++++++++++++-------------------------- 1 file changed, 47 insertions(+), 49 deletions(-) diff --git a/hw/carfield.sv b/hw/carfield.sv index 161ff9d8..636fade2 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -414,7 +414,7 @@ localparam int unsigned LlcWWidth = (2**LogDepth)* Cfg.AxiUserWidth ); logic hyper_isolate_req, hyper_isolated_rsp; -logic secd_isolate_req; +logic security_island_isolate_req; logic [iomsb(Cfg.AxiExtNumSlv-1):0] slave_isolate_req, slave_isolated_rsp, slave_isolated; logic [iomsb(Cfg.AxiExtNumMst):0] master_isolated_rsp; @@ -752,60 +752,47 @@ carfield_reg_top #( .devmode_i (1'b1) ); -// TODO: these still need to be connected but can't at this point in time since RTL is missing -// car_regs_reg2hw.host_isolate // dummy -// car_regs_reg2hw.periph_isolate - -// car_regs_reg2hw.host_fetch_enable // dummy (?) -// car_regs_reg2hw.spatz_cluster_fetch_enable - -// car_regs_reg2hw.host_boot_addr // dummy (?) -// car_regs_reg2hw.safety_island_boot_addr -// car_regs_reg2hw.security_island_boot_addr -// car_regs_reg2hw.pulp_cluster_boot_addr -// car_regs_reg2hw.spatz_cluster_boot_addr - -// car_regs_reg2hw.l2_sram_config0...x - -// car_regs_hw2reg.host_isolate_status // dummy -// car_regs_hw2reg.periph_isolate_status - - -// Temporary assign -// TODO: add ethernet and hyperbus isolate? -assign hyper_isolate_req = '0; - - -// // Isolate and Isolate status -// -// TODO: Add registers to control missing isolate signals -assign slave_isolate_req[SafetyIslandSlvIdx] = car_regs_reg2hw.safety_island_isolate.q; -assign slave_isolate_req[IntClusterSlvIdx] = car_regs_reg2hw.pulp_cluster_isolate.q; -assign slave_isolate_req[FPClusterSlvIdx] = car_regs_reg2hw.spatz_cluster_isolate.q; -assign slave_isolate_req[L2Port1SlvIdx] = 'd0; -assign slave_isolate_req[L2Port2SlvIdx] = 'd0; -assign slave_isolate_req[EthernetSlvIdx] = 'd0; -assign slave_isolate_req[PeriphsSlvIdx] = 'd0; -// if secure boot is enabled then security island cannot be isolate under any circumstances -// especially at boot time -assign secd_isolate_req = car_regs_reg2hw.security_island_isolate.q && - !secure_boot_i; - -always_comb begin: assign_isolated_responses + +// For islands that connect to Cheshire with a master and a slave AXI port (Safety Island, Integer +// Cluster, FP cluster), we consider the island isolated when the isolation status signals for both +// ports are asserted. + +// For islands that connect to Cheshire with a slave port only (L2 port0, L2 port1, Ethernet, +// Carfield peripherals, Hyperbus), we consider the island isolated when the unique isolation status +// signal is asserted. + +// For islands that connect to Cheshire with a master port only (Security Island), we consider the +// island isolated when the unique isolation status signal is asserted. + +assign slave_isolate_req[SafetyIslandSlvIdx] = car_regs_reg2hw.safety_island_isolate.q; +assign slave_isolate_req[IntClusterSlvIdx] = car_regs_reg2hw.pulp_cluster_isolate.q; +assign slave_isolate_req[FPClusterSlvIdx] = car_regs_reg2hw.spatz_cluster_isolate.q; +// We isolate both L2 AXI ports with a single write to the isolate register in `carfield_reg_top` +assign slave_isolate_req[L2Port0SlvIdx] = car_regs_reg2hw.l2_isolate.q; +assign slave_isolate_req[L2Port1SlvIdx] = car_regs_reg2hw.l2_isolate.q; +// Ethernet isolation follows writes to the peripheral isolate registers in `carfield_reg_top` +assign slave_isolate_req[EthernetSlvIdx] = car_regs_reg2hw.periph_isolate.q; +// Hyperbus isolation follows writes to the peripheral isolate registers in `carfield_reg_top` +assign hyper_isolate_req = car_regs_reg2hw.periph_isolate.q; +assign slave_isolate_req[PeriphsSlvIdx] = car_regs_reg2hw.periph_isolate.q; +assign security_island_isolate_req = car_regs_reg2hw.security_island_isolate.q; + +always_comb begin : gen_assign_isolated_responses slave_isolated = '0; for (int i = 0; i < Cfg.AxiExtNumSlv; i++) begin if (i == SafetyIslandSlvIdx) - slave_isolated [i] = slave_isolated_rsp [i] & master_isolated_rsp [SafetyIslandMstIdx]; + slave_isolated[i] = slave_isolated_rsp[i] & master_isolated_rsp[SafetyIslandMstIdx]; else if (i == IntClusterSlvIdx) - slave_isolated [i] = slave_isolated_rsp [i] & master_isolated_rsp [IntClusterMstIdx]; + slave_isolated[i] = slave_isolated_rsp[i] & master_isolated_rsp[IntClusterMstIdx]; else if (i == FPClusterSlvIdx) - slave_isolated [i] = slave_isolated_rsp [i] & master_isolated_rsp [FPClusterMstIdx]; + slave_isolated[i] = slave_isolated_rsp[i] & master_isolated_rsp[FPClusterMstIdx]; else - slave_isolated [i] = slave_isolated_rsp [i]; + slave_isolated[i] = slave_isolated_rsp[i]; end end +// Safety Island, Integer cluster, FP cluster: master and slave AXI ports assign car_regs_hw2reg.safety_island_isolate_status.d = slave_isolated[SafetyIslandSlvIdx]; assign car_regs_hw2reg.safety_island_isolate_status.de = 1'b1; @@ -815,12 +802,23 @@ assign car_regs_hw2reg.pulp_cluster_isolate_status.de = 1'b1; assign car_regs_hw2reg.spatz_cluster_isolate_status.d = slave_isolated[FPClusterSlvIdx]; assign car_regs_hw2reg.spatz_cluster_isolate_status.de = 1'b1; +// L2 port0, L2 port1, Carfield peripherals +// L2 requires both ports to be isolated before asserting the isolated status +assign car_regs_hw2reg.l2_isolate_status.d = slave_isolated[L2Port0SlvIdx] & + slave_isolated[L2Port1SlvIdx]; +assign car_regs_hw2reg.l2_isolate_status.de = 1'b1; + +// Peripheral isolate status is asserted when peripherals or the hyperbus or ethernet assert their +// isolated status +assign car_regs_hw2reg.periph_isolate_status.d = slave_isolated[PeriphsSlvIdx] | + hyper_isolated_rsp | + slave_isolated[EthernetSlvIdx]; +assign car_regs_hw2reg.periph_isolate_status.de = 1'b1; + // security island only has a master port assign car_regs_hw2reg.security_island_isolate_status.d = master_isolated_rsp[SecurityIslandMstIdx]; assign car_regs_hw2reg.security_island_isolate_status.de = 1'b1; -// TODO: propagate isolated signal from security island to register - // hyperbus reg req/rsp carfield_a32_d32_reg_req_t reg_hyper_req; carfield_a32_d32_reg_rsp_t reg_hyper_rsp; @@ -1614,8 +1612,8 @@ secure_subsystem_synth_wrap #( .async_axi_out_r_data_i ( axi_mst_ext_r_data [SecurityIslandMstIdx] ), .async_axi_out_r_wptr_i ( axi_mst_ext_r_wptr [SecurityIslandMstIdx] ), .async_axi_out_r_rptr_o ( axi_mst_ext_r_rptr [SecurityIslandMstIdx] ), - .axi_isolate_i ( secd_isolate_req ), - .axi_isolated_o ( master_isolated_rsp [SecurityIslandMstIdx] ), + .axi_isolate_i ( security_island_isolate_req ), + .axi_isolated_o ( master_isolated_rsp[SecurityIslandMstIdx] ), // Uart .ibex_uart_rx_i ( uart_ot_rx_i ), .ibex_uart_tx_o ( uart_ot_tx_o ), From c1cd7122b6f94f78fa29a006b6b4055cc6964890 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Sat, 22 Jul 2023 19:07:16 +0200 Subject: [PATCH 03/10] sw/include: Move error codes to utils header --- sw/include/car_util.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/sw/include/car_util.h b/sw/include/car_util.h index 2e1adf5e..c4cc8da6 100644 --- a/sw/include/car_util.h +++ b/sw/include/car_util.h @@ -14,6 +14,21 @@ #include "regs/soc_ctrl.h" #include "io.h" +// execution error codes +#define EHOSTDEXEC 1 // Execution error host domain +#define ESAFEDEXEC 2 // Execution error safe domain +#define EINTCLEXEC 3 // Execution error integer cluster +#define EFPCLEXEC 4 // Execution error floating point cluster +#define EPERIPHEXEC 5 // Execution error peripheral domain +// access error codes +#define EHOSTDNOACCES 6 // Access error in host domain +#define ESAFEDNOACCES 7 // Access error in safe domain +#define EINTCLNOACCES 8 // Access error in integer cluster +#define EFPCLNOACCES 9 // Access error in floating point cluster +#define EPERIPHNOACCES 10 // Access error in peripheral domain + +// Clock and reset control + // for the calculation check safety island top #define SAFETY_ISLAND_BOOT_ADDR_RSVAL (CAR_SAFETY_ISLAND_PERIPHS_BASE_ADDR + 0x1080) From 8c992c3275b326a67924c23eb19de77c61f69851 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Mon, 24 Jul 2023 07:23:57 +0200 Subject: [PATCH 04/10] hw: Align indentation * We have weird indentation (to be reverted in the future), but we should at least try to be consistent with it --- hw/carfield.sv | 60 +++++++++++++++++++++++++------------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/hw/carfield.sv b/hw/carfield.sv index 636fade2..000287ba 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -542,36 +542,36 @@ end // shared_l2_memory (sw reset 5) // Clock Multiplexing for each sub block - localparam int unsigned DomainClkDivValueWidth = 16; - typedef logic [DomainClkDivValueWidth-1:0] domain_clk_div_value_t; - logic [NumDomains-1:0] domain_clk; - logic [NumDomains-1:0] domain_clk_en; - logic [NumDomains-1:0] domain_clk_gated; - logic [NumDomains-1:0][1:0] domain_clk_sel; - - logic [NumDomains-1:0] domain_clk_div_changed; - logic [NumDomains-1:0] domain_clk_div_decoupled_valid, domain_clk_div_decoupled_ready; - domain_clk_div_value_t [NumDomains-1:0] domain_clk_div_value; - domain_clk_div_value_t [NumDomains-1:0] domain_clk_div_value_decoupled; - logic [NumDomains-1:0] domain_clk_div_valid_synced, domain_clk_div_ready_synced; - domain_clk_div_value_t [NumDomains-1:0] domain_clk_div_value_synced; - - // Note that each accelerator has two resets: One for the combined - // software/power-on reset and a power-on reset only - logic [NumDomains-1:0] pwr_on_rsts_n; - logic [NumDomains-1:0] rsts_n; - - - // Each of the 5 clock gateable domains (periph, safety island, security island, spatz and pulp - // cluster) have the following clock distribution scheme: - // 1. For each domain the user selects one of 3 different clock sources (host clock, alt clock and - // per clock). Each of these main clocks are either supplied externally, by a dedicated PLL per - // clock source or by a single PLL that supplies all three clock sources. The configuration of - // the clock source is handled by the external PLL wrapper configuration registers. - // 2. The selected clock source for the domain is fed into a default-bypassed arbitrary integer - // clock divider with 50% duty cycle. This allows to use different integer clock divisions for - // every target domain to use different clock frequencies. - // 3. The internal clock gate of the clock divider is used to provide clock gating for the domain. +localparam int unsigned DomainClkDivValueWidth = 24; +typedef logic [DomainClkDivValueWidth-1:0] domain_clk_div_value_t; +logic [NumDomains-1:0] domain_clk; +logic [NumDomains-1:0] domain_clk_en; +logic [NumDomains-1:0] domain_clk_gated; +logic [NumDomains-1:0][1:0] domain_clk_sel; + +logic [NumDomains-1:0] domain_clk_div_changed; +logic [NumDomains-1:0] domain_clk_div_decoupled_valid, domain_clk_div_decoupled_ready; +domain_clk_div_value_t [NumDomains-1:0] domain_clk_div_value; +domain_clk_div_value_t [NumDomains-1:0] domain_clk_div_value_decoupled; +logic [NumDomains-1:0] domain_clk_div_valid_synced, domain_clk_div_ready_synced; +domain_clk_div_value_t [NumDomains-1:0] domain_clk_div_value_synced; + +// Note that each accelerator has two resets: One for the combined +// software/power-on reset and a power-on reset only +logic [NumDomains-1:0] pwr_on_rsts_n; +logic [NumDomains-1:0] rsts_n; + + +// Each of the 5 clock gateable domains (periph, safety island, security island, spatz and pulp +// cluster) have the following clock distribution scheme: +// 1. For each domain the user selects one of 3 different clock sources (host clock, alt clock and +// per clock). Each of these main clocks are either supplied externally, by a dedicated PLL per +// clock source or by a single PLL that supplies all three clock sources. The configuration of +// the clock source is handled by the external PLL wrapper configuration registers. +// 2. The selected clock source for the domain is fed into a default-bypassed arbitrary integer +// clock divider with 50% duty cycle. This allows to use different integer clock divisions for +// every target domain to use different clock frequencies. +// 3. The internal clock gate of the clock divider is used to provide clock gating for the domain. for (genvar i = 0; i < NumDomains; i++) begin : gen_domain_clock_mux clk_mux_glitch_free #( From 5eb04239edc53186199b4893600adc246c9b9b7a Mon Sep 17 00:00:00 2001 From: aottaviano Date: Mon, 24 Jul 2023 07:28:40 +0200 Subject: [PATCH 05/10] hw: Align HW and SW terminology for L2 ports * Ports were sometimes named 0/1 and other times 1/2 --- hw/carfield_pkg.sv | 24 ++++++++++++------------ hw/l2_wrap.sv | 16 ++++++++-------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index 2b1b1cec..6928ecd2 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -34,8 +34,8 @@ typedef enum int { } carfield_domains_e; typedef enum byte_bt { - L2Port1SlvIdx = 'd0, - L2Port2SlvIdx = 'd1, + L2Port0SlvIdx = 'd0, + L2Port1SlvIdx = 'd1, SafetyIslandSlvIdx = 'd2, EthernetSlvIdx = 'd3, PeriphsSlvIdx = 'd4, @@ -52,8 +52,8 @@ typedef enum byte_bt { } axi_mst_idx_t; typedef enum doub_bt { - L2Port1Base = 'h0000_0000_7800_0000, - L2Port2Base = 'h0000_0000_7820_0000, + L2Port0Base = 'h0000_0000_7800_0000, + L2Port1Base = 'h0000_0000_7820_0000, SafetyIslandBase = 'h0000_0000_6000_0000, EthernetBase = 'h0000_0000_2000_0000, PeriphsBase = 'h0000_0000_2000_1000, @@ -72,8 +72,8 @@ localparam doub_bt FPClusterSize = 'h0000_0000_0080_0000; localparam doub_bt MailboxSize = 'h0000_0000_0000_1000; typedef enum doub_bt { + L2Port0End = L2Port0Base + L2Size, L2Port1End = L2Port1Base + L2Size, - L2Port2End = L2Port2Base + L2Size, SafetyIslandEnd = SafetyIslandBase + SafetyIslandSize, EthernetEnd = EthernetBase + EthernetSize, PeriphsEnd = PeriphsBase + PeriphsSize, @@ -257,24 +257,24 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ PeriphsSlvIdx , EthernetSlvIdx , SafetyIslandSlvIdx, - L2Port2SlvIdx , - L2Port1SlvIdx }, + L2Port1SlvIdx , + L2Port0SlvIdx }, AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxBase , IntClusterBase , FPClusterBase , PeriphsBase , EthernetBase , SafetyIslandBase, - L2Port2Base , - L2Port1Base }, + L2Port1Base , + L2Port0Base }, AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxEnd , IntClusterEnd , FPClusterEnd , PeriphsEnd , EthernetEnd , SafetyIslandEnd, - L2Port2End , - L2Port1End }, + L2Port1End , + L2Port0End }, // External reg slaves (at most 8 ports and rules) RegExtNumSlv : NumTotalRegSlv, RegExtNumRules : NumTotalRegRules, @@ -379,8 +379,8 @@ localparam int unsigned NumL2Ports = 2; localparam int unsigned L2MemSize = 2**20; localparam int unsigned L2NumRules = 4; // 2 rules per each access mode // (interleaved, non-interleaved) +localparam doub_bt L2Port0NonInterlBase = L2Port0Base + L2MemSize; localparam doub_bt L2Port1NonInterlBase = L2Port1Base + L2MemSize; -localparam doub_bt L2Port2NonInterlBase = L2Port2Base + L2MemSize; /****************************/ /* Safety Island Parameters */ diff --git a/hw/l2_wrap.sv b/hw/l2_wrap.sv index ad4740b1..90f6995a 100644 --- a/hw/l2_wrap.sv +++ b/hw/l2_wrap.sv @@ -154,17 +154,17 @@ typedef struct packed { localparam map_rule_t [NumRules-1:0] MappingRules = '{ '{idx : car_l2_pkg::INTERLEAVE , - start_addr: L2Port1Base , - end_addr : L2Port1Base + L2MemSize}, + start_addr: L2Port0Base , + end_addr : L2Port0Base + L2MemSize}, '{idx : car_l2_pkg::NONE_INTER , - start_addr: L2Port1NonInterlBase , - end_addr : L2Port1NonInterlBase + L2MemSize}, + start_addr: L2Port0NonInterlBase , + end_addr : L2Port0NonInterlBase + L2MemSize}, '{idx : car_l2_pkg::INTERLEAVE , - start_addr: L2Port2Base , - end_addr : L2Port2Base + L2MemSize}, + start_addr: L2Port1Base , + end_addr : L2Port1Base + L2MemSize}, '{idx : car_l2_pkg::NONE_INTER , - start_addr: L2Port2NonInterlBase , - end_addr : L2Port2NonInterlBase + L2MemSize} + start_addr: L2Port1NonInterlBase , + end_addr : L2Port1NonInterlBase + L2MemSize} }; car_l2_top #( From b15406bf8562f2e2fe8a3f3d7162165da075849e Mon Sep 17 00:00:00 2001 From: aottaviano Date: Mon, 24 Jul 2023 07:31:29 +0200 Subject: [PATCH 06/10] hw: Connect L2 ECC error interrupt --- hw/carfield.sv | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/carfield.sv b/hw/carfield.sv index 000287ba..061778ad 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -839,17 +839,20 @@ carfield_axi_slv_rsp_t axi_mbox_rsp; // Host Clock Domain // Interrupts -logic [CarfieldNumExtIntrs-1:0] chs_ext_intrs; -logic [IntClusterNumEoc-1:0] pulpcl_eoc; +logic [CarfieldNumExtIntrs-1:0] chs_ext_intrs; +logic [IntClusterNumEoc-1:0] pulpcl_eoc; +logic l2_ecc_err; // Edge-triggered interrupts from a different clock domain than cheshire (host clock domain) have // been synchronized already. Synchronization of level-sensitive interrupts is handled within the // module, before or inside the interrupt controller. assign chs_ext_intrs = { // tie unused to 0 - {(CarfieldNumExtIntrs-21){1'b0}}, + {(CarfieldNumExtIntrs-22){1'b0}}, // System peripherals car_periph_intrs, // 16 + // L2 ECC + l2_ecc_err, // 1 // Mailboxes secd_hostd_mbox_intr, // 1 safed_hostd_mbox_intr, // 1 @@ -1140,7 +1143,6 @@ hyperbus_wrap #( // Reconfigurable L2 Memory // Host Clock Domain -logic l2_ecc_err; l2_wrap #( .NumPort ( NumL2Ports ), From 1d6bcc5d01943dceb0c4df0a962eb669ccc3fd58 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Mon, 24 Jul 2023 07:36:02 +0200 Subject: [PATCH 07/10] sw: Remove dummy value for L2 isolate register --- sw/include/car_util.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sw/include/car_util.h b/sw/include/car_util.h index c4cc8da6..62f5afb1 100644 --- a/sw/include/car_util.h +++ b/sw/include/car_util.h @@ -62,10 +62,6 @@ enum car_rst { CAR_L2_RST = 5, }; -// these do not exist so we set a dummy value -#define CARFIELD_L2_ISOLATE_REG_OFFSET -1 -#define CARFIELD_L2_ISOLATE_STATUS_REG_OFFSET -1 - #define CARFIELD_HOST_CLK_EN_REG_OFFSET -1 #define CARFIELD_HOST_CLK_SEL_REG_OFFSET -1 #define CARFIELD_HOST_CLK_DIV_VALUE_REG_OFFSET -1 From 751afc3622e33bff3a5f29b4f309803733cbf753 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Mon, 24 Jul 2023 07:36:38 +0200 Subject: [PATCH 08/10] sw/tests: Extend SW reset basic test --- sw/tests/bare-metal/hostd/sw_rst_seq.c | 51 ++++++++++++++------------ 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/sw/tests/bare-metal/hostd/sw_rst_seq.c b/sw/tests/bare-metal/hostd/sw_rst_seq.c index 4045a1f9..e66f0e67 100644 --- a/sw/tests/bare-metal/hostd/sw_rst_seq.c +++ b/sw/tests/bare-metal/hostd/sw_rst_seq.c @@ -5,13 +5,8 @@ // Robert Balas // Alessandro Ottaviano -// basic testing of warm resets - -// Safety Island OK -// Spatz OK -// PULP cluster Hangs -// Security Island Hangs -// Peripherals Hangs +// Basic testing of warm resets. This test is executed only from LLC/SPM since it tests SW reset on +// shared L2 and hyperbus memory controller. #include #include "params.h" @@ -34,44 +29,52 @@ int main(void) // Write a pattern to safety island boot addr writew(magic, CAR_SAFETY_ISLAND_PERIPHS_BASE_ADDR + - SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET); + SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET); // Double check if (readw(CAR_SAFETY_ISLAND_PERIPHS_BASE_ADDR + - SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET) != magic) - return 2; + SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET) != magic) + return ESAFEDNOACCES; // engage reset sequence for safety island car_reset_domain(CAR_SAFETY_RST); // After the reset we should only see zeros if (readw(CAR_SAFETY_ISLAND_PERIPHS_BASE_ADDR + - SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET) != - SAFETY_ISLAND_BOOT_ADDR_RSVAL) - return 3; + SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET) != + SAFETY_ISLAND_BOOT_ADDR_RSVAL) + return ESAFEDNOACCES; // Spatz writew(magic, CAR_FP_CLUSTER_PERIPHS_BASE_ADDR + - SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET); + SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET); if (readw(CAR_FP_CLUSTER_PERIPHS_BASE_ADDR + - SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET) != - magic) - return 4; + SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET) != + magic) + return EFPCLNOACCES; car_reset_domain(CAR_SPATZ_RST); if (readw(CAR_FP_CLUSTER_PERIPHS_BASE_ADDR + - SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET) != 0) - return 5; + SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_REG_OFFSET) != 0) + return EFPCLNOACCES; // PULP Reset - // car_reset_domain(CAR_PULP_RST); + writew(magic, CAR_INT_CLUSTER_BOOT_ADDR_REG); + if (readw(CAR_INT_CLUSTER_BOOT_ADDR_REG) != magic) + return EINTCLNOACCES; + + volatile uint32_t pulp_boot_addr_rst_value = 0x78200000; + car_reset_domain(CAR_PULP_RST); + if (readw(CAR_INT_CLUSTER_BOOT_ADDR_REG) != pulp_boot_addr_rst_value) + return EINTCLNOACCES; - // Periph Reset - // car_reset_domain(CAR_PERIPH_RST); + // L2 Reset + // Memory doesn't have a reset so this needs to be checked manually + car_reset_domain(CAR_L2_RST); // Security Island - // We can't access anything no way to check if the reset worked - // car_reset_domain(CAR_SECURITY_RST); + // We can't access anything so this needs to be checked manually + car_reset_domain(CAR_SECURITY_RST); return 0; } From ec4be8dccb7743278c380bbc48b460abd2f90354 Mon Sep 17 00:00:00 2001 From: aottaviano Date: Wed, 23 Aug 2023 14:04:45 +0200 Subject: [PATCH 09/10] carfield.mk: Update nonfree pointer --- carfield.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/carfield.mk b/carfield.mk index c19991f8..2889f775 100644 --- a/carfield.mk +++ b/carfield.mk @@ -94,7 +94,7 @@ endif ###################### CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git -CAR_NONFREE_COMMIT ?= b25a18bce74df67bbd5e0fe3b56aab62aa2befd8 +CAR_NONFREE_COMMIT ?= 0bd54b6d992594847c76a546b3c9b7357567b39c ## Clone the non-free verification IP for the Carfield TB car-nonfree-init: From 1db0e34c59ed47ec6321fd65309f0549dd717ecb Mon Sep 17 00:00:00 2001 From: aottaviano Date: Thu, 24 Aug 2023 09:32:06 +0200 Subject: [PATCH 10/10] carfield.mk: Add mibench init to car-init target --- carfield.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/carfield.mk b/carfield.mk index 2889f775..1ab14214 100644 --- a/carfield.mk +++ b/carfield.mk @@ -266,7 +266,7 @@ car-sw-build: chs-sw-build safed-sw-build pulpd-sw-build car-sw-all .PHONY: car-init ## Shortcut to initialize carfield with all the targets described above. -car-init: car-checkout car-hw-init car-sim-init safed-sw-init pulpd-sw-init +car-init: car-checkout car-hw-init car-sim-init safed-sw-init pulpd-sw-init mibench # Initialize and build SW for the Islands .PHONY: safed-sw-init pulpd-sw-init