diff --git a/Bender.lock b/Bender.lock index b08779bb..f380b3b4 100644 --- a/Bender.lock +++ b/Bender.lock @@ -43,6 +43,15 @@ packages: - axi - common_cells - common_verification + axi_rt: + revision: b243310dd33b31e4e2ca5229aac20df25cfc45d5 + version: 0.0.0-alpha + source: + Git: https://github.com/pulp-platform/axi_rt.git + dependencies: + - axi + - common_cells + - register_interface axi_vga: revision: 07be187d1e954d8090031b32d236ad76dc62ce45 version: 0.1.1 @@ -108,8 +117,8 @@ packages: dependencies: - common_cells idma: - revision: 2c64e0773fab5a54757646715485fcdf3432c7c1 - version: 0.5.0 + revision: ca1b28816a3706be0bf9ce01378246d5346384f0 + version: 0.5.1 source: Git: https://github.com/pulp-platform/iDMA.git dependencies: @@ -136,8 +145,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: 3b2bf592100b769977c76e51812c55cd742882f6 - version: 0.4.1 + revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c + version: 0.4.2 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: @@ -163,8 +172,8 @@ packages: - common_cells - register_interface tech_cells_generic: - revision: 298b7297d220ba2601d0f24f684f97ff32f61123 - version: 0.2.12 + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 source: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: diff --git a/Bender.yml b/Bender.yml index c9a5c7a4..b072d9b0 100644 --- a/Bender.yml +++ b/Bender.yml @@ -16,6 +16,7 @@ dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 } axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 } axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 } + axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha } axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 } clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 } @@ -23,7 +24,7 @@ dependencies: cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v0.4.3 } iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.0 } opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 } - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 } serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 } clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 } @@ -34,12 +35,9 @@ export_include_dirs: - hw/include sources: - - hw/future/axi_to_reg_v2.sv - hw/bootrom/cheshire_bootrom.sv - hw/regs/cheshire_reg_pkg.sv - hw/regs/cheshire_reg_top.sv - - hw/regs/axi_rt_reg_pkg.sv - - hw/regs/axi_rt_reg_top.sv - hw/cheshire_pkg.sv - hw/cheshire_soc.sv diff --git a/cheshire.mk b/cheshire.mk index afbfcc48..15936a6c 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -20,6 +20,7 @@ CHS_LLC_DIR := $(shell $(BENDER) path axi_llc) # Define paths used in dependencies OTPROOT := $(shell $(BENDER) path opentitan_peripherals) CLINTROOT := $(shell $(BENDER) path clint) +AXIRTROOT := $(shell $(BENDER) path axi_rt) AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga) IDMA_ROOT := $(shell $(BENDER) path idma) @@ -74,10 +75,6 @@ include $(CHS_ROOT)/sw/sw.mk $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv: $(CHS_ROOT)/hw/regs/cheshire_regs.hjson $(REGTOOL) -r $< --outdir $(dir $@) -# AXI RT registers -$(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv: $(CHS_ROOT)/hw/regs/axi_rt_regs.hjson - $(REGTOOL) -r $< --outdir $(dir $@) - # CLINT CLINTCORES ?= 1 include $(CLINTROOT)/clint.mk @@ -89,6 +86,13 @@ include $(OTPROOT)/otp.mk $(OTPROOT)/.generated: $(CHS_ROOT)/hw/rv_plic.cfg.hjson flock -x $@ sh -c "cp $< $(dir $@)/src/rv_plic/; $(MAKE) -j1 otp" && touch $@ +# AXI RT +AXIRT_NUM_MGRS ?= 8 +AXIRT_NUM_SUBS ?= 2 +include $(AXIRTROOT)/axirt.mk +$(AXIRTROOT)/.generated: axirt_regs + touch $@ + # AXI VGA include $(AXI_VGA_ROOT)/axi_vga.mk $(AXI_VGA_ROOT)/.generated: @@ -100,9 +104,9 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs && touch $@ CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv -CHS_HW_ALL += $(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv CHS_HW_ALL += $(CLINTROOT)/.generated CHS_HW_ALL += $(OTPROOT)/.generated +CHS_HW_ALL += $(AXIRTROOT)/.generated CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated @@ -129,7 +133,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo ############## $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: Bender.yml - $(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 --vlog-arg="$(VLOG_ARGS)" > $@ + $(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@ echo 'vlog "$(CURDIR)/$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ $(CHS_ROOT)/target/sim/models: diff --git a/docs/um/arch.md b/docs/um/arch.md index 83829bbc..f8f6ae19 100644 --- a/docs/um/arch.md +++ b/docs/um/arch.md @@ -41,6 +41,8 @@ Cheshire's internal memory map is *static*. While device instantiation and layou | | CLINT | `0x0204_0000` | 256K | | | +-------------------+---------------+------+-------+ | | IRQ router | `0x0208_0000` | 256K | | +| +-------------------+---------------+------+-------+ +| | AXI RT (Cfg) | `0x020C_0000` | 256K | | +--------------------+-------------------+---------------+------+-------+ | 4K periphs @ Reg | SoC Regs | `0x0300_0000` | 4K | | | +-------------------+---------------+------+-------+ @@ -58,9 +60,7 @@ Cheshire's internal memory map is *static*. While device instantiation and layou | +-------------------+---------------+------+-------+ | | VGA (Cfg) | `0x0300_7000` | 4K | | | +-------------------+---------------+------+-------+ -| | AXI RT (Cfg) | `0x0300_8000` | 4K | | -| +-------------------+---------------+------+-------+ -| | UNBENT | `0x0300_9000` | 4K | | +| | UNBENT | `0x0300_8000` | 4K | | +--------------------+-------------------+---------------+------+-------+ | INTCs @ Reg | PLIC | `0x0400_0000` | 64M | | | +-------------------+---------------+------+-------+ diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv index 028fdb2e..0b46c6db 100644 --- a/hw/cheshire_pkg.sv +++ b/hw/cheshire_pkg.sv @@ -180,8 +180,10 @@ package cheshire_pkg; // Parameters for GPIO bit GpioInputSyncs; // Parameters for AXI RT - word_bt AxiRtNumPending; - word_bt AxiRtWBufferDepth; + aw_bt AxiRtNumPending; + dw_bt AxiRtWBufferDepth; + aw_bt AxiRtNumAddrRegions; + bit AxiRtCutPaths; } cheshire_cfg_t; ////////////////// @@ -263,7 +265,7 @@ package cheshire_pkg; localparam doub_bt AmRegs = 'h0300_0000; localparam doub_bt AmLlc = 'h0300_1000; localparam doub_bt AmSlink = 'h0300_6000; - localparam doub_bt AmBusErr = 'h0300_9000; + localparam doub_bt AmBusErr = 'h0300_8000; localparam doub_bt AmSpm = 'h1000_0000; // Cached region at bottom, uncached on top localparam doub_bt AmClic = 'h0800_0000; @@ -400,8 +402,8 @@ package cheshire_pkg; if (cfg.Gpio) begin i++; ret.gpio = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end - if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end + if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin i++; ret.clic[j] = i; r++; ret.map[r] = '{i, AmClic + j*'h40000, AmClic + (j+1)*'h40000}; end @@ -539,7 +541,7 @@ package cheshire_pkg; Dma : 1, SerialLink : 1, Vga : 1, - AxiRt : 0, + AxiRt : 1, Clic : 0, IrqRouter : 0, BusErr : 1, @@ -590,8 +592,10 @@ package cheshire_pkg; // GPIOs GpioInputSyncs : 1, // AXI RT - AxiRtNumPending : 16, - AxiRtWBufferDepth : 16, + AxiRtNumPending : 16, + AxiRtWBufferDepth : 16, + AxiRtNumAddrRegions : 2, + AxiRtCutPaths : 1, // All non-set values should be zero default: '0 }; diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index b631db66..03566135 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -1095,86 +1095,45 @@ module cheshire_soc import cheshire_pkg::*; #( if (Cfg.AxiRt) begin : gen_axi_rt - // Connect AXI RT units, one for each master - axi_rt_reg_pkg::axi_rt_hw2reg_t axi_rt_hw2reg; - axi_rt_reg_pkg::axi_rt_reg2hw_t axi_rt_reg2hw; - - // Rule type - typedef struct packed { - logic [0:0] idx; - addr_t start_addr; - addr_t end_addr; - } rt_rule_t; - - localparam rt_rule_t [0:0] RtAddrmap = '{ - '{ idx: 8'h00, start_addr: '0, end_addr: '1 } - }; - - for (genvar i = 0; i < AxiIn.num_in; i++) begin : gen_axi_rt_units - axi_rt_unit #( - .AddrWidth ( Cfg.AddrWidth ), - .DataWidth ( Cfg.AxiDataWidth ), - .IdWidth ( Cfg.AxiMstIdWidth ), - .UserWidth ( Cfg.AxiUserWidth ), - .NumPending ( Cfg.AxiRtNumPending ), - .WBufferDepth ( Cfg.AxiRtWBufferDepth ), - .NumAddrRegions ( 1 ), - .NumRules ( 1 ), - .PeriodWidth ( 32 ), - .BudgetWidth ( 32 ), - .rt_rule_t ( rt_rule_t ), - .addr_t ( addr_t ), - .aw_chan_t ( axi_mst_aw_chan_t ), - .w_chan_t ( axi_mst_w_chan_t ), - .axi_req_t ( axi_mst_req_t ), - .axi_resp_t ( axi_mst_rsp_t ) - ) i_axi_rt_unit ( - .clk_i, - .rst_ni, - .slv_req_i ( axi_in_req [i] ), - .slv_resp_o ( axi_in_rsp [i] ), - .mst_req_o ( axi_rt_in_req [i] ), - .mst_resp_i ( axi_rt_in_rsp [i] ), - .rt_enable_i ( axi_rt_reg2hw.rt_enable [i] ), - .rt_bypassed_o ( axi_rt_hw2reg.rt_bypassed [i] ), - .len_limit_i ( axi_rt_reg2hw.len_limit [i] ), - .num_w_pending_o ( ), - .num_aw_pending_o ( ), - .rt_rule_i ( RtAddrmap ), - .w_decode_error_o ( ), - .r_decode_error_o ( ), - .imtu_enable_i ( axi_rt_reg2hw.imtu_enable [i] ), - .imtu_abort_i ( axi_rt_reg2hw.imtu_abort [i] ), - .w_budget_i ( axi_rt_reg2hw.write_budget [i] ), - .w_budget_left_o ( axi_rt_hw2reg.write_budget_left [i] ), - .w_period_i ( axi_rt_reg2hw.write_period [i] ), - .w_period_left_o ( axi_rt_hw2reg.write_period_left [i] ), - .r_budget_i ( axi_rt_reg2hw.read_budget [i] ), - .r_budget_left_o ( axi_rt_hw2reg.read_budget_left [i] ), - .r_period_i ( axi_rt_reg2hw.read_period [i] ), - .r_period_left_o ( axi_rt_hw2reg.read_period_left [i] ), - .isolate_o ( axi_rt_hw2reg.isolate [i] ), - .isolated_o ( axi_rt_hw2reg.isolated [i] ) - ); - end - - axi_rt_reg_top #( - .reg_req_t ( reg_req_t ), - .reg_rsp_t ( reg_rsp_t ) - ) i_axi_rt_regs ( + axi_rt_unit_top #( + .NumManagers ( AxiIn.num_in ), + .AddrWidth ( Cfg.AddrWidth ), + .DataWidth ( Cfg.AxiDataWidth ), + .IdWidth ( Cfg.AxiMstIdWidth ), + .UserWidth ( Cfg.AxiUserWidth ), + .NumPending ( Cfg.AxiRtNumPending ), + .WBufferDepth ( Cfg.AxiRtWBufferDepth ), + .NumAddrRegions ( Cfg.AxiRtNumAddrRegions ), + .PeriodWidth ( 32'd32 ), + .BudgetWidth ( 32'd32 ), + .RegIdWidth ( AxiSlvIdWidth ), + .CutSplitterPaths ( Cfg.AxiRtCutPaths ), + .CutDecErrors ( 1'b0 ), + .aw_chan_t ( axi_mst_aw_chan_t ), + .w_chan_t ( axi_mst_w_chan_t ), + .b_chan_t ( axi_mst_b_chan_t ), + .ar_chan_t ( axi_mst_ar_chan_t ), + .r_chan_t ( axi_mst_r_chan_t ), + .axi_req_t ( axi_mst_req_t ), + .axi_resp_t ( axi_mst_rsp_t ), + .req_req_t ( reg_req_t ), + .req_rsp_t ( reg_rsp_t ) + ) i_axi_rt_unit_top ( .clk_i, .rst_ni, + .slv_req_i ( axi_in_req ), + .slv_resp_o ( axi_in_rsp ), + .mst_req_o ( axi_rt_in_req ), + .mst_resp_i ( axi_rt_in_rsp ), .reg_req_i ( reg_out_req[RegOut.axirt] ), .reg_rsp_o ( reg_out_rsp[RegOut.axirt] ), - .hw2reg ( axi_rt_hw2reg ), - .reg2hw ( axi_rt_reg2hw ), - .devmode_i ( 1'b1 ) + .reg_id_i ( reg_id ) ); end else begin : gen_no_axi_rt - assign axi_rt_in_req = axi_in_req; - assign axi_in_rsp = axi_rt_in_rsp; + assign axi_rt_in_req = axi_in_req; + assign axi_in_rsp = axi_rt_in_rsp; end diff --git a/hw/future/axi_to_reg_v2.sv b/hw/future/axi_to_reg_v2.sv deleted file mode 100644 index 6ba723d8..00000000 --- a/hw/future/axi_to_reg_v2.sv +++ /dev/null @@ -1,170 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Thomas Benz - -`include "axi/typedef.svh" - -/// Version 2 of a protocol converter from AXI4 to the register interface. -/// AXI Data Width >= Reg Data Width -module axi_to_reg_v2 #( - /// The width of the address. - parameter int unsigned AxiAddrWidth = 32'd0, - /// The width of the data. - parameter int unsigned AxiDataWidth = 32'd0, - /// The width of the id. - parameter int unsigned AxiIdWidth = 32'd0, - /// The width of the user signal. - parameter int unsigned AxiUserWidth = 32'd0, - /// The data width of the Reg bus - parameter int unsigned RegDataWidth = 32'd0, - /// AXI request struct type. - parameter type axi_req_t = logic, - /// AXI response struct type. - parameter type axi_rsp_t = logic, - /// Regbus request struct type. - parameter type reg_req_t = logic, - /// Regbus response struct type. - parameter type reg_rsp_t = logic, - /// Dependent parameter: ID Width - parameter type id_t = logic[AxiIdWidth-1:0] -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t axi_req_i, - output axi_rsp_t axi_rsp_o, - output reg_req_t reg_req_o, - input reg_rsp_t reg_rsp_i, - output id_t reg_id_o, - output logic busy_o -); - - // how many times is the AXI bus wider than the regbus? - localparam int unsigned NumBanks = AxiDataWidth / RegDataWidth; - - localparam type addr_t = logic [AxiAddrWidth-1 :0]; - localparam type reg_data_t = logic [RegDataWidth-1 :0]; - localparam type reg_strb_t = logic [RegDataWidth/8-1:0]; - - // TCDM BUS - logic [NumBanks-1:0] mem_req; - logic [NumBanks-1:0] mem_gnt; - addr_t [NumBanks-1:0] mem_addr; - reg_data_t [NumBanks-1:0] mem_wdata; - reg_strb_t [NumBanks-1:0] mem_strb; - logic [NumBanks-1:0] mem_we; - id_t [NumBanks-1:0] mem_id; - logic [NumBanks-1:0] mem_rvalid; - reg_data_t [NumBanks-1:0] mem_rdata; - logic [NumBanks-1:0] mem_err; - - // sub reg buses - reg_req_t [NumBanks-1:0] reg_req, valid_req, zero_w_req; - reg_rsp_t [NumBanks-1:0] reg_rsp, valid_rsp, zero_w_rsp; - - // convert to TCDM first - axi_to_detailed_mem #( - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_rsp_t ), - .AddrWidth ( AxiAddrWidth ), - .DataWidth ( AxiDataWidth ), - .IdWidth ( AxiIdWidth ), - .UserWidth ( AxiUserWidth ), - .NumBanks ( NumBanks ), - .BufDepth ( 32'd1 ), - .HideStrb ( 1'b0 ), - .OutFifoDepth ( 32'd1 ) - ) i_axi_to_detailed_mem ( - .clk_i, - .rst_ni, - .busy_o, - .axi_req_i, - .axi_resp_o ( axi_rsp_o ), - .mem_req_o ( mem_req ), - .mem_gnt_i ( mem_gnt ), - .mem_addr_o ( mem_addr ), - .mem_wdata_o ( mem_wdata ), - .mem_strb_o ( mem_strb ), - .mem_atop_o ( /* NOT CONNECTED */ ), - .mem_lock_o ( /* NOT CONNECTED */ ), - .mem_we_o ( mem_we ), - .mem_id_o ( mem_id ), - .mem_user_o ( /* NOT CONNECTED */ ), - .mem_cache_o ( /* NOT CONNECTED */ ), - .mem_prot_o ( /* NOT CONNECTED */ ), - .mem_qos_o ( /* NOT CONNECTED */ ), - .mem_region_o ( /* NOT CONNECTED */ ), - .mem_rvalid_i ( mem_rvalid ), - .mem_rdata_i ( mem_rdata ), - .mem_err_i ( mem_err ), - .mem_exokay_i ( '0 ) - ); - - // every subbus is converted independently - for (genvar i = 0; i < NumBanks; i++) begin : gen_tcdm_to_reg - periph_to_reg #( - .AW ( AxiAddrWidth ), - .DW ( RegDataWidth ), - .IW ( AxiIdWidth ), - .req_t ( reg_req_t ), - .rsp_t ( reg_rsp_t ) - ) i_periph_to_reg ( - .clk_i, - .rst_ni, - .req_i ( mem_req [i] ), - .add_i ( mem_addr [i] ), - .wen_i ( !mem_we [i] ), - .wdata_i ( mem_wdata [i] ), - .be_i ( mem_strb [i] ), - .id_i ( '0 ), - .gnt_o ( mem_gnt [i] ), - .r_rdata_o ( mem_rdata [i] ), - .r_opc_o ( mem_err [i] ), - .r_id_o ( /* NOT CONNECTED */ ), - .r_valid_o ( mem_rvalid [i] ), - .reg_req_o ( reg_req [i] ), - .reg_rsp_i ( reg_rsp [i] ) - ); - - // filter zero strobe writes early, directly ack them - reg_demux #( - .NoPorts ( 32'd2 ), - .req_t ( reg_req_t ), - .rsp_t ( reg_rsp_t ) - ) i_reg_demux ( - .clk_i, - .rst_ni, - .in_select_i ( reg_req[i].write & (reg_req[i].wstrb == '0) ), - .in_req_i ( reg_req[i] ), - .in_rsp_o ( reg_rsp[i] ), - .out_req_o ( {zero_w_req[i], valid_req[i]} ), - .out_rsp_i ( {zero_w_rsp[i], valid_rsp[i]} ) - ); - - // ack zero strobe writes here - assign zero_w_rsp[i].ready = 1'b1; - assign zero_w_rsp[i].error = 1'b0; - assign zero_w_rsp[i].rdata = '0; - end - - // arbitrate over valid accesses in sub buses - reg_mux #( - .NoPorts( NumBanks ), - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .req_t ( reg_req_t ), - .rsp_t ( reg_rsp_t ) - ) i_reg_mux ( - .clk_i, - .rst_ni, - .in_req_i ( valid_req ), - .in_rsp_o ( valid_rsp ), - .out_req_o ( reg_req_o ), - .out_rsp_i ( reg_rsp_i ) - ); - - // forward the id, all banks carry the same ID here - assign reg_id_o = mem_id[0]; - -endmodule diff --git a/hw/regs/axi_rt_reg_pkg.sv b/hw/regs/axi_rt_reg_pkg.sv deleted file mode 100644 index aca38220..00000000 --- a/hw/regs/axi_rt_reg_pkg.sv +++ /dev/null @@ -1,922 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Package auto-generated by `reggen` containing data structure - -package axi_rt_reg_pkg; - - // Param list - parameter int NumMst = 24; - - // Address widths within the block - parameter int BlockAw = 10; - - //////////////////////////// - // Typedefs for registers // - //////////////////////////// - - typedef struct packed { - logic q; - } axi_rt_reg2hw_rt_enable_mreg_t; - - typedef struct packed { - logic [7:0] q; - } axi_rt_reg2hw_len_limit_mreg_t; - - typedef struct packed { - logic q; - } axi_rt_reg2hw_imtu_enable_mreg_t; - - typedef struct packed { - logic q; - } axi_rt_reg2hw_imtu_abort_mreg_t; - - typedef struct packed { - logic [31:0] q; - } axi_rt_reg2hw_write_budget_mreg_t; - - typedef struct packed { - logic [31:0] q; - } axi_rt_reg2hw_read_budget_mreg_t; - - typedef struct packed { - logic [31:0] q; - } axi_rt_reg2hw_write_period_mreg_t; - - typedef struct packed { - logic [31:0] q; - } axi_rt_reg2hw_read_period_mreg_t; - - typedef struct packed { - logic d; - } axi_rt_hw2reg_rt_bypassed_mreg_t; - - typedef struct packed { - logic [31:0] d; - } axi_rt_hw2reg_write_budget_left_mreg_t; - - typedef struct packed { - logic [31:0] d; - } axi_rt_hw2reg_read_budget_left_mreg_t; - - typedef struct packed { - logic [31:0] d; - } axi_rt_hw2reg_write_period_left_mreg_t; - - typedef struct packed { - logic [31:0] d; - } axi_rt_hw2reg_read_period_left_mreg_t; - - typedef struct packed { - logic d; - } axi_rt_hw2reg_isolate_mreg_t; - - typedef struct packed { - logic d; - } axi_rt_hw2reg_isolated_mreg_t; - - // Register -> HW type - typedef struct packed { - axi_rt_reg2hw_rt_enable_mreg_t [23:0] rt_enable; // [3335:3312] - axi_rt_reg2hw_len_limit_mreg_t [23:0] len_limit; // [3311:3120] - axi_rt_reg2hw_imtu_enable_mreg_t [23:0] imtu_enable; // [3119:3096] - axi_rt_reg2hw_imtu_abort_mreg_t [23:0] imtu_abort; // [3095:3072] - axi_rt_reg2hw_write_budget_mreg_t [23:0] write_budget; // [3071:2304] - axi_rt_reg2hw_read_budget_mreg_t [23:0] read_budget; // [2303:1536] - axi_rt_reg2hw_write_period_mreg_t [23:0] write_period; // [1535:768] - axi_rt_reg2hw_read_period_mreg_t [23:0] read_period; // [767:0] - } axi_rt_reg2hw_t; - - // HW -> register type - typedef struct packed { - axi_rt_hw2reg_rt_bypassed_mreg_t [23:0] rt_bypassed; // [3143:3120] - axi_rt_hw2reg_write_budget_left_mreg_t [23:0] write_budget_left; // [3119:2352] - axi_rt_hw2reg_read_budget_left_mreg_t [23:0] read_budget_left; // [2351:1584] - axi_rt_hw2reg_write_period_left_mreg_t [23:0] write_period_left; // [1583:816] - axi_rt_hw2reg_read_period_left_mreg_t [23:0] read_period_left; // [815:48] - axi_rt_hw2reg_isolate_mreg_t [23:0] isolate; // [47:24] - axi_rt_hw2reg_isolated_mreg_t [23:0] isolated; // [23:0] - } axi_rt_hw2reg_t; - - // Register offsets - parameter logic [BlockAw-1:0] AXI_RT_RT_ENABLE_OFFSET = 10'h 0; - parameter logic [BlockAw-1:0] AXI_RT_RT_BYPASSED_OFFSET = 10'h 4; - parameter logic [BlockAw-1:0] AXI_RT_LEN_LIMIT_0_OFFSET = 10'h 8; - parameter logic [BlockAw-1:0] AXI_RT_LEN_LIMIT_1_OFFSET = 10'h c; - parameter logic [BlockAw-1:0] AXI_RT_LEN_LIMIT_2_OFFSET = 10'h 10; - parameter logic [BlockAw-1:0] AXI_RT_LEN_LIMIT_3_OFFSET = 10'h 14; - parameter logic [BlockAw-1:0] AXI_RT_LEN_LIMIT_4_OFFSET = 10'h 18; - parameter logic [BlockAw-1:0] AXI_RT_LEN_LIMIT_5_OFFSET = 10'h 1c; - parameter logic [BlockAw-1:0] AXI_RT_IMTU_ENABLE_OFFSET = 10'h 20; - parameter logic [BlockAw-1:0] AXI_RT_IMTU_ABORT_OFFSET = 10'h 24; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_0_OFFSET = 10'h 28; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_1_OFFSET = 10'h 2c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_2_OFFSET = 10'h 30; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_3_OFFSET = 10'h 34; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_4_OFFSET = 10'h 38; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_5_OFFSET = 10'h 3c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_6_OFFSET = 10'h 40; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_7_OFFSET = 10'h 44; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_8_OFFSET = 10'h 48; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_9_OFFSET = 10'h 4c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_10_OFFSET = 10'h 50; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_11_OFFSET = 10'h 54; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_12_OFFSET = 10'h 58; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_13_OFFSET = 10'h 5c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_14_OFFSET = 10'h 60; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_15_OFFSET = 10'h 64; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_16_OFFSET = 10'h 68; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_17_OFFSET = 10'h 6c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_18_OFFSET = 10'h 70; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_19_OFFSET = 10'h 74; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_20_OFFSET = 10'h 78; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_21_OFFSET = 10'h 7c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_22_OFFSET = 10'h 80; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_23_OFFSET = 10'h 84; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_0_OFFSET = 10'h 88; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_1_OFFSET = 10'h 8c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_2_OFFSET = 10'h 90; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_3_OFFSET = 10'h 94; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_4_OFFSET = 10'h 98; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_5_OFFSET = 10'h 9c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_6_OFFSET = 10'h a0; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_7_OFFSET = 10'h a4; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_8_OFFSET = 10'h a8; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_9_OFFSET = 10'h ac; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_10_OFFSET = 10'h b0; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_11_OFFSET = 10'h b4; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_12_OFFSET = 10'h b8; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_13_OFFSET = 10'h bc; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_14_OFFSET = 10'h c0; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_15_OFFSET = 10'h c4; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_16_OFFSET = 10'h c8; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_17_OFFSET = 10'h cc; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_18_OFFSET = 10'h d0; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_19_OFFSET = 10'h d4; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_20_OFFSET = 10'h d8; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_21_OFFSET = 10'h dc; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_22_OFFSET = 10'h e0; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_23_OFFSET = 10'h e4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_0_OFFSET = 10'h e8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_1_OFFSET = 10'h ec; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_2_OFFSET = 10'h f0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_3_OFFSET = 10'h f4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_4_OFFSET = 10'h f8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_5_OFFSET = 10'h fc; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_6_OFFSET = 10'h 100; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_7_OFFSET = 10'h 104; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_8_OFFSET = 10'h 108; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_9_OFFSET = 10'h 10c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_10_OFFSET = 10'h 110; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_11_OFFSET = 10'h 114; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_12_OFFSET = 10'h 118; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_13_OFFSET = 10'h 11c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_14_OFFSET = 10'h 120; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_15_OFFSET = 10'h 124; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_16_OFFSET = 10'h 128; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_17_OFFSET = 10'h 12c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_18_OFFSET = 10'h 130; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_19_OFFSET = 10'h 134; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_20_OFFSET = 10'h 138; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_21_OFFSET = 10'h 13c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_22_OFFSET = 10'h 140; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_23_OFFSET = 10'h 144; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_0_OFFSET = 10'h 148; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_1_OFFSET = 10'h 14c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_2_OFFSET = 10'h 150; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_3_OFFSET = 10'h 154; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_4_OFFSET = 10'h 158; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_5_OFFSET = 10'h 15c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_6_OFFSET = 10'h 160; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_7_OFFSET = 10'h 164; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_8_OFFSET = 10'h 168; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_9_OFFSET = 10'h 16c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_10_OFFSET = 10'h 170; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_11_OFFSET = 10'h 174; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_12_OFFSET = 10'h 178; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_13_OFFSET = 10'h 17c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_14_OFFSET = 10'h 180; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_15_OFFSET = 10'h 184; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_16_OFFSET = 10'h 188; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_17_OFFSET = 10'h 18c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_18_OFFSET = 10'h 190; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_19_OFFSET = 10'h 194; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_20_OFFSET = 10'h 198; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_21_OFFSET = 10'h 19c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_22_OFFSET = 10'h 1a0; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_23_OFFSET = 10'h 1a4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_0_OFFSET = 10'h 1a8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_1_OFFSET = 10'h 1ac; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_2_OFFSET = 10'h 1b0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_3_OFFSET = 10'h 1b4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_4_OFFSET = 10'h 1b8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_5_OFFSET = 10'h 1bc; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_6_OFFSET = 10'h 1c0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_7_OFFSET = 10'h 1c4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_8_OFFSET = 10'h 1c8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_9_OFFSET = 10'h 1cc; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_10_OFFSET = 10'h 1d0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_11_OFFSET = 10'h 1d4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_12_OFFSET = 10'h 1d8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_13_OFFSET = 10'h 1dc; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_14_OFFSET = 10'h 1e0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_15_OFFSET = 10'h 1e4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_16_OFFSET = 10'h 1e8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_17_OFFSET = 10'h 1ec; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_18_OFFSET = 10'h 1f0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_19_OFFSET = 10'h 1f4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_20_OFFSET = 10'h 1f8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_21_OFFSET = 10'h 1fc; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_22_OFFSET = 10'h 200; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_BUDGET_LEFT_23_OFFSET = 10'h 204; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_0_OFFSET = 10'h 208; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_1_OFFSET = 10'h 20c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_2_OFFSET = 10'h 210; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_3_OFFSET = 10'h 214; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_4_OFFSET = 10'h 218; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_5_OFFSET = 10'h 21c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_6_OFFSET = 10'h 220; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_7_OFFSET = 10'h 224; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_8_OFFSET = 10'h 228; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_9_OFFSET = 10'h 22c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_10_OFFSET = 10'h 230; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_11_OFFSET = 10'h 234; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_12_OFFSET = 10'h 238; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_13_OFFSET = 10'h 23c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_14_OFFSET = 10'h 240; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_15_OFFSET = 10'h 244; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_16_OFFSET = 10'h 248; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_17_OFFSET = 10'h 24c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_18_OFFSET = 10'h 250; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_19_OFFSET = 10'h 254; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_20_OFFSET = 10'h 258; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_21_OFFSET = 10'h 25c; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_22_OFFSET = 10'h 260; - parameter logic [BlockAw-1:0] AXI_RT_READ_BUDGET_LEFT_23_OFFSET = 10'h 264; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_0_OFFSET = 10'h 268; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_1_OFFSET = 10'h 26c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_2_OFFSET = 10'h 270; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_3_OFFSET = 10'h 274; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_4_OFFSET = 10'h 278; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_5_OFFSET = 10'h 27c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_6_OFFSET = 10'h 280; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_7_OFFSET = 10'h 284; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_8_OFFSET = 10'h 288; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_9_OFFSET = 10'h 28c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_10_OFFSET = 10'h 290; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_11_OFFSET = 10'h 294; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_12_OFFSET = 10'h 298; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_13_OFFSET = 10'h 29c; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_14_OFFSET = 10'h 2a0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_15_OFFSET = 10'h 2a4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_16_OFFSET = 10'h 2a8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_17_OFFSET = 10'h 2ac; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_18_OFFSET = 10'h 2b0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_19_OFFSET = 10'h 2b4; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_20_OFFSET = 10'h 2b8; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_21_OFFSET = 10'h 2bc; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_22_OFFSET = 10'h 2c0; - parameter logic [BlockAw-1:0] AXI_RT_WRITE_PERIOD_LEFT_23_OFFSET = 10'h 2c4; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_0_OFFSET = 10'h 2c8; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_1_OFFSET = 10'h 2cc; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_2_OFFSET = 10'h 2d0; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_3_OFFSET = 10'h 2d4; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_4_OFFSET = 10'h 2d8; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_5_OFFSET = 10'h 2dc; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_6_OFFSET = 10'h 2e0; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_7_OFFSET = 10'h 2e4; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_8_OFFSET = 10'h 2e8; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_9_OFFSET = 10'h 2ec; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_10_OFFSET = 10'h 2f0; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_11_OFFSET = 10'h 2f4; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_12_OFFSET = 10'h 2f8; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_13_OFFSET = 10'h 2fc; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_14_OFFSET = 10'h 300; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_15_OFFSET = 10'h 304; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_16_OFFSET = 10'h 308; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_17_OFFSET = 10'h 30c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_18_OFFSET = 10'h 310; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_19_OFFSET = 10'h 314; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_20_OFFSET = 10'h 318; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_21_OFFSET = 10'h 31c; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_22_OFFSET = 10'h 320; - parameter logic [BlockAw-1:0] AXI_RT_READ_PERIOD_LEFT_23_OFFSET = 10'h 324; - parameter logic [BlockAw-1:0] AXI_RT_ISOLATE_OFFSET = 10'h 328; - parameter logic [BlockAw-1:0] AXI_RT_ISOLATED_OFFSET = 10'h 32c; - - // Reset values for hwext registers and their fields - parameter logic [23:0] AXI_RT_RT_BYPASSED_RESVAL = 24'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_0_WRITE_BUDGET_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_1_WRITE_BUDGET_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_2_WRITE_BUDGET_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_3_WRITE_BUDGET_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_4_WRITE_BUDGET_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_5_WRITE_BUDGET_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_6_WRITE_BUDGET_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_7_WRITE_BUDGET_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_8_WRITE_BUDGET_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_9_WRITE_BUDGET_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_10_WRITE_BUDGET_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_11_WRITE_BUDGET_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_12_WRITE_BUDGET_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_13_WRITE_BUDGET_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_14_WRITE_BUDGET_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_15_WRITE_BUDGET_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_16_WRITE_BUDGET_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_17_WRITE_BUDGET_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_18_WRITE_BUDGET_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_19_WRITE_BUDGET_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_20_WRITE_BUDGET_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_21_WRITE_BUDGET_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_22_WRITE_BUDGET_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_BUDGET_LEFT_23_WRITE_BUDGET_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_0_READ_BUDGET_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_1_READ_BUDGET_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_2_READ_BUDGET_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_3_READ_BUDGET_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_4_READ_BUDGET_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_5_READ_BUDGET_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_6_READ_BUDGET_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_7_READ_BUDGET_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_8_READ_BUDGET_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_9_READ_BUDGET_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_10_READ_BUDGET_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_11_READ_BUDGET_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_12_READ_BUDGET_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_13_READ_BUDGET_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_14_READ_BUDGET_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_15_READ_BUDGET_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_16_READ_BUDGET_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_17_READ_BUDGET_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_18_READ_BUDGET_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_19_READ_BUDGET_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_20_READ_BUDGET_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_21_READ_BUDGET_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_22_READ_BUDGET_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_BUDGET_LEFT_23_READ_BUDGET_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_0_WRITE_PERIOD_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_1_WRITE_PERIOD_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_2_WRITE_PERIOD_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_3_WRITE_PERIOD_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_4_WRITE_PERIOD_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_5_WRITE_PERIOD_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_6_WRITE_PERIOD_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_7_WRITE_PERIOD_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_8_WRITE_PERIOD_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_9_WRITE_PERIOD_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_10_WRITE_PERIOD_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_11_WRITE_PERIOD_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_12_WRITE_PERIOD_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_13_WRITE_PERIOD_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_14_WRITE_PERIOD_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_15_WRITE_PERIOD_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_16_WRITE_PERIOD_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_17_WRITE_PERIOD_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_18_WRITE_PERIOD_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_19_WRITE_PERIOD_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_20_WRITE_PERIOD_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_21_WRITE_PERIOD_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_22_WRITE_PERIOD_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_WRITE_PERIOD_LEFT_23_WRITE_PERIOD_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_0_READ_PERIOD_LEFT_0_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_1_READ_PERIOD_LEFT_1_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_2_READ_PERIOD_LEFT_2_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_3_READ_PERIOD_LEFT_3_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_4_READ_PERIOD_LEFT_4_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_5_READ_PERIOD_LEFT_5_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_6_READ_PERIOD_LEFT_6_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_7_READ_PERIOD_LEFT_7_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_8_READ_PERIOD_LEFT_8_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_9_READ_PERIOD_LEFT_9_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_10_READ_PERIOD_LEFT_10_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_11_READ_PERIOD_LEFT_11_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_12_READ_PERIOD_LEFT_12_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_13_READ_PERIOD_LEFT_13_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_14_READ_PERIOD_LEFT_14_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_15_READ_PERIOD_LEFT_15_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_16_READ_PERIOD_LEFT_16_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_17_READ_PERIOD_LEFT_17_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_18_READ_PERIOD_LEFT_18_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_19_READ_PERIOD_LEFT_19_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_20_READ_PERIOD_LEFT_20_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_21_READ_PERIOD_LEFT_21_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_22_READ_PERIOD_LEFT_22_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_23_RESVAL = 32'h 0; - parameter logic [31:0] AXI_RT_READ_PERIOD_LEFT_23_READ_PERIOD_LEFT_23_RESVAL = 32'h 0; - parameter logic [23:0] AXI_RT_ISOLATE_RESVAL = 24'h 0; - parameter logic [23:0] AXI_RT_ISOLATED_RESVAL = 24'h 0; - - // Register index - typedef enum int { - AXI_RT_RT_ENABLE, - AXI_RT_RT_BYPASSED, - AXI_RT_LEN_LIMIT_0, - AXI_RT_LEN_LIMIT_1, - AXI_RT_LEN_LIMIT_2, - AXI_RT_LEN_LIMIT_3, - AXI_RT_LEN_LIMIT_4, - AXI_RT_LEN_LIMIT_5, - AXI_RT_IMTU_ENABLE, - AXI_RT_IMTU_ABORT, - AXI_RT_WRITE_BUDGET_0, - AXI_RT_WRITE_BUDGET_1, - AXI_RT_WRITE_BUDGET_2, - AXI_RT_WRITE_BUDGET_3, - AXI_RT_WRITE_BUDGET_4, - AXI_RT_WRITE_BUDGET_5, - AXI_RT_WRITE_BUDGET_6, - AXI_RT_WRITE_BUDGET_7, - AXI_RT_WRITE_BUDGET_8, - AXI_RT_WRITE_BUDGET_9, - AXI_RT_WRITE_BUDGET_10, - AXI_RT_WRITE_BUDGET_11, - AXI_RT_WRITE_BUDGET_12, - AXI_RT_WRITE_BUDGET_13, - AXI_RT_WRITE_BUDGET_14, - AXI_RT_WRITE_BUDGET_15, - AXI_RT_WRITE_BUDGET_16, - AXI_RT_WRITE_BUDGET_17, - AXI_RT_WRITE_BUDGET_18, - AXI_RT_WRITE_BUDGET_19, - AXI_RT_WRITE_BUDGET_20, - AXI_RT_WRITE_BUDGET_21, - AXI_RT_WRITE_BUDGET_22, - AXI_RT_WRITE_BUDGET_23, - AXI_RT_READ_BUDGET_0, - AXI_RT_READ_BUDGET_1, - AXI_RT_READ_BUDGET_2, - AXI_RT_READ_BUDGET_3, - AXI_RT_READ_BUDGET_4, - AXI_RT_READ_BUDGET_5, - AXI_RT_READ_BUDGET_6, - AXI_RT_READ_BUDGET_7, - AXI_RT_READ_BUDGET_8, - AXI_RT_READ_BUDGET_9, - AXI_RT_READ_BUDGET_10, - AXI_RT_READ_BUDGET_11, - AXI_RT_READ_BUDGET_12, - AXI_RT_READ_BUDGET_13, - AXI_RT_READ_BUDGET_14, - AXI_RT_READ_BUDGET_15, - AXI_RT_READ_BUDGET_16, - AXI_RT_READ_BUDGET_17, - AXI_RT_READ_BUDGET_18, - AXI_RT_READ_BUDGET_19, - AXI_RT_READ_BUDGET_20, - AXI_RT_READ_BUDGET_21, - AXI_RT_READ_BUDGET_22, - AXI_RT_READ_BUDGET_23, - AXI_RT_WRITE_PERIOD_0, - AXI_RT_WRITE_PERIOD_1, - AXI_RT_WRITE_PERIOD_2, - AXI_RT_WRITE_PERIOD_3, - AXI_RT_WRITE_PERIOD_4, - AXI_RT_WRITE_PERIOD_5, - AXI_RT_WRITE_PERIOD_6, - AXI_RT_WRITE_PERIOD_7, - AXI_RT_WRITE_PERIOD_8, - AXI_RT_WRITE_PERIOD_9, - AXI_RT_WRITE_PERIOD_10, - AXI_RT_WRITE_PERIOD_11, - AXI_RT_WRITE_PERIOD_12, - AXI_RT_WRITE_PERIOD_13, - AXI_RT_WRITE_PERIOD_14, - AXI_RT_WRITE_PERIOD_15, - AXI_RT_WRITE_PERIOD_16, - AXI_RT_WRITE_PERIOD_17, - AXI_RT_WRITE_PERIOD_18, - AXI_RT_WRITE_PERIOD_19, - AXI_RT_WRITE_PERIOD_20, - AXI_RT_WRITE_PERIOD_21, - AXI_RT_WRITE_PERIOD_22, - AXI_RT_WRITE_PERIOD_23, - AXI_RT_READ_PERIOD_0, - AXI_RT_READ_PERIOD_1, - AXI_RT_READ_PERIOD_2, - AXI_RT_READ_PERIOD_3, - AXI_RT_READ_PERIOD_4, - AXI_RT_READ_PERIOD_5, - AXI_RT_READ_PERIOD_6, - AXI_RT_READ_PERIOD_7, - AXI_RT_READ_PERIOD_8, - AXI_RT_READ_PERIOD_9, - AXI_RT_READ_PERIOD_10, - AXI_RT_READ_PERIOD_11, - AXI_RT_READ_PERIOD_12, - AXI_RT_READ_PERIOD_13, - AXI_RT_READ_PERIOD_14, - AXI_RT_READ_PERIOD_15, - AXI_RT_READ_PERIOD_16, - AXI_RT_READ_PERIOD_17, - AXI_RT_READ_PERIOD_18, - AXI_RT_READ_PERIOD_19, - AXI_RT_READ_PERIOD_20, - AXI_RT_READ_PERIOD_21, - AXI_RT_READ_PERIOD_22, - AXI_RT_READ_PERIOD_23, - AXI_RT_WRITE_BUDGET_LEFT_0, - AXI_RT_WRITE_BUDGET_LEFT_1, - AXI_RT_WRITE_BUDGET_LEFT_2, - AXI_RT_WRITE_BUDGET_LEFT_3, - AXI_RT_WRITE_BUDGET_LEFT_4, - AXI_RT_WRITE_BUDGET_LEFT_5, - AXI_RT_WRITE_BUDGET_LEFT_6, - AXI_RT_WRITE_BUDGET_LEFT_7, - AXI_RT_WRITE_BUDGET_LEFT_8, - AXI_RT_WRITE_BUDGET_LEFT_9, - AXI_RT_WRITE_BUDGET_LEFT_10, - AXI_RT_WRITE_BUDGET_LEFT_11, - AXI_RT_WRITE_BUDGET_LEFT_12, - AXI_RT_WRITE_BUDGET_LEFT_13, - AXI_RT_WRITE_BUDGET_LEFT_14, - AXI_RT_WRITE_BUDGET_LEFT_15, - AXI_RT_WRITE_BUDGET_LEFT_16, - AXI_RT_WRITE_BUDGET_LEFT_17, - AXI_RT_WRITE_BUDGET_LEFT_18, - AXI_RT_WRITE_BUDGET_LEFT_19, - AXI_RT_WRITE_BUDGET_LEFT_20, - AXI_RT_WRITE_BUDGET_LEFT_21, - AXI_RT_WRITE_BUDGET_LEFT_22, - AXI_RT_WRITE_BUDGET_LEFT_23, - AXI_RT_READ_BUDGET_LEFT_0, - AXI_RT_READ_BUDGET_LEFT_1, - AXI_RT_READ_BUDGET_LEFT_2, - AXI_RT_READ_BUDGET_LEFT_3, - AXI_RT_READ_BUDGET_LEFT_4, - AXI_RT_READ_BUDGET_LEFT_5, - AXI_RT_READ_BUDGET_LEFT_6, - AXI_RT_READ_BUDGET_LEFT_7, - AXI_RT_READ_BUDGET_LEFT_8, - AXI_RT_READ_BUDGET_LEFT_9, - AXI_RT_READ_BUDGET_LEFT_10, - AXI_RT_READ_BUDGET_LEFT_11, - AXI_RT_READ_BUDGET_LEFT_12, - AXI_RT_READ_BUDGET_LEFT_13, - AXI_RT_READ_BUDGET_LEFT_14, - AXI_RT_READ_BUDGET_LEFT_15, - AXI_RT_READ_BUDGET_LEFT_16, - AXI_RT_READ_BUDGET_LEFT_17, - AXI_RT_READ_BUDGET_LEFT_18, - AXI_RT_READ_BUDGET_LEFT_19, - AXI_RT_READ_BUDGET_LEFT_20, - AXI_RT_READ_BUDGET_LEFT_21, - AXI_RT_READ_BUDGET_LEFT_22, - AXI_RT_READ_BUDGET_LEFT_23, - AXI_RT_WRITE_PERIOD_LEFT_0, - AXI_RT_WRITE_PERIOD_LEFT_1, - AXI_RT_WRITE_PERIOD_LEFT_2, - AXI_RT_WRITE_PERIOD_LEFT_3, - AXI_RT_WRITE_PERIOD_LEFT_4, - AXI_RT_WRITE_PERIOD_LEFT_5, - AXI_RT_WRITE_PERIOD_LEFT_6, - AXI_RT_WRITE_PERIOD_LEFT_7, - AXI_RT_WRITE_PERIOD_LEFT_8, - AXI_RT_WRITE_PERIOD_LEFT_9, - AXI_RT_WRITE_PERIOD_LEFT_10, - AXI_RT_WRITE_PERIOD_LEFT_11, - AXI_RT_WRITE_PERIOD_LEFT_12, - AXI_RT_WRITE_PERIOD_LEFT_13, - AXI_RT_WRITE_PERIOD_LEFT_14, - AXI_RT_WRITE_PERIOD_LEFT_15, - AXI_RT_WRITE_PERIOD_LEFT_16, - AXI_RT_WRITE_PERIOD_LEFT_17, - AXI_RT_WRITE_PERIOD_LEFT_18, - AXI_RT_WRITE_PERIOD_LEFT_19, - AXI_RT_WRITE_PERIOD_LEFT_20, - AXI_RT_WRITE_PERIOD_LEFT_21, - AXI_RT_WRITE_PERIOD_LEFT_22, - AXI_RT_WRITE_PERIOD_LEFT_23, - AXI_RT_READ_PERIOD_LEFT_0, - AXI_RT_READ_PERIOD_LEFT_1, - AXI_RT_READ_PERIOD_LEFT_2, - AXI_RT_READ_PERIOD_LEFT_3, - AXI_RT_READ_PERIOD_LEFT_4, - AXI_RT_READ_PERIOD_LEFT_5, - AXI_RT_READ_PERIOD_LEFT_6, - AXI_RT_READ_PERIOD_LEFT_7, - AXI_RT_READ_PERIOD_LEFT_8, - AXI_RT_READ_PERIOD_LEFT_9, - AXI_RT_READ_PERIOD_LEFT_10, - AXI_RT_READ_PERIOD_LEFT_11, - AXI_RT_READ_PERIOD_LEFT_12, - AXI_RT_READ_PERIOD_LEFT_13, - AXI_RT_READ_PERIOD_LEFT_14, - AXI_RT_READ_PERIOD_LEFT_15, - AXI_RT_READ_PERIOD_LEFT_16, - AXI_RT_READ_PERIOD_LEFT_17, - AXI_RT_READ_PERIOD_LEFT_18, - AXI_RT_READ_PERIOD_LEFT_19, - AXI_RT_READ_PERIOD_LEFT_20, - AXI_RT_READ_PERIOD_LEFT_21, - AXI_RT_READ_PERIOD_LEFT_22, - AXI_RT_READ_PERIOD_LEFT_23, - AXI_RT_ISOLATE, - AXI_RT_ISOLATED - } axi_rt_id_e; - - // Register width information to check illegal writes - parameter logic [3:0] AXI_RT_PERMIT [204] = '{ - 4'b 0111, // index[ 0] AXI_RT_RT_ENABLE - 4'b 0111, // index[ 1] AXI_RT_RT_BYPASSED - 4'b 1111, // index[ 2] AXI_RT_LEN_LIMIT_0 - 4'b 1111, // index[ 3] AXI_RT_LEN_LIMIT_1 - 4'b 1111, // index[ 4] AXI_RT_LEN_LIMIT_2 - 4'b 1111, // index[ 5] AXI_RT_LEN_LIMIT_3 - 4'b 1111, // index[ 6] AXI_RT_LEN_LIMIT_4 - 4'b 1111, // index[ 7] AXI_RT_LEN_LIMIT_5 - 4'b 0111, // index[ 8] AXI_RT_IMTU_ENABLE - 4'b 0111, // index[ 9] AXI_RT_IMTU_ABORT - 4'b 1111, // index[ 10] AXI_RT_WRITE_BUDGET_0 - 4'b 1111, // index[ 11] AXI_RT_WRITE_BUDGET_1 - 4'b 1111, // index[ 12] AXI_RT_WRITE_BUDGET_2 - 4'b 1111, // index[ 13] AXI_RT_WRITE_BUDGET_3 - 4'b 1111, // index[ 14] AXI_RT_WRITE_BUDGET_4 - 4'b 1111, // index[ 15] AXI_RT_WRITE_BUDGET_5 - 4'b 1111, // index[ 16] AXI_RT_WRITE_BUDGET_6 - 4'b 1111, // index[ 17] AXI_RT_WRITE_BUDGET_7 - 4'b 1111, // index[ 18] AXI_RT_WRITE_BUDGET_8 - 4'b 1111, // index[ 19] AXI_RT_WRITE_BUDGET_9 - 4'b 1111, // index[ 20] AXI_RT_WRITE_BUDGET_10 - 4'b 1111, // index[ 21] AXI_RT_WRITE_BUDGET_11 - 4'b 1111, // index[ 22] AXI_RT_WRITE_BUDGET_12 - 4'b 1111, // index[ 23] AXI_RT_WRITE_BUDGET_13 - 4'b 1111, // index[ 24] AXI_RT_WRITE_BUDGET_14 - 4'b 1111, // index[ 25] AXI_RT_WRITE_BUDGET_15 - 4'b 1111, // index[ 26] AXI_RT_WRITE_BUDGET_16 - 4'b 1111, // index[ 27] AXI_RT_WRITE_BUDGET_17 - 4'b 1111, // index[ 28] AXI_RT_WRITE_BUDGET_18 - 4'b 1111, // index[ 29] AXI_RT_WRITE_BUDGET_19 - 4'b 1111, // index[ 30] AXI_RT_WRITE_BUDGET_20 - 4'b 1111, // index[ 31] AXI_RT_WRITE_BUDGET_21 - 4'b 1111, // index[ 32] AXI_RT_WRITE_BUDGET_22 - 4'b 1111, // index[ 33] AXI_RT_WRITE_BUDGET_23 - 4'b 1111, // index[ 34] AXI_RT_READ_BUDGET_0 - 4'b 1111, // index[ 35] AXI_RT_READ_BUDGET_1 - 4'b 1111, // index[ 36] AXI_RT_READ_BUDGET_2 - 4'b 1111, // index[ 37] AXI_RT_READ_BUDGET_3 - 4'b 1111, // index[ 38] AXI_RT_READ_BUDGET_4 - 4'b 1111, // index[ 39] AXI_RT_READ_BUDGET_5 - 4'b 1111, // index[ 40] AXI_RT_READ_BUDGET_6 - 4'b 1111, // index[ 41] AXI_RT_READ_BUDGET_7 - 4'b 1111, // index[ 42] AXI_RT_READ_BUDGET_8 - 4'b 1111, // index[ 43] AXI_RT_READ_BUDGET_9 - 4'b 1111, // index[ 44] AXI_RT_READ_BUDGET_10 - 4'b 1111, // index[ 45] AXI_RT_READ_BUDGET_11 - 4'b 1111, // index[ 46] AXI_RT_READ_BUDGET_12 - 4'b 1111, // index[ 47] AXI_RT_READ_BUDGET_13 - 4'b 1111, // index[ 48] AXI_RT_READ_BUDGET_14 - 4'b 1111, // index[ 49] AXI_RT_READ_BUDGET_15 - 4'b 1111, // index[ 50] AXI_RT_READ_BUDGET_16 - 4'b 1111, // index[ 51] AXI_RT_READ_BUDGET_17 - 4'b 1111, // index[ 52] AXI_RT_READ_BUDGET_18 - 4'b 1111, // index[ 53] AXI_RT_READ_BUDGET_19 - 4'b 1111, // index[ 54] AXI_RT_READ_BUDGET_20 - 4'b 1111, // index[ 55] AXI_RT_READ_BUDGET_21 - 4'b 1111, // index[ 56] AXI_RT_READ_BUDGET_22 - 4'b 1111, // index[ 57] AXI_RT_READ_BUDGET_23 - 4'b 1111, // index[ 58] AXI_RT_WRITE_PERIOD_0 - 4'b 1111, // index[ 59] AXI_RT_WRITE_PERIOD_1 - 4'b 1111, // index[ 60] AXI_RT_WRITE_PERIOD_2 - 4'b 1111, // index[ 61] AXI_RT_WRITE_PERIOD_3 - 4'b 1111, // index[ 62] AXI_RT_WRITE_PERIOD_4 - 4'b 1111, // index[ 63] AXI_RT_WRITE_PERIOD_5 - 4'b 1111, // index[ 64] AXI_RT_WRITE_PERIOD_6 - 4'b 1111, // index[ 65] AXI_RT_WRITE_PERIOD_7 - 4'b 1111, // index[ 66] AXI_RT_WRITE_PERIOD_8 - 4'b 1111, // index[ 67] AXI_RT_WRITE_PERIOD_9 - 4'b 1111, // index[ 68] AXI_RT_WRITE_PERIOD_10 - 4'b 1111, // index[ 69] AXI_RT_WRITE_PERIOD_11 - 4'b 1111, // index[ 70] AXI_RT_WRITE_PERIOD_12 - 4'b 1111, // index[ 71] AXI_RT_WRITE_PERIOD_13 - 4'b 1111, // index[ 72] AXI_RT_WRITE_PERIOD_14 - 4'b 1111, // index[ 73] AXI_RT_WRITE_PERIOD_15 - 4'b 1111, // index[ 74] AXI_RT_WRITE_PERIOD_16 - 4'b 1111, // index[ 75] AXI_RT_WRITE_PERIOD_17 - 4'b 1111, // index[ 76] AXI_RT_WRITE_PERIOD_18 - 4'b 1111, // index[ 77] AXI_RT_WRITE_PERIOD_19 - 4'b 1111, // index[ 78] AXI_RT_WRITE_PERIOD_20 - 4'b 1111, // index[ 79] AXI_RT_WRITE_PERIOD_21 - 4'b 1111, // index[ 80] AXI_RT_WRITE_PERIOD_22 - 4'b 1111, // index[ 81] AXI_RT_WRITE_PERIOD_23 - 4'b 1111, // index[ 82] AXI_RT_READ_PERIOD_0 - 4'b 1111, // index[ 83] AXI_RT_READ_PERIOD_1 - 4'b 1111, // index[ 84] AXI_RT_READ_PERIOD_2 - 4'b 1111, // index[ 85] AXI_RT_READ_PERIOD_3 - 4'b 1111, // index[ 86] AXI_RT_READ_PERIOD_4 - 4'b 1111, // index[ 87] AXI_RT_READ_PERIOD_5 - 4'b 1111, // index[ 88] AXI_RT_READ_PERIOD_6 - 4'b 1111, // index[ 89] AXI_RT_READ_PERIOD_7 - 4'b 1111, // index[ 90] AXI_RT_READ_PERIOD_8 - 4'b 1111, // index[ 91] AXI_RT_READ_PERIOD_9 - 4'b 1111, // index[ 92] AXI_RT_READ_PERIOD_10 - 4'b 1111, // index[ 93] AXI_RT_READ_PERIOD_11 - 4'b 1111, // index[ 94] AXI_RT_READ_PERIOD_12 - 4'b 1111, // index[ 95] AXI_RT_READ_PERIOD_13 - 4'b 1111, // index[ 96] AXI_RT_READ_PERIOD_14 - 4'b 1111, // index[ 97] AXI_RT_READ_PERIOD_15 - 4'b 1111, // index[ 98] AXI_RT_READ_PERIOD_16 - 4'b 1111, // index[ 99] AXI_RT_READ_PERIOD_17 - 4'b 1111, // index[100] AXI_RT_READ_PERIOD_18 - 4'b 1111, // index[101] AXI_RT_READ_PERIOD_19 - 4'b 1111, // index[102] AXI_RT_READ_PERIOD_20 - 4'b 1111, // index[103] AXI_RT_READ_PERIOD_21 - 4'b 1111, // index[104] AXI_RT_READ_PERIOD_22 - 4'b 1111, // index[105] AXI_RT_READ_PERIOD_23 - 4'b 1111, // index[106] AXI_RT_WRITE_BUDGET_LEFT_0 - 4'b 1111, // index[107] AXI_RT_WRITE_BUDGET_LEFT_1 - 4'b 1111, // index[108] AXI_RT_WRITE_BUDGET_LEFT_2 - 4'b 1111, // index[109] AXI_RT_WRITE_BUDGET_LEFT_3 - 4'b 1111, // index[110] AXI_RT_WRITE_BUDGET_LEFT_4 - 4'b 1111, // index[111] AXI_RT_WRITE_BUDGET_LEFT_5 - 4'b 1111, // index[112] AXI_RT_WRITE_BUDGET_LEFT_6 - 4'b 1111, // index[113] AXI_RT_WRITE_BUDGET_LEFT_7 - 4'b 1111, // index[114] AXI_RT_WRITE_BUDGET_LEFT_8 - 4'b 1111, // index[115] AXI_RT_WRITE_BUDGET_LEFT_9 - 4'b 1111, // index[116] AXI_RT_WRITE_BUDGET_LEFT_10 - 4'b 1111, // index[117] AXI_RT_WRITE_BUDGET_LEFT_11 - 4'b 1111, // index[118] AXI_RT_WRITE_BUDGET_LEFT_12 - 4'b 1111, // index[119] AXI_RT_WRITE_BUDGET_LEFT_13 - 4'b 1111, // index[120] AXI_RT_WRITE_BUDGET_LEFT_14 - 4'b 1111, // index[121] AXI_RT_WRITE_BUDGET_LEFT_15 - 4'b 1111, // index[122] AXI_RT_WRITE_BUDGET_LEFT_16 - 4'b 1111, // index[123] AXI_RT_WRITE_BUDGET_LEFT_17 - 4'b 1111, // index[124] AXI_RT_WRITE_BUDGET_LEFT_18 - 4'b 1111, // index[125] AXI_RT_WRITE_BUDGET_LEFT_19 - 4'b 1111, // index[126] AXI_RT_WRITE_BUDGET_LEFT_20 - 4'b 1111, // index[127] AXI_RT_WRITE_BUDGET_LEFT_21 - 4'b 1111, // index[128] AXI_RT_WRITE_BUDGET_LEFT_22 - 4'b 1111, // index[129] AXI_RT_WRITE_BUDGET_LEFT_23 - 4'b 1111, // index[130] AXI_RT_READ_BUDGET_LEFT_0 - 4'b 1111, // index[131] AXI_RT_READ_BUDGET_LEFT_1 - 4'b 1111, // index[132] AXI_RT_READ_BUDGET_LEFT_2 - 4'b 1111, // index[133] AXI_RT_READ_BUDGET_LEFT_3 - 4'b 1111, // index[134] AXI_RT_READ_BUDGET_LEFT_4 - 4'b 1111, // index[135] AXI_RT_READ_BUDGET_LEFT_5 - 4'b 1111, // index[136] AXI_RT_READ_BUDGET_LEFT_6 - 4'b 1111, // index[137] AXI_RT_READ_BUDGET_LEFT_7 - 4'b 1111, // index[138] AXI_RT_READ_BUDGET_LEFT_8 - 4'b 1111, // index[139] AXI_RT_READ_BUDGET_LEFT_9 - 4'b 1111, // index[140] AXI_RT_READ_BUDGET_LEFT_10 - 4'b 1111, // index[141] AXI_RT_READ_BUDGET_LEFT_11 - 4'b 1111, // index[142] AXI_RT_READ_BUDGET_LEFT_12 - 4'b 1111, // index[143] AXI_RT_READ_BUDGET_LEFT_13 - 4'b 1111, // index[144] AXI_RT_READ_BUDGET_LEFT_14 - 4'b 1111, // index[145] AXI_RT_READ_BUDGET_LEFT_15 - 4'b 1111, // index[146] AXI_RT_READ_BUDGET_LEFT_16 - 4'b 1111, // index[147] AXI_RT_READ_BUDGET_LEFT_17 - 4'b 1111, // index[148] AXI_RT_READ_BUDGET_LEFT_18 - 4'b 1111, // index[149] AXI_RT_READ_BUDGET_LEFT_19 - 4'b 1111, // index[150] AXI_RT_READ_BUDGET_LEFT_20 - 4'b 1111, // index[151] AXI_RT_READ_BUDGET_LEFT_21 - 4'b 1111, // index[152] AXI_RT_READ_BUDGET_LEFT_22 - 4'b 1111, // index[153] AXI_RT_READ_BUDGET_LEFT_23 - 4'b 1111, // index[154] AXI_RT_WRITE_PERIOD_LEFT_0 - 4'b 1111, // index[155] AXI_RT_WRITE_PERIOD_LEFT_1 - 4'b 1111, // index[156] AXI_RT_WRITE_PERIOD_LEFT_2 - 4'b 1111, // index[157] AXI_RT_WRITE_PERIOD_LEFT_3 - 4'b 1111, // index[158] AXI_RT_WRITE_PERIOD_LEFT_4 - 4'b 1111, // index[159] AXI_RT_WRITE_PERIOD_LEFT_5 - 4'b 1111, // index[160] AXI_RT_WRITE_PERIOD_LEFT_6 - 4'b 1111, // index[161] AXI_RT_WRITE_PERIOD_LEFT_7 - 4'b 1111, // index[162] AXI_RT_WRITE_PERIOD_LEFT_8 - 4'b 1111, // index[163] AXI_RT_WRITE_PERIOD_LEFT_9 - 4'b 1111, // index[164] AXI_RT_WRITE_PERIOD_LEFT_10 - 4'b 1111, // index[165] AXI_RT_WRITE_PERIOD_LEFT_11 - 4'b 1111, // index[166] AXI_RT_WRITE_PERIOD_LEFT_12 - 4'b 1111, // index[167] AXI_RT_WRITE_PERIOD_LEFT_13 - 4'b 1111, // index[168] AXI_RT_WRITE_PERIOD_LEFT_14 - 4'b 1111, // index[169] AXI_RT_WRITE_PERIOD_LEFT_15 - 4'b 1111, // index[170] AXI_RT_WRITE_PERIOD_LEFT_16 - 4'b 1111, // index[171] AXI_RT_WRITE_PERIOD_LEFT_17 - 4'b 1111, // index[172] AXI_RT_WRITE_PERIOD_LEFT_18 - 4'b 1111, // index[173] AXI_RT_WRITE_PERIOD_LEFT_19 - 4'b 1111, // index[174] AXI_RT_WRITE_PERIOD_LEFT_20 - 4'b 1111, // index[175] AXI_RT_WRITE_PERIOD_LEFT_21 - 4'b 1111, // index[176] AXI_RT_WRITE_PERIOD_LEFT_22 - 4'b 1111, // index[177] AXI_RT_WRITE_PERIOD_LEFT_23 - 4'b 1111, // index[178] AXI_RT_READ_PERIOD_LEFT_0 - 4'b 1111, // index[179] AXI_RT_READ_PERIOD_LEFT_1 - 4'b 1111, // index[180] AXI_RT_READ_PERIOD_LEFT_2 - 4'b 1111, // index[181] AXI_RT_READ_PERIOD_LEFT_3 - 4'b 1111, // index[182] AXI_RT_READ_PERIOD_LEFT_4 - 4'b 1111, // index[183] AXI_RT_READ_PERIOD_LEFT_5 - 4'b 1111, // index[184] AXI_RT_READ_PERIOD_LEFT_6 - 4'b 1111, // index[185] AXI_RT_READ_PERIOD_LEFT_7 - 4'b 1111, // index[186] AXI_RT_READ_PERIOD_LEFT_8 - 4'b 1111, // index[187] AXI_RT_READ_PERIOD_LEFT_9 - 4'b 1111, // index[188] AXI_RT_READ_PERIOD_LEFT_10 - 4'b 1111, // index[189] AXI_RT_READ_PERIOD_LEFT_11 - 4'b 1111, // index[190] AXI_RT_READ_PERIOD_LEFT_12 - 4'b 1111, // index[191] AXI_RT_READ_PERIOD_LEFT_13 - 4'b 1111, // index[192] AXI_RT_READ_PERIOD_LEFT_14 - 4'b 1111, // index[193] AXI_RT_READ_PERIOD_LEFT_15 - 4'b 1111, // index[194] AXI_RT_READ_PERIOD_LEFT_16 - 4'b 1111, // index[195] AXI_RT_READ_PERIOD_LEFT_17 - 4'b 1111, // index[196] AXI_RT_READ_PERIOD_LEFT_18 - 4'b 1111, // index[197] AXI_RT_READ_PERIOD_LEFT_19 - 4'b 1111, // index[198] AXI_RT_READ_PERIOD_LEFT_20 - 4'b 1111, // index[199] AXI_RT_READ_PERIOD_LEFT_21 - 4'b 1111, // index[200] AXI_RT_READ_PERIOD_LEFT_22 - 4'b 1111, // index[201] AXI_RT_READ_PERIOD_LEFT_23 - 4'b 0111, // index[202] AXI_RT_ISOLATE - 4'b 0111 // index[203] AXI_RT_ISOLATED - }; - -endpackage - diff --git a/hw/regs/axi_rt_reg_top.sv b/hw/regs/axi_rt_reg_top.sv deleted file mode 100644 index e7a0e949..00000000 --- a/hw/regs/axi_rt_reg_top.sv +++ /dev/null @@ -1,11135 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - - -`include "common_cells/assertions.svh" - -module axi_rt_reg_top #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic, - parameter int AW = 10 -) ( - input logic clk_i, - input logic rst_ni, - input reg_req_t reg_req_i, - output reg_rsp_t reg_rsp_o, - // To HW - output axi_rt_reg_pkg::axi_rt_reg2hw_t reg2hw, // Write - input axi_rt_reg_pkg::axi_rt_hw2reg_t hw2reg, // Read - - - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - - import axi_rt_reg_pkg::* ; - - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [BlockAw-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - - // Below register interface can be changed - reg_req_t reg_intf_req; - reg_rsp_t reg_intf_rsp; - - - assign reg_intf_req = reg_req_i; - assign reg_rsp_o = reg_intf_rsp; - - - assign reg_we = reg_intf_req.valid & reg_intf_req.write; - assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; - assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; - assign reg_wdata = reg_intf_req.wdata; - assign reg_be = reg_intf_req.wstrb; - assign reg_intf_rsp.rdata = reg_rdata; - assign reg_intf_rsp.error = reg_error; - assign reg_intf_rsp.ready = 1'b1; - - assign reg_rdata = reg_rdata_next ; - assign reg_error = (devmode_i & addrmiss) | wr_err; - - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic rt_enable_enable_0_qs; - logic rt_enable_enable_0_wd; - logic rt_enable_enable_0_we; - logic rt_enable_enable_1_qs; - logic rt_enable_enable_1_wd; - logic rt_enable_enable_1_we; - logic rt_enable_enable_2_qs; - logic rt_enable_enable_2_wd; - logic rt_enable_enable_2_we; - logic rt_enable_enable_3_qs; - logic rt_enable_enable_3_wd; - logic rt_enable_enable_3_we; - logic rt_enable_enable_4_qs; - logic rt_enable_enable_4_wd; - logic rt_enable_enable_4_we; - logic rt_enable_enable_5_qs; - logic rt_enable_enable_5_wd; - logic rt_enable_enable_5_we; - logic rt_enable_enable_6_qs; - logic rt_enable_enable_6_wd; - logic rt_enable_enable_6_we; - logic rt_enable_enable_7_qs; - logic rt_enable_enable_7_wd; - logic rt_enable_enable_7_we; - logic rt_enable_enable_8_qs; - logic rt_enable_enable_8_wd; - logic rt_enable_enable_8_we; - logic rt_enable_enable_9_qs; - logic rt_enable_enable_9_wd; - logic rt_enable_enable_9_we; - logic rt_enable_enable_10_qs; - logic rt_enable_enable_10_wd; - logic rt_enable_enable_10_we; - logic rt_enable_enable_11_qs; - logic rt_enable_enable_11_wd; - logic rt_enable_enable_11_we; - logic rt_enable_enable_12_qs; - logic rt_enable_enable_12_wd; - logic rt_enable_enable_12_we; - logic rt_enable_enable_13_qs; - logic rt_enable_enable_13_wd; - logic rt_enable_enable_13_we; - logic rt_enable_enable_14_qs; - logic rt_enable_enable_14_wd; - logic rt_enable_enable_14_we; - logic rt_enable_enable_15_qs; - logic rt_enable_enable_15_wd; - logic rt_enable_enable_15_we; - logic rt_enable_enable_16_qs; - logic rt_enable_enable_16_wd; - logic rt_enable_enable_16_we; - logic rt_enable_enable_17_qs; - logic rt_enable_enable_17_wd; - logic rt_enable_enable_17_we; - logic rt_enable_enable_18_qs; - logic rt_enable_enable_18_wd; - logic rt_enable_enable_18_we; - logic rt_enable_enable_19_qs; - logic rt_enable_enable_19_wd; - logic rt_enable_enable_19_we; - logic rt_enable_enable_20_qs; - logic rt_enable_enable_20_wd; - logic rt_enable_enable_20_we; - logic rt_enable_enable_21_qs; - logic rt_enable_enable_21_wd; - logic rt_enable_enable_21_we; - logic rt_enable_enable_22_qs; - logic rt_enable_enable_22_wd; - logic rt_enable_enable_22_we; - logic rt_enable_enable_23_qs; - logic rt_enable_enable_23_wd; - logic rt_enable_enable_23_we; - logic rt_bypassed_bypassed_0_qs; - logic rt_bypassed_bypassed_0_re; - logic rt_bypassed_bypassed_1_qs; - logic rt_bypassed_bypassed_1_re; - logic rt_bypassed_bypassed_2_qs; - logic rt_bypassed_bypassed_2_re; - logic rt_bypassed_bypassed_3_qs; - logic rt_bypassed_bypassed_3_re; - logic rt_bypassed_bypassed_4_qs; - logic rt_bypassed_bypassed_4_re; - logic rt_bypassed_bypassed_5_qs; - logic rt_bypassed_bypassed_5_re; - logic rt_bypassed_bypassed_6_qs; - logic rt_bypassed_bypassed_6_re; - logic rt_bypassed_bypassed_7_qs; - logic rt_bypassed_bypassed_7_re; - logic rt_bypassed_bypassed_8_qs; - logic rt_bypassed_bypassed_8_re; - logic rt_bypassed_bypassed_9_qs; - logic rt_bypassed_bypassed_9_re; - logic rt_bypassed_bypassed_10_qs; - logic rt_bypassed_bypassed_10_re; - logic rt_bypassed_bypassed_11_qs; - logic rt_bypassed_bypassed_11_re; - logic rt_bypassed_bypassed_12_qs; - logic rt_bypassed_bypassed_12_re; - logic rt_bypassed_bypassed_13_qs; - logic rt_bypassed_bypassed_13_re; - logic rt_bypassed_bypassed_14_qs; - logic rt_bypassed_bypassed_14_re; - logic rt_bypassed_bypassed_15_qs; - logic rt_bypassed_bypassed_15_re; - logic rt_bypassed_bypassed_16_qs; - logic rt_bypassed_bypassed_16_re; - logic rt_bypassed_bypassed_17_qs; - logic rt_bypassed_bypassed_17_re; - logic rt_bypassed_bypassed_18_qs; - logic rt_bypassed_bypassed_18_re; - logic rt_bypassed_bypassed_19_qs; - logic rt_bypassed_bypassed_19_re; - logic rt_bypassed_bypassed_20_qs; - logic rt_bypassed_bypassed_20_re; - logic rt_bypassed_bypassed_21_qs; - logic rt_bypassed_bypassed_21_re; - logic rt_bypassed_bypassed_22_qs; - logic rt_bypassed_bypassed_22_re; - logic rt_bypassed_bypassed_23_qs; - logic rt_bypassed_bypassed_23_re; - logic [7:0] len_limit_0_len_0_qs; - logic [7:0] len_limit_0_len_0_wd; - logic len_limit_0_len_0_we; - logic [7:0] len_limit_0_len_1_qs; - logic [7:0] len_limit_0_len_1_wd; - logic len_limit_0_len_1_we; - logic [7:0] len_limit_0_len_2_qs; - logic [7:0] len_limit_0_len_2_wd; - logic len_limit_0_len_2_we; - logic [7:0] len_limit_0_len_3_qs; - logic [7:0] len_limit_0_len_3_wd; - logic len_limit_0_len_3_we; - logic [7:0] len_limit_1_len_4_qs; - logic [7:0] len_limit_1_len_4_wd; - logic len_limit_1_len_4_we; - logic [7:0] len_limit_1_len_5_qs; - logic [7:0] len_limit_1_len_5_wd; - logic len_limit_1_len_5_we; - logic [7:0] len_limit_1_len_6_qs; - logic [7:0] len_limit_1_len_6_wd; - logic len_limit_1_len_6_we; - logic [7:0] len_limit_1_len_7_qs; - logic [7:0] len_limit_1_len_7_wd; - logic len_limit_1_len_7_we; - logic [7:0] len_limit_2_len_8_qs; - logic [7:0] len_limit_2_len_8_wd; - logic len_limit_2_len_8_we; - logic [7:0] len_limit_2_len_9_qs; - logic [7:0] len_limit_2_len_9_wd; - logic len_limit_2_len_9_we; - logic [7:0] len_limit_2_len_10_qs; - logic [7:0] len_limit_2_len_10_wd; - logic len_limit_2_len_10_we; - logic [7:0] len_limit_2_len_11_qs; - logic [7:0] len_limit_2_len_11_wd; - logic len_limit_2_len_11_we; - logic [7:0] len_limit_3_len_12_qs; - logic [7:0] len_limit_3_len_12_wd; - logic len_limit_3_len_12_we; - logic [7:0] len_limit_3_len_13_qs; - logic [7:0] len_limit_3_len_13_wd; - logic len_limit_3_len_13_we; - logic [7:0] len_limit_3_len_14_qs; - logic [7:0] len_limit_3_len_14_wd; - logic len_limit_3_len_14_we; - logic [7:0] len_limit_3_len_15_qs; - logic [7:0] len_limit_3_len_15_wd; - logic len_limit_3_len_15_we; - logic [7:0] len_limit_4_len_16_qs; - logic [7:0] len_limit_4_len_16_wd; - logic len_limit_4_len_16_we; - logic [7:0] len_limit_4_len_17_qs; - logic [7:0] len_limit_4_len_17_wd; - logic len_limit_4_len_17_we; - logic [7:0] len_limit_4_len_18_qs; - logic [7:0] len_limit_4_len_18_wd; - logic len_limit_4_len_18_we; - logic [7:0] len_limit_4_len_19_qs; - logic [7:0] len_limit_4_len_19_wd; - logic len_limit_4_len_19_we; - logic [7:0] len_limit_5_len_20_qs; - logic [7:0] len_limit_5_len_20_wd; - logic len_limit_5_len_20_we; - logic [7:0] len_limit_5_len_21_qs; - logic [7:0] len_limit_5_len_21_wd; - logic len_limit_5_len_21_we; - logic [7:0] len_limit_5_len_22_qs; - logic [7:0] len_limit_5_len_22_wd; - logic len_limit_5_len_22_we; - logic [7:0] len_limit_5_len_23_qs; - logic [7:0] len_limit_5_len_23_wd; - logic len_limit_5_len_23_we; - logic imtu_enable_enable_0_qs; - logic imtu_enable_enable_0_wd; - logic imtu_enable_enable_0_we; - logic imtu_enable_enable_1_qs; - logic imtu_enable_enable_1_wd; - logic imtu_enable_enable_1_we; - logic imtu_enable_enable_2_qs; - logic imtu_enable_enable_2_wd; - logic imtu_enable_enable_2_we; - logic imtu_enable_enable_3_qs; - logic imtu_enable_enable_3_wd; - logic imtu_enable_enable_3_we; - logic imtu_enable_enable_4_qs; - logic imtu_enable_enable_4_wd; - logic imtu_enable_enable_4_we; - logic imtu_enable_enable_5_qs; - logic imtu_enable_enable_5_wd; - logic imtu_enable_enable_5_we; - logic imtu_enable_enable_6_qs; - logic imtu_enable_enable_6_wd; - logic imtu_enable_enable_6_we; - logic imtu_enable_enable_7_qs; - logic imtu_enable_enable_7_wd; - logic imtu_enable_enable_7_we; - logic imtu_enable_enable_8_qs; - logic imtu_enable_enable_8_wd; - logic imtu_enable_enable_8_we; - logic imtu_enable_enable_9_qs; - logic imtu_enable_enable_9_wd; - logic imtu_enable_enable_9_we; - logic imtu_enable_enable_10_qs; - logic imtu_enable_enable_10_wd; - logic imtu_enable_enable_10_we; - logic imtu_enable_enable_11_qs; - logic imtu_enable_enable_11_wd; - logic imtu_enable_enable_11_we; - logic imtu_enable_enable_12_qs; - logic imtu_enable_enable_12_wd; - logic imtu_enable_enable_12_we; - logic imtu_enable_enable_13_qs; - logic imtu_enable_enable_13_wd; - logic imtu_enable_enable_13_we; - logic imtu_enable_enable_14_qs; - logic imtu_enable_enable_14_wd; - logic imtu_enable_enable_14_we; - logic imtu_enable_enable_15_qs; - logic imtu_enable_enable_15_wd; - logic imtu_enable_enable_15_we; - logic imtu_enable_enable_16_qs; - logic imtu_enable_enable_16_wd; - logic imtu_enable_enable_16_we; - logic imtu_enable_enable_17_qs; - logic imtu_enable_enable_17_wd; - logic imtu_enable_enable_17_we; - logic imtu_enable_enable_18_qs; - logic imtu_enable_enable_18_wd; - logic imtu_enable_enable_18_we; - logic imtu_enable_enable_19_qs; - logic imtu_enable_enable_19_wd; - logic imtu_enable_enable_19_we; - logic imtu_enable_enable_20_qs; - logic imtu_enable_enable_20_wd; - logic imtu_enable_enable_20_we; - logic imtu_enable_enable_21_qs; - logic imtu_enable_enable_21_wd; - logic imtu_enable_enable_21_we; - logic imtu_enable_enable_22_qs; - logic imtu_enable_enable_22_wd; - logic imtu_enable_enable_22_we; - logic imtu_enable_enable_23_qs; - logic imtu_enable_enable_23_wd; - logic imtu_enable_enable_23_we; - logic imtu_abort_abort_0_qs; - logic imtu_abort_abort_0_wd; - logic imtu_abort_abort_0_we; - logic imtu_abort_abort_1_qs; - logic imtu_abort_abort_1_wd; - logic imtu_abort_abort_1_we; - logic imtu_abort_abort_2_qs; - logic imtu_abort_abort_2_wd; - logic imtu_abort_abort_2_we; - logic imtu_abort_abort_3_qs; - logic imtu_abort_abort_3_wd; - logic imtu_abort_abort_3_we; - logic imtu_abort_abort_4_qs; - logic imtu_abort_abort_4_wd; - logic imtu_abort_abort_4_we; - logic imtu_abort_abort_5_qs; - logic imtu_abort_abort_5_wd; - logic imtu_abort_abort_5_we; - logic imtu_abort_abort_6_qs; - logic imtu_abort_abort_6_wd; - logic imtu_abort_abort_6_we; - logic imtu_abort_abort_7_qs; - logic imtu_abort_abort_7_wd; - logic imtu_abort_abort_7_we; - logic imtu_abort_abort_8_qs; - logic imtu_abort_abort_8_wd; - logic imtu_abort_abort_8_we; - logic imtu_abort_abort_9_qs; - logic imtu_abort_abort_9_wd; - logic imtu_abort_abort_9_we; - logic imtu_abort_abort_10_qs; - logic imtu_abort_abort_10_wd; - logic imtu_abort_abort_10_we; - logic imtu_abort_abort_11_qs; - logic imtu_abort_abort_11_wd; - logic imtu_abort_abort_11_we; - logic imtu_abort_abort_12_qs; - logic imtu_abort_abort_12_wd; - logic imtu_abort_abort_12_we; - logic imtu_abort_abort_13_qs; - logic imtu_abort_abort_13_wd; - logic imtu_abort_abort_13_we; - logic imtu_abort_abort_14_qs; - logic imtu_abort_abort_14_wd; - logic imtu_abort_abort_14_we; - logic imtu_abort_abort_15_qs; - logic imtu_abort_abort_15_wd; - logic imtu_abort_abort_15_we; - logic imtu_abort_abort_16_qs; - logic imtu_abort_abort_16_wd; - logic imtu_abort_abort_16_we; - logic imtu_abort_abort_17_qs; - logic imtu_abort_abort_17_wd; - logic imtu_abort_abort_17_we; - logic imtu_abort_abort_18_qs; - logic imtu_abort_abort_18_wd; - logic imtu_abort_abort_18_we; - logic imtu_abort_abort_19_qs; - logic imtu_abort_abort_19_wd; - logic imtu_abort_abort_19_we; - logic imtu_abort_abort_20_qs; - logic imtu_abort_abort_20_wd; - logic imtu_abort_abort_20_we; - logic imtu_abort_abort_21_qs; - logic imtu_abort_abort_21_wd; - logic imtu_abort_abort_21_we; - logic imtu_abort_abort_22_qs; - logic imtu_abort_abort_22_wd; - logic imtu_abort_abort_22_we; - logic imtu_abort_abort_23_qs; - logic imtu_abort_abort_23_wd; - logic imtu_abort_abort_23_we; - logic [31:0] write_budget_0_qs; - logic [31:0] write_budget_0_wd; - logic write_budget_0_we; - logic [31:0] write_budget_1_qs; - logic [31:0] write_budget_1_wd; - logic write_budget_1_we; - logic [31:0] write_budget_2_qs; - logic [31:0] write_budget_2_wd; - logic write_budget_2_we; - logic [31:0] write_budget_3_qs; - logic [31:0] write_budget_3_wd; - logic write_budget_3_we; - logic [31:0] write_budget_4_qs; - logic [31:0] write_budget_4_wd; - logic write_budget_4_we; - logic [31:0] write_budget_5_qs; - logic [31:0] write_budget_5_wd; - logic write_budget_5_we; - logic [31:0] write_budget_6_qs; - logic [31:0] write_budget_6_wd; - logic write_budget_6_we; - logic [31:0] write_budget_7_qs; - logic [31:0] write_budget_7_wd; - logic write_budget_7_we; - logic [31:0] write_budget_8_qs; - logic [31:0] write_budget_8_wd; - logic write_budget_8_we; - logic [31:0] write_budget_9_qs; - logic [31:0] write_budget_9_wd; - logic write_budget_9_we; - logic [31:0] write_budget_10_qs; - logic [31:0] write_budget_10_wd; - logic write_budget_10_we; - logic [31:0] write_budget_11_qs; - logic [31:0] write_budget_11_wd; - logic write_budget_11_we; - logic [31:0] write_budget_12_qs; - logic [31:0] write_budget_12_wd; - logic write_budget_12_we; - logic [31:0] write_budget_13_qs; - logic [31:0] write_budget_13_wd; - logic write_budget_13_we; - logic [31:0] write_budget_14_qs; - logic [31:0] write_budget_14_wd; - logic write_budget_14_we; - logic [31:0] write_budget_15_qs; - logic [31:0] write_budget_15_wd; - logic write_budget_15_we; - logic [31:0] write_budget_16_qs; - logic [31:0] write_budget_16_wd; - logic write_budget_16_we; - logic [31:0] write_budget_17_qs; - logic [31:0] write_budget_17_wd; - logic write_budget_17_we; - logic [31:0] write_budget_18_qs; - logic [31:0] write_budget_18_wd; - logic write_budget_18_we; - logic [31:0] write_budget_19_qs; - logic [31:0] write_budget_19_wd; - logic write_budget_19_we; - logic [31:0] write_budget_20_qs; - logic [31:0] write_budget_20_wd; - logic write_budget_20_we; - logic [31:0] write_budget_21_qs; - logic [31:0] write_budget_21_wd; - logic write_budget_21_we; - logic [31:0] write_budget_22_qs; - logic [31:0] write_budget_22_wd; - logic write_budget_22_we; - logic [31:0] write_budget_23_qs; - logic [31:0] write_budget_23_wd; - logic write_budget_23_we; - logic [31:0] read_budget_0_qs; - logic [31:0] read_budget_0_wd; - logic read_budget_0_we; - logic [31:0] read_budget_1_qs; - logic [31:0] read_budget_1_wd; - logic read_budget_1_we; - logic [31:0] read_budget_2_qs; - logic [31:0] read_budget_2_wd; - logic read_budget_2_we; - logic [31:0] read_budget_3_qs; - logic [31:0] read_budget_3_wd; - logic read_budget_3_we; - logic [31:0] read_budget_4_qs; - logic [31:0] read_budget_4_wd; - logic read_budget_4_we; - logic [31:0] read_budget_5_qs; - logic [31:0] read_budget_5_wd; - logic read_budget_5_we; - logic [31:0] read_budget_6_qs; - logic [31:0] read_budget_6_wd; - logic read_budget_6_we; - logic [31:0] read_budget_7_qs; - logic [31:0] read_budget_7_wd; - logic read_budget_7_we; - logic [31:0] read_budget_8_qs; - logic [31:0] read_budget_8_wd; - logic read_budget_8_we; - logic [31:0] read_budget_9_qs; - logic [31:0] read_budget_9_wd; - logic read_budget_9_we; - logic [31:0] read_budget_10_qs; - logic [31:0] read_budget_10_wd; - logic read_budget_10_we; - logic [31:0] read_budget_11_qs; - logic [31:0] read_budget_11_wd; - logic read_budget_11_we; - logic [31:0] read_budget_12_qs; - logic [31:0] read_budget_12_wd; - logic read_budget_12_we; - logic [31:0] read_budget_13_qs; - logic [31:0] read_budget_13_wd; - logic read_budget_13_we; - logic [31:0] read_budget_14_qs; - logic [31:0] read_budget_14_wd; - logic read_budget_14_we; - logic [31:0] read_budget_15_qs; - logic [31:0] read_budget_15_wd; - logic read_budget_15_we; - logic [31:0] read_budget_16_qs; - logic [31:0] read_budget_16_wd; - logic read_budget_16_we; - logic [31:0] read_budget_17_qs; - logic [31:0] read_budget_17_wd; - logic read_budget_17_we; - logic [31:0] read_budget_18_qs; - logic [31:0] read_budget_18_wd; - logic read_budget_18_we; - logic [31:0] read_budget_19_qs; - logic [31:0] read_budget_19_wd; - logic read_budget_19_we; - logic [31:0] read_budget_20_qs; - logic [31:0] read_budget_20_wd; - logic read_budget_20_we; - logic [31:0] read_budget_21_qs; - logic [31:0] read_budget_21_wd; - logic read_budget_21_we; - logic [31:0] read_budget_22_qs; - logic [31:0] read_budget_22_wd; - logic read_budget_22_we; - logic [31:0] read_budget_23_qs; - logic [31:0] read_budget_23_wd; - logic read_budget_23_we; - logic [31:0] write_period_0_qs; - logic [31:0] write_period_0_wd; - logic write_period_0_we; - logic [31:0] write_period_1_qs; - logic [31:0] write_period_1_wd; - logic write_period_1_we; - logic [31:0] write_period_2_qs; - logic [31:0] write_period_2_wd; - logic write_period_2_we; - logic [31:0] write_period_3_qs; - logic [31:0] write_period_3_wd; - logic write_period_3_we; - logic [31:0] write_period_4_qs; - logic [31:0] write_period_4_wd; - logic write_period_4_we; - logic [31:0] write_period_5_qs; - logic [31:0] write_period_5_wd; - logic write_period_5_we; - logic [31:0] write_period_6_qs; - logic [31:0] write_period_6_wd; - logic write_period_6_we; - logic [31:0] write_period_7_qs; - logic [31:0] write_period_7_wd; - logic write_period_7_we; - logic [31:0] write_period_8_qs; - logic [31:0] write_period_8_wd; - logic write_period_8_we; - logic [31:0] write_period_9_qs; - logic [31:0] write_period_9_wd; - logic write_period_9_we; - logic [31:0] write_period_10_qs; - logic [31:0] write_period_10_wd; - logic write_period_10_we; - logic [31:0] write_period_11_qs; - logic [31:0] write_period_11_wd; - logic write_period_11_we; - logic [31:0] write_period_12_qs; - logic [31:0] write_period_12_wd; - logic write_period_12_we; - logic [31:0] write_period_13_qs; - logic [31:0] write_period_13_wd; - logic write_period_13_we; - logic [31:0] write_period_14_qs; - logic [31:0] write_period_14_wd; - logic write_period_14_we; - logic [31:0] write_period_15_qs; - logic [31:0] write_period_15_wd; - logic write_period_15_we; - logic [31:0] write_period_16_qs; - logic [31:0] write_period_16_wd; - logic write_period_16_we; - logic [31:0] write_period_17_qs; - logic [31:0] write_period_17_wd; - logic write_period_17_we; - logic [31:0] write_period_18_qs; - logic [31:0] write_period_18_wd; - logic write_period_18_we; - logic [31:0] write_period_19_qs; - logic [31:0] write_period_19_wd; - logic write_period_19_we; - logic [31:0] write_period_20_qs; - logic [31:0] write_period_20_wd; - logic write_period_20_we; - logic [31:0] write_period_21_qs; - logic [31:0] write_period_21_wd; - logic write_period_21_we; - logic [31:0] write_period_22_qs; - logic [31:0] write_period_22_wd; - logic write_period_22_we; - logic [31:0] write_period_23_qs; - logic [31:0] write_period_23_wd; - logic write_period_23_we; - logic [31:0] read_period_0_qs; - logic [31:0] read_period_0_wd; - logic read_period_0_we; - logic [31:0] read_period_1_qs; - logic [31:0] read_period_1_wd; - logic read_period_1_we; - logic [31:0] read_period_2_qs; - logic [31:0] read_period_2_wd; - logic read_period_2_we; - logic [31:0] read_period_3_qs; - logic [31:0] read_period_3_wd; - logic read_period_3_we; - logic [31:0] read_period_4_qs; - logic [31:0] read_period_4_wd; - logic read_period_4_we; - logic [31:0] read_period_5_qs; - logic [31:0] read_period_5_wd; - logic read_period_5_we; - logic [31:0] read_period_6_qs; - logic [31:0] read_period_6_wd; - logic read_period_6_we; - logic [31:0] read_period_7_qs; - logic [31:0] read_period_7_wd; - logic read_period_7_we; - logic [31:0] read_period_8_qs; - logic [31:0] read_period_8_wd; - logic read_period_8_we; - logic [31:0] read_period_9_qs; - logic [31:0] read_period_9_wd; - logic read_period_9_we; - logic [31:0] read_period_10_qs; - logic [31:0] read_period_10_wd; - logic read_period_10_we; - logic [31:0] read_period_11_qs; - logic [31:0] read_period_11_wd; - logic read_period_11_we; - logic [31:0] read_period_12_qs; - logic [31:0] read_period_12_wd; - logic read_period_12_we; - logic [31:0] read_period_13_qs; - logic [31:0] read_period_13_wd; - logic read_period_13_we; - logic [31:0] read_period_14_qs; - logic [31:0] read_period_14_wd; - logic read_period_14_we; - logic [31:0] read_period_15_qs; - logic [31:0] read_period_15_wd; - logic read_period_15_we; - logic [31:0] read_period_16_qs; - logic [31:0] read_period_16_wd; - logic read_period_16_we; - logic [31:0] read_period_17_qs; - logic [31:0] read_period_17_wd; - logic read_period_17_we; - logic [31:0] read_period_18_qs; - logic [31:0] read_period_18_wd; - logic read_period_18_we; - logic [31:0] read_period_19_qs; - logic [31:0] read_period_19_wd; - logic read_period_19_we; - logic [31:0] read_period_20_qs; - logic [31:0] read_period_20_wd; - logic read_period_20_we; - logic [31:0] read_period_21_qs; - logic [31:0] read_period_21_wd; - logic read_period_21_we; - logic [31:0] read_period_22_qs; - logic [31:0] read_period_22_wd; - logic read_period_22_we; - logic [31:0] read_period_23_qs; - logic [31:0] read_period_23_wd; - logic read_period_23_we; - logic [31:0] write_budget_left_0_qs; - logic write_budget_left_0_re; - logic [31:0] write_budget_left_1_qs; - logic write_budget_left_1_re; - logic [31:0] write_budget_left_2_qs; - logic write_budget_left_2_re; - logic [31:0] write_budget_left_3_qs; - logic write_budget_left_3_re; - logic [31:0] write_budget_left_4_qs; - logic write_budget_left_4_re; - logic [31:0] write_budget_left_5_qs; - logic write_budget_left_5_re; - logic [31:0] write_budget_left_6_qs; - logic write_budget_left_6_re; - logic [31:0] write_budget_left_7_qs; - logic write_budget_left_7_re; - logic [31:0] write_budget_left_8_qs; - logic write_budget_left_8_re; - logic [31:0] write_budget_left_9_qs; - logic write_budget_left_9_re; - logic [31:0] write_budget_left_10_qs; - logic write_budget_left_10_re; - logic [31:0] write_budget_left_11_qs; - logic write_budget_left_11_re; - logic [31:0] write_budget_left_12_qs; - logic write_budget_left_12_re; - logic [31:0] write_budget_left_13_qs; - logic write_budget_left_13_re; - logic [31:0] write_budget_left_14_qs; - logic write_budget_left_14_re; - logic [31:0] write_budget_left_15_qs; - logic write_budget_left_15_re; - logic [31:0] write_budget_left_16_qs; - logic write_budget_left_16_re; - logic [31:0] write_budget_left_17_qs; - logic write_budget_left_17_re; - logic [31:0] write_budget_left_18_qs; - logic write_budget_left_18_re; - logic [31:0] write_budget_left_19_qs; - logic write_budget_left_19_re; - logic [31:0] write_budget_left_20_qs; - logic write_budget_left_20_re; - logic [31:0] write_budget_left_21_qs; - logic write_budget_left_21_re; - logic [31:0] write_budget_left_22_qs; - logic write_budget_left_22_re; - logic [31:0] write_budget_left_23_qs; - logic write_budget_left_23_re; - logic [31:0] read_budget_left_0_qs; - logic read_budget_left_0_re; - logic [31:0] read_budget_left_1_qs; - logic read_budget_left_1_re; - logic [31:0] read_budget_left_2_qs; - logic read_budget_left_2_re; - logic [31:0] read_budget_left_3_qs; - logic read_budget_left_3_re; - logic [31:0] read_budget_left_4_qs; - logic read_budget_left_4_re; - logic [31:0] read_budget_left_5_qs; - logic read_budget_left_5_re; - logic [31:0] read_budget_left_6_qs; - logic read_budget_left_6_re; - logic [31:0] read_budget_left_7_qs; - logic read_budget_left_7_re; - logic [31:0] read_budget_left_8_qs; - logic read_budget_left_8_re; - logic [31:0] read_budget_left_9_qs; - logic read_budget_left_9_re; - logic [31:0] read_budget_left_10_qs; - logic read_budget_left_10_re; - logic [31:0] read_budget_left_11_qs; - logic read_budget_left_11_re; - logic [31:0] read_budget_left_12_qs; - logic read_budget_left_12_re; - logic [31:0] read_budget_left_13_qs; - logic read_budget_left_13_re; - logic [31:0] read_budget_left_14_qs; - logic read_budget_left_14_re; - logic [31:0] read_budget_left_15_qs; - logic read_budget_left_15_re; - logic [31:0] read_budget_left_16_qs; - logic read_budget_left_16_re; - logic [31:0] read_budget_left_17_qs; - logic read_budget_left_17_re; - logic [31:0] read_budget_left_18_qs; - logic read_budget_left_18_re; - logic [31:0] read_budget_left_19_qs; - logic read_budget_left_19_re; - logic [31:0] read_budget_left_20_qs; - logic read_budget_left_20_re; - logic [31:0] read_budget_left_21_qs; - logic read_budget_left_21_re; - logic [31:0] read_budget_left_22_qs; - logic read_budget_left_22_re; - logic [31:0] read_budget_left_23_qs; - logic read_budget_left_23_re; - logic [31:0] write_period_left_0_qs; - logic write_period_left_0_re; - logic [31:0] write_period_left_1_qs; - logic write_period_left_1_re; - logic [31:0] write_period_left_2_qs; - logic write_period_left_2_re; - logic [31:0] write_period_left_3_qs; - logic write_period_left_3_re; - logic [31:0] write_period_left_4_qs; - logic write_period_left_4_re; - logic [31:0] write_period_left_5_qs; - logic write_period_left_5_re; - logic [31:0] write_period_left_6_qs; - logic write_period_left_6_re; - logic [31:0] write_period_left_7_qs; - logic write_period_left_7_re; - logic [31:0] write_period_left_8_qs; - logic write_period_left_8_re; - logic [31:0] write_period_left_9_qs; - logic write_period_left_9_re; - logic [31:0] write_period_left_10_qs; - logic write_period_left_10_re; - logic [31:0] write_period_left_11_qs; - logic write_period_left_11_re; - logic [31:0] write_period_left_12_qs; - logic write_period_left_12_re; - logic [31:0] write_period_left_13_qs; - logic write_period_left_13_re; - logic [31:0] write_period_left_14_qs; - logic write_period_left_14_re; - logic [31:0] write_period_left_15_qs; - logic write_period_left_15_re; - logic [31:0] write_period_left_16_qs; - logic write_period_left_16_re; - logic [31:0] write_period_left_17_qs; - logic write_period_left_17_re; - logic [31:0] write_period_left_18_qs; - logic write_period_left_18_re; - logic [31:0] write_period_left_19_qs; - logic write_period_left_19_re; - logic [31:0] write_period_left_20_qs; - logic write_period_left_20_re; - logic [31:0] write_period_left_21_qs; - logic write_period_left_21_re; - logic [31:0] write_period_left_22_qs; - logic write_period_left_22_re; - logic [31:0] write_period_left_23_qs; - logic write_period_left_23_re; - logic [31:0] read_period_left_0_qs; - logic read_period_left_0_re; - logic [31:0] read_period_left_1_qs; - logic read_period_left_1_re; - logic [31:0] read_period_left_2_qs; - logic read_period_left_2_re; - logic [31:0] read_period_left_3_qs; - logic read_period_left_3_re; - logic [31:0] read_period_left_4_qs; - logic read_period_left_4_re; - logic [31:0] read_period_left_5_qs; - logic read_period_left_5_re; - logic [31:0] read_period_left_6_qs; - logic read_period_left_6_re; - logic [31:0] read_period_left_7_qs; - logic read_period_left_7_re; - logic [31:0] read_period_left_8_qs; - logic read_period_left_8_re; - logic [31:0] read_period_left_9_qs; - logic read_period_left_9_re; - logic [31:0] read_period_left_10_qs; - logic read_period_left_10_re; - logic [31:0] read_period_left_11_qs; - logic read_period_left_11_re; - logic [31:0] read_period_left_12_qs; - logic read_period_left_12_re; - logic [31:0] read_period_left_13_qs; - logic read_period_left_13_re; - logic [31:0] read_period_left_14_qs; - logic read_period_left_14_re; - logic [31:0] read_period_left_15_qs; - logic read_period_left_15_re; - logic [31:0] read_period_left_16_qs; - logic read_period_left_16_re; - logic [31:0] read_period_left_17_qs; - logic read_period_left_17_re; - logic [31:0] read_period_left_18_qs; - logic read_period_left_18_re; - logic [31:0] read_period_left_19_qs; - logic read_period_left_19_re; - logic [31:0] read_period_left_20_qs; - logic read_period_left_20_re; - logic [31:0] read_period_left_21_qs; - logic read_period_left_21_re; - logic [31:0] read_period_left_22_qs; - logic read_period_left_22_re; - logic [31:0] read_period_left_23_qs; - logic read_period_left_23_re; - logic isolate_isolate_0_qs; - logic isolate_isolate_0_re; - logic isolate_isolate_1_qs; - logic isolate_isolate_1_re; - logic isolate_isolate_2_qs; - logic isolate_isolate_2_re; - logic isolate_isolate_3_qs; - logic isolate_isolate_3_re; - logic isolate_isolate_4_qs; - logic isolate_isolate_4_re; - logic isolate_isolate_5_qs; - logic isolate_isolate_5_re; - logic isolate_isolate_6_qs; - logic isolate_isolate_6_re; - logic isolate_isolate_7_qs; - logic isolate_isolate_7_re; - logic isolate_isolate_8_qs; - logic isolate_isolate_8_re; - logic isolate_isolate_9_qs; - logic isolate_isolate_9_re; - logic isolate_isolate_10_qs; - logic isolate_isolate_10_re; - logic isolate_isolate_11_qs; - logic isolate_isolate_11_re; - logic isolate_isolate_12_qs; - logic isolate_isolate_12_re; - logic isolate_isolate_13_qs; - logic isolate_isolate_13_re; - logic isolate_isolate_14_qs; - logic isolate_isolate_14_re; - logic isolate_isolate_15_qs; - logic isolate_isolate_15_re; - logic isolate_isolate_16_qs; - logic isolate_isolate_16_re; - logic isolate_isolate_17_qs; - logic isolate_isolate_17_re; - logic isolate_isolate_18_qs; - logic isolate_isolate_18_re; - logic isolate_isolate_19_qs; - logic isolate_isolate_19_re; - logic isolate_isolate_20_qs; - logic isolate_isolate_20_re; - logic isolate_isolate_21_qs; - logic isolate_isolate_21_re; - logic isolate_isolate_22_qs; - logic isolate_isolate_22_re; - logic isolate_isolate_23_qs; - logic isolate_isolate_23_re; - logic isolated_isolated_0_qs; - logic isolated_isolated_0_re; - logic isolated_isolated_1_qs; - logic isolated_isolated_1_re; - logic isolated_isolated_2_qs; - logic isolated_isolated_2_re; - logic isolated_isolated_3_qs; - logic isolated_isolated_3_re; - logic isolated_isolated_4_qs; - logic isolated_isolated_4_re; - logic isolated_isolated_5_qs; - logic isolated_isolated_5_re; - logic isolated_isolated_6_qs; - logic isolated_isolated_6_re; - logic isolated_isolated_7_qs; - logic isolated_isolated_7_re; - logic isolated_isolated_8_qs; - logic isolated_isolated_8_re; - logic isolated_isolated_9_qs; - logic isolated_isolated_9_re; - logic isolated_isolated_10_qs; - logic isolated_isolated_10_re; - logic isolated_isolated_11_qs; - logic isolated_isolated_11_re; - logic isolated_isolated_12_qs; - logic isolated_isolated_12_re; - logic isolated_isolated_13_qs; - logic isolated_isolated_13_re; - logic isolated_isolated_14_qs; - logic isolated_isolated_14_re; - logic isolated_isolated_15_qs; - logic isolated_isolated_15_re; - logic isolated_isolated_16_qs; - logic isolated_isolated_16_re; - logic isolated_isolated_17_qs; - logic isolated_isolated_17_re; - logic isolated_isolated_18_qs; - logic isolated_isolated_18_re; - logic isolated_isolated_19_qs; - logic isolated_isolated_19_re; - logic isolated_isolated_20_qs; - logic isolated_isolated_20_re; - logic isolated_isolated_21_qs; - logic isolated_isolated_21_re; - logic isolated_isolated_22_qs; - logic isolated_isolated_22_re; - logic isolated_isolated_23_qs; - logic isolated_isolated_23_re; - - // Register instances - - // Subregister 0 of Multireg rt_enable - // R[rt_enable]: V(False) - - // F[enable_0]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_0_we), - .wd (rt_enable_enable_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[0].q ), - - // to register interface (read) - .qs (rt_enable_enable_0_qs) - ); - - - // F[enable_1]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_1_we), - .wd (rt_enable_enable_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[1].q ), - - // to register interface (read) - .qs (rt_enable_enable_1_qs) - ); - - - // F[enable_2]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_2_we), - .wd (rt_enable_enable_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[2].q ), - - // to register interface (read) - .qs (rt_enable_enable_2_qs) - ); - - - // F[enable_3]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_3_we), - .wd (rt_enable_enable_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[3].q ), - - // to register interface (read) - .qs (rt_enable_enable_3_qs) - ); - - - // F[enable_4]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_4_we), - .wd (rt_enable_enable_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[4].q ), - - // to register interface (read) - .qs (rt_enable_enable_4_qs) - ); - - - // F[enable_5]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_5_we), - .wd (rt_enable_enable_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[5].q ), - - // to register interface (read) - .qs (rt_enable_enable_5_qs) - ); - - - // F[enable_6]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_6_we), - .wd (rt_enable_enable_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[6].q ), - - // to register interface (read) - .qs (rt_enable_enable_6_qs) - ); - - - // F[enable_7]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_7_we), - .wd (rt_enable_enable_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[7].q ), - - // to register interface (read) - .qs (rt_enable_enable_7_qs) - ); - - - // F[enable_8]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_8_we), - .wd (rt_enable_enable_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[8].q ), - - // to register interface (read) - .qs (rt_enable_enable_8_qs) - ); - - - // F[enable_9]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_9_we), - .wd (rt_enable_enable_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[9].q ), - - // to register interface (read) - .qs (rt_enable_enable_9_qs) - ); - - - // F[enable_10]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_10_we), - .wd (rt_enable_enable_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[10].q ), - - // to register interface (read) - .qs (rt_enable_enable_10_qs) - ); - - - // F[enable_11]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_11_we), - .wd (rt_enable_enable_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[11].q ), - - // to register interface (read) - .qs (rt_enable_enable_11_qs) - ); - - - // F[enable_12]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_12_we), - .wd (rt_enable_enable_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[12].q ), - - // to register interface (read) - .qs (rt_enable_enable_12_qs) - ); - - - // F[enable_13]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_13_we), - .wd (rt_enable_enable_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[13].q ), - - // to register interface (read) - .qs (rt_enable_enable_13_qs) - ); - - - // F[enable_14]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_14_we), - .wd (rt_enable_enable_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[14].q ), - - // to register interface (read) - .qs (rt_enable_enable_14_qs) - ); - - - // F[enable_15]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_15_we), - .wd (rt_enable_enable_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[15].q ), - - // to register interface (read) - .qs (rt_enable_enable_15_qs) - ); - - - // F[enable_16]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_16_we), - .wd (rt_enable_enable_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[16].q ), - - // to register interface (read) - .qs (rt_enable_enable_16_qs) - ); - - - // F[enable_17]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_17_we), - .wd (rt_enable_enable_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[17].q ), - - // to register interface (read) - .qs (rt_enable_enable_17_qs) - ); - - - // F[enable_18]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_18_we), - .wd (rt_enable_enable_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[18].q ), - - // to register interface (read) - .qs (rt_enable_enable_18_qs) - ); - - - // F[enable_19]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_19_we), - .wd (rt_enable_enable_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[19].q ), - - // to register interface (read) - .qs (rt_enable_enable_19_qs) - ); - - - // F[enable_20]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_20_we), - .wd (rt_enable_enable_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[20].q ), - - // to register interface (read) - .qs (rt_enable_enable_20_qs) - ); - - - // F[enable_21]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_21_we), - .wd (rt_enable_enable_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[21].q ), - - // to register interface (read) - .qs (rt_enable_enable_21_qs) - ); - - - // F[enable_22]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_22_we), - .wd (rt_enable_enable_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[22].q ), - - // to register interface (read) - .qs (rt_enable_enable_22_qs) - ); - - - // F[enable_23]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_rt_enable_enable_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (rt_enable_enable_23_we), - .wd (rt_enable_enable_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rt_enable[23].q ), - - // to register interface (read) - .qs (rt_enable_enable_23_qs) - ); - - - - - // Subregister 0 of Multireg rt_bypassed - // R[rt_bypassed]: V(True) - - // F[bypassed_0]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_0 ( - .re (rt_bypassed_bypassed_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[0].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_0_qs) - ); - - - // F[bypassed_1]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_1 ( - .re (rt_bypassed_bypassed_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[1].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_1_qs) - ); - - - // F[bypassed_2]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_2 ( - .re (rt_bypassed_bypassed_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[2].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_2_qs) - ); - - - // F[bypassed_3]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_3 ( - .re (rt_bypassed_bypassed_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[3].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_3_qs) - ); - - - // F[bypassed_4]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_4 ( - .re (rt_bypassed_bypassed_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[4].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_4_qs) - ); - - - // F[bypassed_5]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_5 ( - .re (rt_bypassed_bypassed_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[5].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_5_qs) - ); - - - // F[bypassed_6]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_6 ( - .re (rt_bypassed_bypassed_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[6].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_6_qs) - ); - - - // F[bypassed_7]: 7:7 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_7 ( - .re (rt_bypassed_bypassed_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[7].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_7_qs) - ); - - - // F[bypassed_8]: 8:8 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_8 ( - .re (rt_bypassed_bypassed_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[8].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_8_qs) - ); - - - // F[bypassed_9]: 9:9 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_9 ( - .re (rt_bypassed_bypassed_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[9].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_9_qs) - ); - - - // F[bypassed_10]: 10:10 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_10 ( - .re (rt_bypassed_bypassed_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[10].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_10_qs) - ); - - - // F[bypassed_11]: 11:11 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_11 ( - .re (rt_bypassed_bypassed_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[11].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_11_qs) - ); - - - // F[bypassed_12]: 12:12 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_12 ( - .re (rt_bypassed_bypassed_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[12].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_12_qs) - ); - - - // F[bypassed_13]: 13:13 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_13 ( - .re (rt_bypassed_bypassed_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[13].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_13_qs) - ); - - - // F[bypassed_14]: 14:14 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_14 ( - .re (rt_bypassed_bypassed_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[14].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_14_qs) - ); - - - // F[bypassed_15]: 15:15 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_15 ( - .re (rt_bypassed_bypassed_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[15].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_15_qs) - ); - - - // F[bypassed_16]: 16:16 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_16 ( - .re (rt_bypassed_bypassed_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[16].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_16_qs) - ); - - - // F[bypassed_17]: 17:17 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_17 ( - .re (rt_bypassed_bypassed_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[17].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_17_qs) - ); - - - // F[bypassed_18]: 18:18 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_18 ( - .re (rt_bypassed_bypassed_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[18].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_18_qs) - ); - - - // F[bypassed_19]: 19:19 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_19 ( - .re (rt_bypassed_bypassed_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[19].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_19_qs) - ); - - - // F[bypassed_20]: 20:20 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_20 ( - .re (rt_bypassed_bypassed_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[20].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_20_qs) - ); - - - // F[bypassed_21]: 21:21 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_21 ( - .re (rt_bypassed_bypassed_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[21].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_21_qs) - ); - - - // F[bypassed_22]: 22:22 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_22 ( - .re (rt_bypassed_bypassed_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[22].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_22_qs) - ); - - - // F[bypassed_23]: 23:23 - prim_subreg_ext #( - .DW (1) - ) u_rt_bypassed_bypassed_23 ( - .re (rt_bypassed_bypassed_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.rt_bypassed[23].d), - .qre (), - .qe (), - .q (), - .qs (rt_bypassed_bypassed_23_qs) - ); - - - - - // Subregister 0 of Multireg len_limit - // R[len_limit_0]: V(False) - - // F[len_0]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_0_len_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_0_len_0_we), - .wd (len_limit_0_len_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[0].q ), - - // to register interface (read) - .qs (len_limit_0_len_0_qs) - ); - - - // F[len_1]: 15:8 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_0_len_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_0_len_1_we), - .wd (len_limit_0_len_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[1].q ), - - // to register interface (read) - .qs (len_limit_0_len_1_qs) - ); - - - // F[len_2]: 23:16 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_0_len_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_0_len_2_we), - .wd (len_limit_0_len_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[2].q ), - - // to register interface (read) - .qs (len_limit_0_len_2_qs) - ); - - - // F[len_3]: 31:24 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_0_len_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_0_len_3_we), - .wd (len_limit_0_len_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[3].q ), - - // to register interface (read) - .qs (len_limit_0_len_3_qs) - ); - - - // Subregister 4 of Multireg len_limit - // R[len_limit_1]: V(False) - - // F[len_4]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_1_len_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_1_len_4_we), - .wd (len_limit_1_len_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[4].q ), - - // to register interface (read) - .qs (len_limit_1_len_4_qs) - ); - - - // F[len_5]: 15:8 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_1_len_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_1_len_5_we), - .wd (len_limit_1_len_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[5].q ), - - // to register interface (read) - .qs (len_limit_1_len_5_qs) - ); - - - // F[len_6]: 23:16 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_1_len_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_1_len_6_we), - .wd (len_limit_1_len_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[6].q ), - - // to register interface (read) - .qs (len_limit_1_len_6_qs) - ); - - - // F[len_7]: 31:24 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_1_len_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_1_len_7_we), - .wd (len_limit_1_len_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[7].q ), - - // to register interface (read) - .qs (len_limit_1_len_7_qs) - ); - - - // Subregister 8 of Multireg len_limit - // R[len_limit_2]: V(False) - - // F[len_8]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_2_len_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_2_len_8_we), - .wd (len_limit_2_len_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[8].q ), - - // to register interface (read) - .qs (len_limit_2_len_8_qs) - ); - - - // F[len_9]: 15:8 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_2_len_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_2_len_9_we), - .wd (len_limit_2_len_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[9].q ), - - // to register interface (read) - .qs (len_limit_2_len_9_qs) - ); - - - // F[len_10]: 23:16 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_2_len_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_2_len_10_we), - .wd (len_limit_2_len_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[10].q ), - - // to register interface (read) - .qs (len_limit_2_len_10_qs) - ); - - - // F[len_11]: 31:24 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_2_len_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_2_len_11_we), - .wd (len_limit_2_len_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[11].q ), - - // to register interface (read) - .qs (len_limit_2_len_11_qs) - ); - - - // Subregister 12 of Multireg len_limit - // R[len_limit_3]: V(False) - - // F[len_12]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_3_len_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_3_len_12_we), - .wd (len_limit_3_len_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[12].q ), - - // to register interface (read) - .qs (len_limit_3_len_12_qs) - ); - - - // F[len_13]: 15:8 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_3_len_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_3_len_13_we), - .wd (len_limit_3_len_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[13].q ), - - // to register interface (read) - .qs (len_limit_3_len_13_qs) - ); - - - // F[len_14]: 23:16 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_3_len_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_3_len_14_we), - .wd (len_limit_3_len_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[14].q ), - - // to register interface (read) - .qs (len_limit_3_len_14_qs) - ); - - - // F[len_15]: 31:24 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_3_len_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_3_len_15_we), - .wd (len_limit_3_len_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[15].q ), - - // to register interface (read) - .qs (len_limit_3_len_15_qs) - ); - - - // Subregister 16 of Multireg len_limit - // R[len_limit_4]: V(False) - - // F[len_16]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_4_len_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_4_len_16_we), - .wd (len_limit_4_len_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[16].q ), - - // to register interface (read) - .qs (len_limit_4_len_16_qs) - ); - - - // F[len_17]: 15:8 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_4_len_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_4_len_17_we), - .wd (len_limit_4_len_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[17].q ), - - // to register interface (read) - .qs (len_limit_4_len_17_qs) - ); - - - // F[len_18]: 23:16 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_4_len_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_4_len_18_we), - .wd (len_limit_4_len_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[18].q ), - - // to register interface (read) - .qs (len_limit_4_len_18_qs) - ); - - - // F[len_19]: 31:24 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_4_len_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_4_len_19_we), - .wd (len_limit_4_len_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[19].q ), - - // to register interface (read) - .qs (len_limit_4_len_19_qs) - ); - - - // Subregister 20 of Multireg len_limit - // R[len_limit_5]: V(False) - - // F[len_20]: 7:0 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_5_len_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_5_len_20_we), - .wd (len_limit_5_len_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[20].q ), - - // to register interface (read) - .qs (len_limit_5_len_20_qs) - ); - - - // F[len_21]: 15:8 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_5_len_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_5_len_21_we), - .wd (len_limit_5_len_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[21].q ), - - // to register interface (read) - .qs (len_limit_5_len_21_qs) - ); - - - // F[len_22]: 23:16 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_5_len_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_5_len_22_we), - .wd (len_limit_5_len_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[22].q ), - - // to register interface (read) - .qs (len_limit_5_len_22_qs) - ); - - - // F[len_23]: 31:24 - prim_subreg #( - .DW (8), - .SWACCESS("RW"), - .RESVAL (8'h0) - ) u_len_limit_5_len_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (len_limit_5_len_23_we), - .wd (len_limit_5_len_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.len_limit[23].q ), - - // to register interface (read) - .qs (len_limit_5_len_23_qs) - ); - - - - - // Subregister 0 of Multireg imtu_enable - // R[imtu_enable]: V(False) - - // F[enable_0]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_0_we), - .wd (imtu_enable_enable_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[0].q ), - - // to register interface (read) - .qs (imtu_enable_enable_0_qs) - ); - - - // F[enable_1]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_1_we), - .wd (imtu_enable_enable_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[1].q ), - - // to register interface (read) - .qs (imtu_enable_enable_1_qs) - ); - - - // F[enable_2]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_2_we), - .wd (imtu_enable_enable_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[2].q ), - - // to register interface (read) - .qs (imtu_enable_enable_2_qs) - ); - - - // F[enable_3]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_3_we), - .wd (imtu_enable_enable_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[3].q ), - - // to register interface (read) - .qs (imtu_enable_enable_3_qs) - ); - - - // F[enable_4]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_4_we), - .wd (imtu_enable_enable_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[4].q ), - - // to register interface (read) - .qs (imtu_enable_enable_4_qs) - ); - - - // F[enable_5]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_5_we), - .wd (imtu_enable_enable_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[5].q ), - - // to register interface (read) - .qs (imtu_enable_enable_5_qs) - ); - - - // F[enable_6]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_6_we), - .wd (imtu_enable_enable_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[6].q ), - - // to register interface (read) - .qs (imtu_enable_enable_6_qs) - ); - - - // F[enable_7]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_7_we), - .wd (imtu_enable_enable_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[7].q ), - - // to register interface (read) - .qs (imtu_enable_enable_7_qs) - ); - - - // F[enable_8]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_8_we), - .wd (imtu_enable_enable_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[8].q ), - - // to register interface (read) - .qs (imtu_enable_enable_8_qs) - ); - - - // F[enable_9]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_9_we), - .wd (imtu_enable_enable_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[9].q ), - - // to register interface (read) - .qs (imtu_enable_enable_9_qs) - ); - - - // F[enable_10]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_10_we), - .wd (imtu_enable_enable_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[10].q ), - - // to register interface (read) - .qs (imtu_enable_enable_10_qs) - ); - - - // F[enable_11]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_11_we), - .wd (imtu_enable_enable_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[11].q ), - - // to register interface (read) - .qs (imtu_enable_enable_11_qs) - ); - - - // F[enable_12]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_12_we), - .wd (imtu_enable_enable_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[12].q ), - - // to register interface (read) - .qs (imtu_enable_enable_12_qs) - ); - - - // F[enable_13]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_13_we), - .wd (imtu_enable_enable_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[13].q ), - - // to register interface (read) - .qs (imtu_enable_enable_13_qs) - ); - - - // F[enable_14]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_14_we), - .wd (imtu_enable_enable_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[14].q ), - - // to register interface (read) - .qs (imtu_enable_enable_14_qs) - ); - - - // F[enable_15]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_15_we), - .wd (imtu_enable_enable_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[15].q ), - - // to register interface (read) - .qs (imtu_enable_enable_15_qs) - ); - - - // F[enable_16]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_16_we), - .wd (imtu_enable_enable_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[16].q ), - - // to register interface (read) - .qs (imtu_enable_enable_16_qs) - ); - - - // F[enable_17]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_17_we), - .wd (imtu_enable_enable_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[17].q ), - - // to register interface (read) - .qs (imtu_enable_enable_17_qs) - ); - - - // F[enable_18]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_18_we), - .wd (imtu_enable_enable_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[18].q ), - - // to register interface (read) - .qs (imtu_enable_enable_18_qs) - ); - - - // F[enable_19]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_19_we), - .wd (imtu_enable_enable_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[19].q ), - - // to register interface (read) - .qs (imtu_enable_enable_19_qs) - ); - - - // F[enable_20]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_20_we), - .wd (imtu_enable_enable_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[20].q ), - - // to register interface (read) - .qs (imtu_enable_enable_20_qs) - ); - - - // F[enable_21]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_21_we), - .wd (imtu_enable_enable_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[21].q ), - - // to register interface (read) - .qs (imtu_enable_enable_21_qs) - ); - - - // F[enable_22]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_22_we), - .wd (imtu_enable_enable_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[22].q ), - - // to register interface (read) - .qs (imtu_enable_enable_22_qs) - ); - - - // F[enable_23]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_enable_enable_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_enable_enable_23_we), - .wd (imtu_enable_enable_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_enable[23].q ), - - // to register interface (read) - .qs (imtu_enable_enable_23_qs) - ); - - - - - // Subregister 0 of Multireg imtu_abort - // R[imtu_abort]: V(False) - - // F[abort_0]: 0:0 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_0_we), - .wd (imtu_abort_abort_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[0].q ), - - // to register interface (read) - .qs (imtu_abort_abort_0_qs) - ); - - - // F[abort_1]: 1:1 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_1_we), - .wd (imtu_abort_abort_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[1].q ), - - // to register interface (read) - .qs (imtu_abort_abort_1_qs) - ); - - - // F[abort_2]: 2:2 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_2_we), - .wd (imtu_abort_abort_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[2].q ), - - // to register interface (read) - .qs (imtu_abort_abort_2_qs) - ); - - - // F[abort_3]: 3:3 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_3_we), - .wd (imtu_abort_abort_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[3].q ), - - // to register interface (read) - .qs (imtu_abort_abort_3_qs) - ); - - - // F[abort_4]: 4:4 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_4_we), - .wd (imtu_abort_abort_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[4].q ), - - // to register interface (read) - .qs (imtu_abort_abort_4_qs) - ); - - - // F[abort_5]: 5:5 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_5_we), - .wd (imtu_abort_abort_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[5].q ), - - // to register interface (read) - .qs (imtu_abort_abort_5_qs) - ); - - - // F[abort_6]: 6:6 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_6_we), - .wd (imtu_abort_abort_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[6].q ), - - // to register interface (read) - .qs (imtu_abort_abort_6_qs) - ); - - - // F[abort_7]: 7:7 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_7_we), - .wd (imtu_abort_abort_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[7].q ), - - // to register interface (read) - .qs (imtu_abort_abort_7_qs) - ); - - - // F[abort_8]: 8:8 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_8_we), - .wd (imtu_abort_abort_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[8].q ), - - // to register interface (read) - .qs (imtu_abort_abort_8_qs) - ); - - - // F[abort_9]: 9:9 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_9_we), - .wd (imtu_abort_abort_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[9].q ), - - // to register interface (read) - .qs (imtu_abort_abort_9_qs) - ); - - - // F[abort_10]: 10:10 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_10_we), - .wd (imtu_abort_abort_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[10].q ), - - // to register interface (read) - .qs (imtu_abort_abort_10_qs) - ); - - - // F[abort_11]: 11:11 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_11_we), - .wd (imtu_abort_abort_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[11].q ), - - // to register interface (read) - .qs (imtu_abort_abort_11_qs) - ); - - - // F[abort_12]: 12:12 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_12_we), - .wd (imtu_abort_abort_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[12].q ), - - // to register interface (read) - .qs (imtu_abort_abort_12_qs) - ); - - - // F[abort_13]: 13:13 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_13_we), - .wd (imtu_abort_abort_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[13].q ), - - // to register interface (read) - .qs (imtu_abort_abort_13_qs) - ); - - - // F[abort_14]: 14:14 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_14_we), - .wd (imtu_abort_abort_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[14].q ), - - // to register interface (read) - .qs (imtu_abort_abort_14_qs) - ); - - - // F[abort_15]: 15:15 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_15_we), - .wd (imtu_abort_abort_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[15].q ), - - // to register interface (read) - .qs (imtu_abort_abort_15_qs) - ); - - - // F[abort_16]: 16:16 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_16_we), - .wd (imtu_abort_abort_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[16].q ), - - // to register interface (read) - .qs (imtu_abort_abort_16_qs) - ); - - - // F[abort_17]: 17:17 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_17_we), - .wd (imtu_abort_abort_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[17].q ), - - // to register interface (read) - .qs (imtu_abort_abort_17_qs) - ); - - - // F[abort_18]: 18:18 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_18_we), - .wd (imtu_abort_abort_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[18].q ), - - // to register interface (read) - .qs (imtu_abort_abort_18_qs) - ); - - - // F[abort_19]: 19:19 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_19_we), - .wd (imtu_abort_abort_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[19].q ), - - // to register interface (read) - .qs (imtu_abort_abort_19_qs) - ); - - - // F[abort_20]: 20:20 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_20_we), - .wd (imtu_abort_abort_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[20].q ), - - // to register interface (read) - .qs (imtu_abort_abort_20_qs) - ); - - - // F[abort_21]: 21:21 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_21_we), - .wd (imtu_abort_abort_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[21].q ), - - // to register interface (read) - .qs (imtu_abort_abort_21_qs) - ); - - - // F[abort_22]: 22:22 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_22_we), - .wd (imtu_abort_abort_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[22].q ), - - // to register interface (read) - .qs (imtu_abort_abort_22_qs) - ); - - - // F[abort_23]: 23:23 - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h0) - ) u_imtu_abort_abort_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (imtu_abort_abort_23_we), - .wd (imtu_abort_abort_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.imtu_abort[23].q ), - - // to register interface (read) - .qs (imtu_abort_abort_23_qs) - ); - - - - - // Subregister 0 of Multireg write_budget - // R[write_budget_0]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_0_we), - .wd (write_budget_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[0].q ), - - // to register interface (read) - .qs (write_budget_0_qs) - ); - - // Subregister 1 of Multireg write_budget - // R[write_budget_1]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_1_we), - .wd (write_budget_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[1].q ), - - // to register interface (read) - .qs (write_budget_1_qs) - ); - - // Subregister 2 of Multireg write_budget - // R[write_budget_2]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_2_we), - .wd (write_budget_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[2].q ), - - // to register interface (read) - .qs (write_budget_2_qs) - ); - - // Subregister 3 of Multireg write_budget - // R[write_budget_3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_3_we), - .wd (write_budget_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[3].q ), - - // to register interface (read) - .qs (write_budget_3_qs) - ); - - // Subregister 4 of Multireg write_budget - // R[write_budget_4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_4_we), - .wd (write_budget_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[4].q ), - - // to register interface (read) - .qs (write_budget_4_qs) - ); - - // Subregister 5 of Multireg write_budget - // R[write_budget_5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_5_we), - .wd (write_budget_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[5].q ), - - // to register interface (read) - .qs (write_budget_5_qs) - ); - - // Subregister 6 of Multireg write_budget - // R[write_budget_6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_6_we), - .wd (write_budget_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[6].q ), - - // to register interface (read) - .qs (write_budget_6_qs) - ); - - // Subregister 7 of Multireg write_budget - // R[write_budget_7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_7_we), - .wd (write_budget_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[7].q ), - - // to register interface (read) - .qs (write_budget_7_qs) - ); - - // Subregister 8 of Multireg write_budget - // R[write_budget_8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_8_we), - .wd (write_budget_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[8].q ), - - // to register interface (read) - .qs (write_budget_8_qs) - ); - - // Subregister 9 of Multireg write_budget - // R[write_budget_9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_9_we), - .wd (write_budget_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[9].q ), - - // to register interface (read) - .qs (write_budget_9_qs) - ); - - // Subregister 10 of Multireg write_budget - // R[write_budget_10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_10_we), - .wd (write_budget_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[10].q ), - - // to register interface (read) - .qs (write_budget_10_qs) - ); - - // Subregister 11 of Multireg write_budget - // R[write_budget_11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_11_we), - .wd (write_budget_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[11].q ), - - // to register interface (read) - .qs (write_budget_11_qs) - ); - - // Subregister 12 of Multireg write_budget - // R[write_budget_12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_12_we), - .wd (write_budget_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[12].q ), - - // to register interface (read) - .qs (write_budget_12_qs) - ); - - // Subregister 13 of Multireg write_budget - // R[write_budget_13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_13_we), - .wd (write_budget_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[13].q ), - - // to register interface (read) - .qs (write_budget_13_qs) - ); - - // Subregister 14 of Multireg write_budget - // R[write_budget_14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_14_we), - .wd (write_budget_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[14].q ), - - // to register interface (read) - .qs (write_budget_14_qs) - ); - - // Subregister 15 of Multireg write_budget - // R[write_budget_15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_15_we), - .wd (write_budget_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[15].q ), - - // to register interface (read) - .qs (write_budget_15_qs) - ); - - // Subregister 16 of Multireg write_budget - // R[write_budget_16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_16_we), - .wd (write_budget_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[16].q ), - - // to register interface (read) - .qs (write_budget_16_qs) - ); - - // Subregister 17 of Multireg write_budget - // R[write_budget_17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_17_we), - .wd (write_budget_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[17].q ), - - // to register interface (read) - .qs (write_budget_17_qs) - ); - - // Subregister 18 of Multireg write_budget - // R[write_budget_18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_18_we), - .wd (write_budget_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[18].q ), - - // to register interface (read) - .qs (write_budget_18_qs) - ); - - // Subregister 19 of Multireg write_budget - // R[write_budget_19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_19_we), - .wd (write_budget_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[19].q ), - - // to register interface (read) - .qs (write_budget_19_qs) - ); - - // Subregister 20 of Multireg write_budget - // R[write_budget_20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_20_we), - .wd (write_budget_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[20].q ), - - // to register interface (read) - .qs (write_budget_20_qs) - ); - - // Subregister 21 of Multireg write_budget - // R[write_budget_21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_21_we), - .wd (write_budget_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[21].q ), - - // to register interface (read) - .qs (write_budget_21_qs) - ); - - // Subregister 22 of Multireg write_budget - // R[write_budget_22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_22_we), - .wd (write_budget_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[22].q ), - - // to register interface (read) - .qs (write_budget_22_qs) - ); - - // Subregister 23 of Multireg write_budget - // R[write_budget_23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_budget_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_budget_23_we), - .wd (write_budget_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_budget[23].q ), - - // to register interface (read) - .qs (write_budget_23_qs) - ); - - - - // Subregister 0 of Multireg read_budget - // R[read_budget_0]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_0_we), - .wd (read_budget_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[0].q ), - - // to register interface (read) - .qs (read_budget_0_qs) - ); - - // Subregister 1 of Multireg read_budget - // R[read_budget_1]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_1_we), - .wd (read_budget_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[1].q ), - - // to register interface (read) - .qs (read_budget_1_qs) - ); - - // Subregister 2 of Multireg read_budget - // R[read_budget_2]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_2_we), - .wd (read_budget_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[2].q ), - - // to register interface (read) - .qs (read_budget_2_qs) - ); - - // Subregister 3 of Multireg read_budget - // R[read_budget_3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_3_we), - .wd (read_budget_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[3].q ), - - // to register interface (read) - .qs (read_budget_3_qs) - ); - - // Subregister 4 of Multireg read_budget - // R[read_budget_4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_4_we), - .wd (read_budget_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[4].q ), - - // to register interface (read) - .qs (read_budget_4_qs) - ); - - // Subregister 5 of Multireg read_budget - // R[read_budget_5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_5_we), - .wd (read_budget_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[5].q ), - - // to register interface (read) - .qs (read_budget_5_qs) - ); - - // Subregister 6 of Multireg read_budget - // R[read_budget_6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_6_we), - .wd (read_budget_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[6].q ), - - // to register interface (read) - .qs (read_budget_6_qs) - ); - - // Subregister 7 of Multireg read_budget - // R[read_budget_7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_7_we), - .wd (read_budget_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[7].q ), - - // to register interface (read) - .qs (read_budget_7_qs) - ); - - // Subregister 8 of Multireg read_budget - // R[read_budget_8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_8_we), - .wd (read_budget_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[8].q ), - - // to register interface (read) - .qs (read_budget_8_qs) - ); - - // Subregister 9 of Multireg read_budget - // R[read_budget_9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_9_we), - .wd (read_budget_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[9].q ), - - // to register interface (read) - .qs (read_budget_9_qs) - ); - - // Subregister 10 of Multireg read_budget - // R[read_budget_10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_10_we), - .wd (read_budget_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[10].q ), - - // to register interface (read) - .qs (read_budget_10_qs) - ); - - // Subregister 11 of Multireg read_budget - // R[read_budget_11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_11_we), - .wd (read_budget_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[11].q ), - - // to register interface (read) - .qs (read_budget_11_qs) - ); - - // Subregister 12 of Multireg read_budget - // R[read_budget_12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_12_we), - .wd (read_budget_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[12].q ), - - // to register interface (read) - .qs (read_budget_12_qs) - ); - - // Subregister 13 of Multireg read_budget - // R[read_budget_13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_13_we), - .wd (read_budget_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[13].q ), - - // to register interface (read) - .qs (read_budget_13_qs) - ); - - // Subregister 14 of Multireg read_budget - // R[read_budget_14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_14_we), - .wd (read_budget_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[14].q ), - - // to register interface (read) - .qs (read_budget_14_qs) - ); - - // Subregister 15 of Multireg read_budget - // R[read_budget_15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_15_we), - .wd (read_budget_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[15].q ), - - // to register interface (read) - .qs (read_budget_15_qs) - ); - - // Subregister 16 of Multireg read_budget - // R[read_budget_16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_16_we), - .wd (read_budget_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[16].q ), - - // to register interface (read) - .qs (read_budget_16_qs) - ); - - // Subregister 17 of Multireg read_budget - // R[read_budget_17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_17_we), - .wd (read_budget_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[17].q ), - - // to register interface (read) - .qs (read_budget_17_qs) - ); - - // Subregister 18 of Multireg read_budget - // R[read_budget_18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_18_we), - .wd (read_budget_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[18].q ), - - // to register interface (read) - .qs (read_budget_18_qs) - ); - - // Subregister 19 of Multireg read_budget - // R[read_budget_19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_19_we), - .wd (read_budget_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[19].q ), - - // to register interface (read) - .qs (read_budget_19_qs) - ); - - // Subregister 20 of Multireg read_budget - // R[read_budget_20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_20_we), - .wd (read_budget_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[20].q ), - - // to register interface (read) - .qs (read_budget_20_qs) - ); - - // Subregister 21 of Multireg read_budget - // R[read_budget_21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_21_we), - .wd (read_budget_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[21].q ), - - // to register interface (read) - .qs (read_budget_21_qs) - ); - - // Subregister 22 of Multireg read_budget - // R[read_budget_22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_22_we), - .wd (read_budget_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[22].q ), - - // to register interface (read) - .qs (read_budget_22_qs) - ); - - // Subregister 23 of Multireg read_budget - // R[read_budget_23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_budget_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_budget_23_we), - .wd (read_budget_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_budget[23].q ), - - // to register interface (read) - .qs (read_budget_23_qs) - ); - - - - // Subregister 0 of Multireg write_period - // R[write_period_0]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_0_we), - .wd (write_period_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[0].q ), - - // to register interface (read) - .qs (write_period_0_qs) - ); - - // Subregister 1 of Multireg write_period - // R[write_period_1]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_1_we), - .wd (write_period_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[1].q ), - - // to register interface (read) - .qs (write_period_1_qs) - ); - - // Subregister 2 of Multireg write_period - // R[write_period_2]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_2_we), - .wd (write_period_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[2].q ), - - // to register interface (read) - .qs (write_period_2_qs) - ); - - // Subregister 3 of Multireg write_period - // R[write_period_3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_3_we), - .wd (write_period_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[3].q ), - - // to register interface (read) - .qs (write_period_3_qs) - ); - - // Subregister 4 of Multireg write_period - // R[write_period_4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_4_we), - .wd (write_period_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[4].q ), - - // to register interface (read) - .qs (write_period_4_qs) - ); - - // Subregister 5 of Multireg write_period - // R[write_period_5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_5_we), - .wd (write_period_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[5].q ), - - // to register interface (read) - .qs (write_period_5_qs) - ); - - // Subregister 6 of Multireg write_period - // R[write_period_6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_6_we), - .wd (write_period_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[6].q ), - - // to register interface (read) - .qs (write_period_6_qs) - ); - - // Subregister 7 of Multireg write_period - // R[write_period_7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_7_we), - .wd (write_period_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[7].q ), - - // to register interface (read) - .qs (write_period_7_qs) - ); - - // Subregister 8 of Multireg write_period - // R[write_period_8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_8_we), - .wd (write_period_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[8].q ), - - // to register interface (read) - .qs (write_period_8_qs) - ); - - // Subregister 9 of Multireg write_period - // R[write_period_9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_9_we), - .wd (write_period_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[9].q ), - - // to register interface (read) - .qs (write_period_9_qs) - ); - - // Subregister 10 of Multireg write_period - // R[write_period_10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_10_we), - .wd (write_period_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[10].q ), - - // to register interface (read) - .qs (write_period_10_qs) - ); - - // Subregister 11 of Multireg write_period - // R[write_period_11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_11_we), - .wd (write_period_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[11].q ), - - // to register interface (read) - .qs (write_period_11_qs) - ); - - // Subregister 12 of Multireg write_period - // R[write_period_12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_12_we), - .wd (write_period_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[12].q ), - - // to register interface (read) - .qs (write_period_12_qs) - ); - - // Subregister 13 of Multireg write_period - // R[write_period_13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_13_we), - .wd (write_period_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[13].q ), - - // to register interface (read) - .qs (write_period_13_qs) - ); - - // Subregister 14 of Multireg write_period - // R[write_period_14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_14_we), - .wd (write_period_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[14].q ), - - // to register interface (read) - .qs (write_period_14_qs) - ); - - // Subregister 15 of Multireg write_period - // R[write_period_15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_15_we), - .wd (write_period_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[15].q ), - - // to register interface (read) - .qs (write_period_15_qs) - ); - - // Subregister 16 of Multireg write_period - // R[write_period_16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_16_we), - .wd (write_period_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[16].q ), - - // to register interface (read) - .qs (write_period_16_qs) - ); - - // Subregister 17 of Multireg write_period - // R[write_period_17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_17_we), - .wd (write_period_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[17].q ), - - // to register interface (read) - .qs (write_period_17_qs) - ); - - // Subregister 18 of Multireg write_period - // R[write_period_18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_18_we), - .wd (write_period_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[18].q ), - - // to register interface (read) - .qs (write_period_18_qs) - ); - - // Subregister 19 of Multireg write_period - // R[write_period_19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_19_we), - .wd (write_period_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[19].q ), - - // to register interface (read) - .qs (write_period_19_qs) - ); - - // Subregister 20 of Multireg write_period - // R[write_period_20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_20_we), - .wd (write_period_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[20].q ), - - // to register interface (read) - .qs (write_period_20_qs) - ); - - // Subregister 21 of Multireg write_period - // R[write_period_21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_21_we), - .wd (write_period_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[21].q ), - - // to register interface (read) - .qs (write_period_21_qs) - ); - - // Subregister 22 of Multireg write_period - // R[write_period_22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_22_we), - .wd (write_period_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[22].q ), - - // to register interface (read) - .qs (write_period_22_qs) - ); - - // Subregister 23 of Multireg write_period - // R[write_period_23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_write_period_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (write_period_23_we), - .wd (write_period_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.write_period[23].q ), - - // to register interface (read) - .qs (write_period_23_qs) - ); - - - - // Subregister 0 of Multireg read_period - // R[read_period_0]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_0 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_0_we), - .wd (read_period_0_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[0].q ), - - // to register interface (read) - .qs (read_period_0_qs) - ); - - // Subregister 1 of Multireg read_period - // R[read_period_1]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_1 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_1_we), - .wd (read_period_1_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[1].q ), - - // to register interface (read) - .qs (read_period_1_qs) - ); - - // Subregister 2 of Multireg read_period - // R[read_period_2]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_2 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_2_we), - .wd (read_period_2_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[2].q ), - - // to register interface (read) - .qs (read_period_2_qs) - ); - - // Subregister 3 of Multireg read_period - // R[read_period_3]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_3 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_3_we), - .wd (read_period_3_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[3].q ), - - // to register interface (read) - .qs (read_period_3_qs) - ); - - // Subregister 4 of Multireg read_period - // R[read_period_4]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_4 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_4_we), - .wd (read_period_4_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[4].q ), - - // to register interface (read) - .qs (read_period_4_qs) - ); - - // Subregister 5 of Multireg read_period - // R[read_period_5]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_5 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_5_we), - .wd (read_period_5_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[5].q ), - - // to register interface (read) - .qs (read_period_5_qs) - ); - - // Subregister 6 of Multireg read_period - // R[read_period_6]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_6 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_6_we), - .wd (read_period_6_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[6].q ), - - // to register interface (read) - .qs (read_period_6_qs) - ); - - // Subregister 7 of Multireg read_period - // R[read_period_7]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_7 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_7_we), - .wd (read_period_7_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[7].q ), - - // to register interface (read) - .qs (read_period_7_qs) - ); - - // Subregister 8 of Multireg read_period - // R[read_period_8]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_8 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_8_we), - .wd (read_period_8_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[8].q ), - - // to register interface (read) - .qs (read_period_8_qs) - ); - - // Subregister 9 of Multireg read_period - // R[read_period_9]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_9 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_9_we), - .wd (read_period_9_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[9].q ), - - // to register interface (read) - .qs (read_period_9_qs) - ); - - // Subregister 10 of Multireg read_period - // R[read_period_10]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_10 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_10_we), - .wd (read_period_10_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[10].q ), - - // to register interface (read) - .qs (read_period_10_qs) - ); - - // Subregister 11 of Multireg read_period - // R[read_period_11]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_11 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_11_we), - .wd (read_period_11_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[11].q ), - - // to register interface (read) - .qs (read_period_11_qs) - ); - - // Subregister 12 of Multireg read_period - // R[read_period_12]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_12 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_12_we), - .wd (read_period_12_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[12].q ), - - // to register interface (read) - .qs (read_period_12_qs) - ); - - // Subregister 13 of Multireg read_period - // R[read_period_13]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_13 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_13_we), - .wd (read_period_13_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[13].q ), - - // to register interface (read) - .qs (read_period_13_qs) - ); - - // Subregister 14 of Multireg read_period - // R[read_period_14]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_14 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_14_we), - .wd (read_period_14_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[14].q ), - - // to register interface (read) - .qs (read_period_14_qs) - ); - - // Subregister 15 of Multireg read_period - // R[read_period_15]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_15 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_15_we), - .wd (read_period_15_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[15].q ), - - // to register interface (read) - .qs (read_period_15_qs) - ); - - // Subregister 16 of Multireg read_period - // R[read_period_16]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_16 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_16_we), - .wd (read_period_16_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[16].q ), - - // to register interface (read) - .qs (read_period_16_qs) - ); - - // Subregister 17 of Multireg read_period - // R[read_period_17]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_17 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_17_we), - .wd (read_period_17_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[17].q ), - - // to register interface (read) - .qs (read_period_17_qs) - ); - - // Subregister 18 of Multireg read_period - // R[read_period_18]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_18 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_18_we), - .wd (read_period_18_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[18].q ), - - // to register interface (read) - .qs (read_period_18_qs) - ); - - // Subregister 19 of Multireg read_period - // R[read_period_19]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_19 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_19_we), - .wd (read_period_19_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[19].q ), - - // to register interface (read) - .qs (read_period_19_qs) - ); - - // Subregister 20 of Multireg read_period - // R[read_period_20]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_20 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_20_we), - .wd (read_period_20_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[20].q ), - - // to register interface (read) - .qs (read_period_20_qs) - ); - - // Subregister 21 of Multireg read_period - // R[read_period_21]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_21 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_21_we), - .wd (read_period_21_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[21].q ), - - // to register interface (read) - .qs (read_period_21_qs) - ); - - // Subregister 22 of Multireg read_period - // R[read_period_22]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_22 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_22_we), - .wd (read_period_22_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[22].q ), - - // to register interface (read) - .qs (read_period_22_qs) - ); - - // Subregister 23 of Multireg read_period - // R[read_period_23]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RW"), - .RESVAL (32'h0) - ) u_read_period_23 ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface - .we (read_period_23_we), - .wd (read_period_23_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.read_period[23].q ), - - // to register interface (read) - .qs (read_period_23_qs) - ); - - - - // Subregister 0 of Multireg write_budget_left - // R[write_budget_left_0]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_0 ( - .re (write_budget_left_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[0].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_0_qs) - ); - - // Subregister 1 of Multireg write_budget_left - // R[write_budget_left_1]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_1 ( - .re (write_budget_left_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[1].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_1_qs) - ); - - // Subregister 2 of Multireg write_budget_left - // R[write_budget_left_2]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_2 ( - .re (write_budget_left_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[2].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_2_qs) - ); - - // Subregister 3 of Multireg write_budget_left - // R[write_budget_left_3]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_3 ( - .re (write_budget_left_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[3].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_3_qs) - ); - - // Subregister 4 of Multireg write_budget_left - // R[write_budget_left_4]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_4 ( - .re (write_budget_left_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[4].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_4_qs) - ); - - // Subregister 5 of Multireg write_budget_left - // R[write_budget_left_5]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_5 ( - .re (write_budget_left_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[5].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_5_qs) - ); - - // Subregister 6 of Multireg write_budget_left - // R[write_budget_left_6]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_6 ( - .re (write_budget_left_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[6].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_6_qs) - ); - - // Subregister 7 of Multireg write_budget_left - // R[write_budget_left_7]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_7 ( - .re (write_budget_left_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[7].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_7_qs) - ); - - // Subregister 8 of Multireg write_budget_left - // R[write_budget_left_8]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_8 ( - .re (write_budget_left_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[8].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_8_qs) - ); - - // Subregister 9 of Multireg write_budget_left - // R[write_budget_left_9]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_9 ( - .re (write_budget_left_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[9].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_9_qs) - ); - - // Subregister 10 of Multireg write_budget_left - // R[write_budget_left_10]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_10 ( - .re (write_budget_left_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[10].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_10_qs) - ); - - // Subregister 11 of Multireg write_budget_left - // R[write_budget_left_11]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_11 ( - .re (write_budget_left_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[11].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_11_qs) - ); - - // Subregister 12 of Multireg write_budget_left - // R[write_budget_left_12]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_12 ( - .re (write_budget_left_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[12].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_12_qs) - ); - - // Subregister 13 of Multireg write_budget_left - // R[write_budget_left_13]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_13 ( - .re (write_budget_left_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[13].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_13_qs) - ); - - // Subregister 14 of Multireg write_budget_left - // R[write_budget_left_14]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_14 ( - .re (write_budget_left_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[14].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_14_qs) - ); - - // Subregister 15 of Multireg write_budget_left - // R[write_budget_left_15]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_15 ( - .re (write_budget_left_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[15].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_15_qs) - ); - - // Subregister 16 of Multireg write_budget_left - // R[write_budget_left_16]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_16 ( - .re (write_budget_left_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[16].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_16_qs) - ); - - // Subregister 17 of Multireg write_budget_left - // R[write_budget_left_17]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_17 ( - .re (write_budget_left_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[17].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_17_qs) - ); - - // Subregister 18 of Multireg write_budget_left - // R[write_budget_left_18]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_18 ( - .re (write_budget_left_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[18].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_18_qs) - ); - - // Subregister 19 of Multireg write_budget_left - // R[write_budget_left_19]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_19 ( - .re (write_budget_left_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[19].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_19_qs) - ); - - // Subregister 20 of Multireg write_budget_left - // R[write_budget_left_20]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_20 ( - .re (write_budget_left_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[20].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_20_qs) - ); - - // Subregister 21 of Multireg write_budget_left - // R[write_budget_left_21]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_21 ( - .re (write_budget_left_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[21].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_21_qs) - ); - - // Subregister 22 of Multireg write_budget_left - // R[write_budget_left_22]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_22 ( - .re (write_budget_left_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[22].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_22_qs) - ); - - // Subregister 23 of Multireg write_budget_left - // R[write_budget_left_23]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_budget_left_23 ( - .re (write_budget_left_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_budget_left[23].d), - .qre (), - .qe (), - .q (), - .qs (write_budget_left_23_qs) - ); - - - - // Subregister 0 of Multireg read_budget_left - // R[read_budget_left_0]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_0 ( - .re (read_budget_left_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[0].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_0_qs) - ); - - // Subregister 1 of Multireg read_budget_left - // R[read_budget_left_1]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_1 ( - .re (read_budget_left_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[1].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_1_qs) - ); - - // Subregister 2 of Multireg read_budget_left - // R[read_budget_left_2]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_2 ( - .re (read_budget_left_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[2].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_2_qs) - ); - - // Subregister 3 of Multireg read_budget_left - // R[read_budget_left_3]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_3 ( - .re (read_budget_left_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[3].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_3_qs) - ); - - // Subregister 4 of Multireg read_budget_left - // R[read_budget_left_4]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_4 ( - .re (read_budget_left_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[4].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_4_qs) - ); - - // Subregister 5 of Multireg read_budget_left - // R[read_budget_left_5]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_5 ( - .re (read_budget_left_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[5].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_5_qs) - ); - - // Subregister 6 of Multireg read_budget_left - // R[read_budget_left_6]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_6 ( - .re (read_budget_left_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[6].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_6_qs) - ); - - // Subregister 7 of Multireg read_budget_left - // R[read_budget_left_7]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_7 ( - .re (read_budget_left_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[7].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_7_qs) - ); - - // Subregister 8 of Multireg read_budget_left - // R[read_budget_left_8]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_8 ( - .re (read_budget_left_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[8].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_8_qs) - ); - - // Subregister 9 of Multireg read_budget_left - // R[read_budget_left_9]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_9 ( - .re (read_budget_left_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[9].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_9_qs) - ); - - // Subregister 10 of Multireg read_budget_left - // R[read_budget_left_10]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_10 ( - .re (read_budget_left_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[10].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_10_qs) - ); - - // Subregister 11 of Multireg read_budget_left - // R[read_budget_left_11]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_11 ( - .re (read_budget_left_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[11].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_11_qs) - ); - - // Subregister 12 of Multireg read_budget_left - // R[read_budget_left_12]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_12 ( - .re (read_budget_left_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[12].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_12_qs) - ); - - // Subregister 13 of Multireg read_budget_left - // R[read_budget_left_13]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_13 ( - .re (read_budget_left_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[13].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_13_qs) - ); - - // Subregister 14 of Multireg read_budget_left - // R[read_budget_left_14]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_14 ( - .re (read_budget_left_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[14].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_14_qs) - ); - - // Subregister 15 of Multireg read_budget_left - // R[read_budget_left_15]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_15 ( - .re (read_budget_left_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[15].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_15_qs) - ); - - // Subregister 16 of Multireg read_budget_left - // R[read_budget_left_16]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_16 ( - .re (read_budget_left_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[16].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_16_qs) - ); - - // Subregister 17 of Multireg read_budget_left - // R[read_budget_left_17]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_17 ( - .re (read_budget_left_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[17].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_17_qs) - ); - - // Subregister 18 of Multireg read_budget_left - // R[read_budget_left_18]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_18 ( - .re (read_budget_left_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[18].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_18_qs) - ); - - // Subregister 19 of Multireg read_budget_left - // R[read_budget_left_19]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_19 ( - .re (read_budget_left_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[19].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_19_qs) - ); - - // Subregister 20 of Multireg read_budget_left - // R[read_budget_left_20]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_20 ( - .re (read_budget_left_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[20].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_20_qs) - ); - - // Subregister 21 of Multireg read_budget_left - // R[read_budget_left_21]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_21 ( - .re (read_budget_left_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[21].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_21_qs) - ); - - // Subregister 22 of Multireg read_budget_left - // R[read_budget_left_22]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_22 ( - .re (read_budget_left_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[22].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_22_qs) - ); - - // Subregister 23 of Multireg read_budget_left - // R[read_budget_left_23]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_budget_left_23 ( - .re (read_budget_left_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_budget_left[23].d), - .qre (), - .qe (), - .q (), - .qs (read_budget_left_23_qs) - ); - - - - // Subregister 0 of Multireg write_period_left - // R[write_period_left_0]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_0 ( - .re (write_period_left_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[0].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_0_qs) - ); - - // Subregister 1 of Multireg write_period_left - // R[write_period_left_1]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_1 ( - .re (write_period_left_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[1].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_1_qs) - ); - - // Subregister 2 of Multireg write_period_left - // R[write_period_left_2]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_2 ( - .re (write_period_left_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[2].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_2_qs) - ); - - // Subregister 3 of Multireg write_period_left - // R[write_period_left_3]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_3 ( - .re (write_period_left_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[3].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_3_qs) - ); - - // Subregister 4 of Multireg write_period_left - // R[write_period_left_4]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_4 ( - .re (write_period_left_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[4].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_4_qs) - ); - - // Subregister 5 of Multireg write_period_left - // R[write_period_left_5]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_5 ( - .re (write_period_left_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[5].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_5_qs) - ); - - // Subregister 6 of Multireg write_period_left - // R[write_period_left_6]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_6 ( - .re (write_period_left_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[6].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_6_qs) - ); - - // Subregister 7 of Multireg write_period_left - // R[write_period_left_7]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_7 ( - .re (write_period_left_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[7].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_7_qs) - ); - - // Subregister 8 of Multireg write_period_left - // R[write_period_left_8]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_8 ( - .re (write_period_left_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[8].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_8_qs) - ); - - // Subregister 9 of Multireg write_period_left - // R[write_period_left_9]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_9 ( - .re (write_period_left_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[9].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_9_qs) - ); - - // Subregister 10 of Multireg write_period_left - // R[write_period_left_10]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_10 ( - .re (write_period_left_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[10].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_10_qs) - ); - - // Subregister 11 of Multireg write_period_left - // R[write_period_left_11]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_11 ( - .re (write_period_left_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[11].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_11_qs) - ); - - // Subregister 12 of Multireg write_period_left - // R[write_period_left_12]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_12 ( - .re (write_period_left_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[12].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_12_qs) - ); - - // Subregister 13 of Multireg write_period_left - // R[write_period_left_13]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_13 ( - .re (write_period_left_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[13].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_13_qs) - ); - - // Subregister 14 of Multireg write_period_left - // R[write_period_left_14]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_14 ( - .re (write_period_left_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[14].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_14_qs) - ); - - // Subregister 15 of Multireg write_period_left - // R[write_period_left_15]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_15 ( - .re (write_period_left_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[15].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_15_qs) - ); - - // Subregister 16 of Multireg write_period_left - // R[write_period_left_16]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_16 ( - .re (write_period_left_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[16].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_16_qs) - ); - - // Subregister 17 of Multireg write_period_left - // R[write_period_left_17]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_17 ( - .re (write_period_left_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[17].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_17_qs) - ); - - // Subregister 18 of Multireg write_period_left - // R[write_period_left_18]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_18 ( - .re (write_period_left_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[18].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_18_qs) - ); - - // Subregister 19 of Multireg write_period_left - // R[write_period_left_19]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_19 ( - .re (write_period_left_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[19].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_19_qs) - ); - - // Subregister 20 of Multireg write_period_left - // R[write_period_left_20]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_20 ( - .re (write_period_left_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[20].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_20_qs) - ); - - // Subregister 21 of Multireg write_period_left - // R[write_period_left_21]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_21 ( - .re (write_period_left_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[21].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_21_qs) - ); - - // Subregister 22 of Multireg write_period_left - // R[write_period_left_22]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_22 ( - .re (write_period_left_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[22].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_22_qs) - ); - - // Subregister 23 of Multireg write_period_left - // R[write_period_left_23]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_write_period_left_23 ( - .re (write_period_left_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.write_period_left[23].d), - .qre (), - .qe (), - .q (), - .qs (write_period_left_23_qs) - ); - - - - // Subregister 0 of Multireg read_period_left - // R[read_period_left_0]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_0 ( - .re (read_period_left_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[0].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_0_qs) - ); - - // Subregister 1 of Multireg read_period_left - // R[read_period_left_1]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_1 ( - .re (read_period_left_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[1].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_1_qs) - ); - - // Subregister 2 of Multireg read_period_left - // R[read_period_left_2]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_2 ( - .re (read_period_left_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[2].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_2_qs) - ); - - // Subregister 3 of Multireg read_period_left - // R[read_period_left_3]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_3 ( - .re (read_period_left_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[3].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_3_qs) - ); - - // Subregister 4 of Multireg read_period_left - // R[read_period_left_4]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_4 ( - .re (read_period_left_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[4].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_4_qs) - ); - - // Subregister 5 of Multireg read_period_left - // R[read_period_left_5]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_5 ( - .re (read_period_left_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[5].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_5_qs) - ); - - // Subregister 6 of Multireg read_period_left - // R[read_period_left_6]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_6 ( - .re (read_period_left_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[6].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_6_qs) - ); - - // Subregister 7 of Multireg read_period_left - // R[read_period_left_7]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_7 ( - .re (read_period_left_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[7].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_7_qs) - ); - - // Subregister 8 of Multireg read_period_left - // R[read_period_left_8]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_8 ( - .re (read_period_left_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[8].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_8_qs) - ); - - // Subregister 9 of Multireg read_period_left - // R[read_period_left_9]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_9 ( - .re (read_period_left_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[9].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_9_qs) - ); - - // Subregister 10 of Multireg read_period_left - // R[read_period_left_10]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_10 ( - .re (read_period_left_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[10].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_10_qs) - ); - - // Subregister 11 of Multireg read_period_left - // R[read_period_left_11]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_11 ( - .re (read_period_left_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[11].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_11_qs) - ); - - // Subregister 12 of Multireg read_period_left - // R[read_period_left_12]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_12 ( - .re (read_period_left_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[12].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_12_qs) - ); - - // Subregister 13 of Multireg read_period_left - // R[read_period_left_13]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_13 ( - .re (read_period_left_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[13].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_13_qs) - ); - - // Subregister 14 of Multireg read_period_left - // R[read_period_left_14]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_14 ( - .re (read_period_left_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[14].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_14_qs) - ); - - // Subregister 15 of Multireg read_period_left - // R[read_period_left_15]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_15 ( - .re (read_period_left_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[15].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_15_qs) - ); - - // Subregister 16 of Multireg read_period_left - // R[read_period_left_16]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_16 ( - .re (read_period_left_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[16].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_16_qs) - ); - - // Subregister 17 of Multireg read_period_left - // R[read_period_left_17]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_17 ( - .re (read_period_left_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[17].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_17_qs) - ); - - // Subregister 18 of Multireg read_period_left - // R[read_period_left_18]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_18 ( - .re (read_period_left_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[18].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_18_qs) - ); - - // Subregister 19 of Multireg read_period_left - // R[read_period_left_19]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_19 ( - .re (read_period_left_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[19].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_19_qs) - ); - - // Subregister 20 of Multireg read_period_left - // R[read_period_left_20]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_20 ( - .re (read_period_left_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[20].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_20_qs) - ); - - // Subregister 21 of Multireg read_period_left - // R[read_period_left_21]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_21 ( - .re (read_period_left_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[21].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_21_qs) - ); - - // Subregister 22 of Multireg read_period_left - // R[read_period_left_22]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_22 ( - .re (read_period_left_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[22].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_22_qs) - ); - - // Subregister 23 of Multireg read_period_left - // R[read_period_left_23]: V(True) - - prim_subreg_ext #( - .DW (32) - ) u_read_period_left_23 ( - .re (read_period_left_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.read_period_left[23].d), - .qre (), - .qe (), - .q (), - .qs (read_period_left_23_qs) - ); - - - - // Subregister 0 of Multireg isolate - // R[isolate]: V(True) - - // F[isolate_0]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_0 ( - .re (isolate_isolate_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[0].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_0_qs) - ); - - - // F[isolate_1]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_1 ( - .re (isolate_isolate_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[1].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_1_qs) - ); - - - // F[isolate_2]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_2 ( - .re (isolate_isolate_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[2].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_2_qs) - ); - - - // F[isolate_3]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_3 ( - .re (isolate_isolate_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[3].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_3_qs) - ); - - - // F[isolate_4]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_4 ( - .re (isolate_isolate_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[4].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_4_qs) - ); - - - // F[isolate_5]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_5 ( - .re (isolate_isolate_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[5].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_5_qs) - ); - - - // F[isolate_6]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_6 ( - .re (isolate_isolate_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[6].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_6_qs) - ); - - - // F[isolate_7]: 7:7 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_7 ( - .re (isolate_isolate_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[7].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_7_qs) - ); - - - // F[isolate_8]: 8:8 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_8 ( - .re (isolate_isolate_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[8].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_8_qs) - ); - - - // F[isolate_9]: 9:9 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_9 ( - .re (isolate_isolate_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[9].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_9_qs) - ); - - - // F[isolate_10]: 10:10 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_10 ( - .re (isolate_isolate_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[10].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_10_qs) - ); - - - // F[isolate_11]: 11:11 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_11 ( - .re (isolate_isolate_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[11].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_11_qs) - ); - - - // F[isolate_12]: 12:12 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_12 ( - .re (isolate_isolate_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[12].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_12_qs) - ); - - - // F[isolate_13]: 13:13 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_13 ( - .re (isolate_isolate_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[13].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_13_qs) - ); - - - // F[isolate_14]: 14:14 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_14 ( - .re (isolate_isolate_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[14].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_14_qs) - ); - - - // F[isolate_15]: 15:15 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_15 ( - .re (isolate_isolate_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[15].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_15_qs) - ); - - - // F[isolate_16]: 16:16 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_16 ( - .re (isolate_isolate_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[16].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_16_qs) - ); - - - // F[isolate_17]: 17:17 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_17 ( - .re (isolate_isolate_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[17].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_17_qs) - ); - - - // F[isolate_18]: 18:18 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_18 ( - .re (isolate_isolate_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[18].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_18_qs) - ); - - - // F[isolate_19]: 19:19 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_19 ( - .re (isolate_isolate_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[19].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_19_qs) - ); - - - // F[isolate_20]: 20:20 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_20 ( - .re (isolate_isolate_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[20].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_20_qs) - ); - - - // F[isolate_21]: 21:21 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_21 ( - .re (isolate_isolate_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[21].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_21_qs) - ); - - - // F[isolate_22]: 22:22 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_22 ( - .re (isolate_isolate_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[22].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_22_qs) - ); - - - // F[isolate_23]: 23:23 - prim_subreg_ext #( - .DW (1) - ) u_isolate_isolate_23 ( - .re (isolate_isolate_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolate[23].d), - .qre (), - .qe (), - .q (), - .qs (isolate_isolate_23_qs) - ); - - - - - // Subregister 0 of Multireg isolated - // R[isolated]: V(True) - - // F[isolated_0]: 0:0 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_0 ( - .re (isolated_isolated_0_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[0].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_0_qs) - ); - - - // F[isolated_1]: 1:1 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_1 ( - .re (isolated_isolated_1_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[1].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_1_qs) - ); - - - // F[isolated_2]: 2:2 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_2 ( - .re (isolated_isolated_2_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[2].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_2_qs) - ); - - - // F[isolated_3]: 3:3 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_3 ( - .re (isolated_isolated_3_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[3].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_3_qs) - ); - - - // F[isolated_4]: 4:4 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_4 ( - .re (isolated_isolated_4_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[4].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_4_qs) - ); - - - // F[isolated_5]: 5:5 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_5 ( - .re (isolated_isolated_5_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[5].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_5_qs) - ); - - - // F[isolated_6]: 6:6 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_6 ( - .re (isolated_isolated_6_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[6].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_6_qs) - ); - - - // F[isolated_7]: 7:7 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_7 ( - .re (isolated_isolated_7_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[7].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_7_qs) - ); - - - // F[isolated_8]: 8:8 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_8 ( - .re (isolated_isolated_8_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[8].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_8_qs) - ); - - - // F[isolated_9]: 9:9 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_9 ( - .re (isolated_isolated_9_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[9].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_9_qs) - ); - - - // F[isolated_10]: 10:10 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_10 ( - .re (isolated_isolated_10_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[10].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_10_qs) - ); - - - // F[isolated_11]: 11:11 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_11 ( - .re (isolated_isolated_11_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[11].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_11_qs) - ); - - - // F[isolated_12]: 12:12 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_12 ( - .re (isolated_isolated_12_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[12].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_12_qs) - ); - - - // F[isolated_13]: 13:13 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_13 ( - .re (isolated_isolated_13_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[13].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_13_qs) - ); - - - // F[isolated_14]: 14:14 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_14 ( - .re (isolated_isolated_14_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[14].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_14_qs) - ); - - - // F[isolated_15]: 15:15 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_15 ( - .re (isolated_isolated_15_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[15].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_15_qs) - ); - - - // F[isolated_16]: 16:16 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_16 ( - .re (isolated_isolated_16_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[16].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_16_qs) - ); - - - // F[isolated_17]: 17:17 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_17 ( - .re (isolated_isolated_17_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[17].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_17_qs) - ); - - - // F[isolated_18]: 18:18 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_18 ( - .re (isolated_isolated_18_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[18].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_18_qs) - ); - - - // F[isolated_19]: 19:19 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_19 ( - .re (isolated_isolated_19_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[19].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_19_qs) - ); - - - // F[isolated_20]: 20:20 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_20 ( - .re (isolated_isolated_20_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[20].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_20_qs) - ); - - - // F[isolated_21]: 21:21 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_21 ( - .re (isolated_isolated_21_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[21].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_21_qs) - ); - - - // F[isolated_22]: 22:22 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_22 ( - .re (isolated_isolated_22_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[22].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_22_qs) - ); - - - // F[isolated_23]: 23:23 - prim_subreg_ext #( - .DW (1) - ) u_isolated_isolated_23 ( - .re (isolated_isolated_23_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.isolated[23].d), - .qre (), - .qe (), - .q (), - .qs (isolated_isolated_23_qs) - ); - - - - - - logic [203:0] addr_hit; - always_comb begin - addr_hit = '0; - addr_hit[ 0] = (reg_addr == AXI_RT_RT_ENABLE_OFFSET); - addr_hit[ 1] = (reg_addr == AXI_RT_RT_BYPASSED_OFFSET); - addr_hit[ 2] = (reg_addr == AXI_RT_LEN_LIMIT_0_OFFSET); - addr_hit[ 3] = (reg_addr == AXI_RT_LEN_LIMIT_1_OFFSET); - addr_hit[ 4] = (reg_addr == AXI_RT_LEN_LIMIT_2_OFFSET); - addr_hit[ 5] = (reg_addr == AXI_RT_LEN_LIMIT_3_OFFSET); - addr_hit[ 6] = (reg_addr == AXI_RT_LEN_LIMIT_4_OFFSET); - addr_hit[ 7] = (reg_addr == AXI_RT_LEN_LIMIT_5_OFFSET); - addr_hit[ 8] = (reg_addr == AXI_RT_IMTU_ENABLE_OFFSET); - addr_hit[ 9] = (reg_addr == AXI_RT_IMTU_ABORT_OFFSET); - addr_hit[ 10] = (reg_addr == AXI_RT_WRITE_BUDGET_0_OFFSET); - addr_hit[ 11] = (reg_addr == AXI_RT_WRITE_BUDGET_1_OFFSET); - addr_hit[ 12] = (reg_addr == AXI_RT_WRITE_BUDGET_2_OFFSET); - addr_hit[ 13] = (reg_addr == AXI_RT_WRITE_BUDGET_3_OFFSET); - addr_hit[ 14] = (reg_addr == AXI_RT_WRITE_BUDGET_4_OFFSET); - addr_hit[ 15] = (reg_addr == AXI_RT_WRITE_BUDGET_5_OFFSET); - addr_hit[ 16] = (reg_addr == AXI_RT_WRITE_BUDGET_6_OFFSET); - addr_hit[ 17] = (reg_addr == AXI_RT_WRITE_BUDGET_7_OFFSET); - addr_hit[ 18] = (reg_addr == AXI_RT_WRITE_BUDGET_8_OFFSET); - addr_hit[ 19] = (reg_addr == AXI_RT_WRITE_BUDGET_9_OFFSET); - addr_hit[ 20] = (reg_addr == AXI_RT_WRITE_BUDGET_10_OFFSET); - addr_hit[ 21] = (reg_addr == AXI_RT_WRITE_BUDGET_11_OFFSET); - addr_hit[ 22] = (reg_addr == AXI_RT_WRITE_BUDGET_12_OFFSET); - addr_hit[ 23] = (reg_addr == AXI_RT_WRITE_BUDGET_13_OFFSET); - addr_hit[ 24] = (reg_addr == AXI_RT_WRITE_BUDGET_14_OFFSET); - addr_hit[ 25] = (reg_addr == AXI_RT_WRITE_BUDGET_15_OFFSET); - addr_hit[ 26] = (reg_addr == AXI_RT_WRITE_BUDGET_16_OFFSET); - addr_hit[ 27] = (reg_addr == AXI_RT_WRITE_BUDGET_17_OFFSET); - addr_hit[ 28] = (reg_addr == AXI_RT_WRITE_BUDGET_18_OFFSET); - addr_hit[ 29] = (reg_addr == AXI_RT_WRITE_BUDGET_19_OFFSET); - addr_hit[ 30] = (reg_addr == AXI_RT_WRITE_BUDGET_20_OFFSET); - addr_hit[ 31] = (reg_addr == AXI_RT_WRITE_BUDGET_21_OFFSET); - addr_hit[ 32] = (reg_addr == AXI_RT_WRITE_BUDGET_22_OFFSET); - addr_hit[ 33] = (reg_addr == AXI_RT_WRITE_BUDGET_23_OFFSET); - addr_hit[ 34] = (reg_addr == AXI_RT_READ_BUDGET_0_OFFSET); - addr_hit[ 35] = (reg_addr == AXI_RT_READ_BUDGET_1_OFFSET); - addr_hit[ 36] = (reg_addr == AXI_RT_READ_BUDGET_2_OFFSET); - addr_hit[ 37] = (reg_addr == AXI_RT_READ_BUDGET_3_OFFSET); - addr_hit[ 38] = (reg_addr == AXI_RT_READ_BUDGET_4_OFFSET); - addr_hit[ 39] = (reg_addr == AXI_RT_READ_BUDGET_5_OFFSET); - addr_hit[ 40] = (reg_addr == AXI_RT_READ_BUDGET_6_OFFSET); - addr_hit[ 41] = (reg_addr == AXI_RT_READ_BUDGET_7_OFFSET); - addr_hit[ 42] = (reg_addr == AXI_RT_READ_BUDGET_8_OFFSET); - addr_hit[ 43] = (reg_addr == AXI_RT_READ_BUDGET_9_OFFSET); - addr_hit[ 44] = (reg_addr == AXI_RT_READ_BUDGET_10_OFFSET); - addr_hit[ 45] = (reg_addr == AXI_RT_READ_BUDGET_11_OFFSET); - addr_hit[ 46] = (reg_addr == AXI_RT_READ_BUDGET_12_OFFSET); - addr_hit[ 47] = (reg_addr == AXI_RT_READ_BUDGET_13_OFFSET); - addr_hit[ 48] = (reg_addr == AXI_RT_READ_BUDGET_14_OFFSET); - addr_hit[ 49] = (reg_addr == AXI_RT_READ_BUDGET_15_OFFSET); - addr_hit[ 50] = (reg_addr == AXI_RT_READ_BUDGET_16_OFFSET); - addr_hit[ 51] = (reg_addr == AXI_RT_READ_BUDGET_17_OFFSET); - addr_hit[ 52] = (reg_addr == AXI_RT_READ_BUDGET_18_OFFSET); - addr_hit[ 53] = (reg_addr == AXI_RT_READ_BUDGET_19_OFFSET); - addr_hit[ 54] = (reg_addr == AXI_RT_READ_BUDGET_20_OFFSET); - addr_hit[ 55] = (reg_addr == AXI_RT_READ_BUDGET_21_OFFSET); - addr_hit[ 56] = (reg_addr == AXI_RT_READ_BUDGET_22_OFFSET); - addr_hit[ 57] = (reg_addr == AXI_RT_READ_BUDGET_23_OFFSET); - addr_hit[ 58] = (reg_addr == AXI_RT_WRITE_PERIOD_0_OFFSET); - addr_hit[ 59] = (reg_addr == AXI_RT_WRITE_PERIOD_1_OFFSET); - addr_hit[ 60] = (reg_addr == AXI_RT_WRITE_PERIOD_2_OFFSET); - addr_hit[ 61] = (reg_addr == AXI_RT_WRITE_PERIOD_3_OFFSET); - addr_hit[ 62] = (reg_addr == AXI_RT_WRITE_PERIOD_4_OFFSET); - addr_hit[ 63] = (reg_addr == AXI_RT_WRITE_PERIOD_5_OFFSET); - addr_hit[ 64] = (reg_addr == AXI_RT_WRITE_PERIOD_6_OFFSET); - addr_hit[ 65] = (reg_addr == AXI_RT_WRITE_PERIOD_7_OFFSET); - addr_hit[ 66] = (reg_addr == AXI_RT_WRITE_PERIOD_8_OFFSET); - addr_hit[ 67] = (reg_addr == AXI_RT_WRITE_PERIOD_9_OFFSET); - addr_hit[ 68] = (reg_addr == AXI_RT_WRITE_PERIOD_10_OFFSET); - addr_hit[ 69] = (reg_addr == AXI_RT_WRITE_PERIOD_11_OFFSET); - addr_hit[ 70] = (reg_addr == AXI_RT_WRITE_PERIOD_12_OFFSET); - addr_hit[ 71] = (reg_addr == AXI_RT_WRITE_PERIOD_13_OFFSET); - addr_hit[ 72] = (reg_addr == AXI_RT_WRITE_PERIOD_14_OFFSET); - addr_hit[ 73] = (reg_addr == AXI_RT_WRITE_PERIOD_15_OFFSET); - addr_hit[ 74] = (reg_addr == AXI_RT_WRITE_PERIOD_16_OFFSET); - addr_hit[ 75] = (reg_addr == AXI_RT_WRITE_PERIOD_17_OFFSET); - addr_hit[ 76] = (reg_addr == AXI_RT_WRITE_PERIOD_18_OFFSET); - addr_hit[ 77] = (reg_addr == AXI_RT_WRITE_PERIOD_19_OFFSET); - addr_hit[ 78] = (reg_addr == AXI_RT_WRITE_PERIOD_20_OFFSET); - addr_hit[ 79] = (reg_addr == AXI_RT_WRITE_PERIOD_21_OFFSET); - addr_hit[ 80] = (reg_addr == AXI_RT_WRITE_PERIOD_22_OFFSET); - addr_hit[ 81] = (reg_addr == AXI_RT_WRITE_PERIOD_23_OFFSET); - addr_hit[ 82] = (reg_addr == AXI_RT_READ_PERIOD_0_OFFSET); - addr_hit[ 83] = (reg_addr == AXI_RT_READ_PERIOD_1_OFFSET); - addr_hit[ 84] = (reg_addr == AXI_RT_READ_PERIOD_2_OFFSET); - addr_hit[ 85] = (reg_addr == AXI_RT_READ_PERIOD_3_OFFSET); - addr_hit[ 86] = (reg_addr == AXI_RT_READ_PERIOD_4_OFFSET); - addr_hit[ 87] = (reg_addr == AXI_RT_READ_PERIOD_5_OFFSET); - addr_hit[ 88] = (reg_addr == AXI_RT_READ_PERIOD_6_OFFSET); - addr_hit[ 89] = (reg_addr == AXI_RT_READ_PERIOD_7_OFFSET); - addr_hit[ 90] = (reg_addr == AXI_RT_READ_PERIOD_8_OFFSET); - addr_hit[ 91] = (reg_addr == AXI_RT_READ_PERIOD_9_OFFSET); - addr_hit[ 92] = (reg_addr == AXI_RT_READ_PERIOD_10_OFFSET); - addr_hit[ 93] = (reg_addr == AXI_RT_READ_PERIOD_11_OFFSET); - addr_hit[ 94] = (reg_addr == AXI_RT_READ_PERIOD_12_OFFSET); - addr_hit[ 95] = (reg_addr == AXI_RT_READ_PERIOD_13_OFFSET); - addr_hit[ 96] = (reg_addr == AXI_RT_READ_PERIOD_14_OFFSET); - addr_hit[ 97] = (reg_addr == AXI_RT_READ_PERIOD_15_OFFSET); - addr_hit[ 98] = (reg_addr == AXI_RT_READ_PERIOD_16_OFFSET); - addr_hit[ 99] = (reg_addr == AXI_RT_READ_PERIOD_17_OFFSET); - addr_hit[100] = (reg_addr == AXI_RT_READ_PERIOD_18_OFFSET); - addr_hit[101] = (reg_addr == AXI_RT_READ_PERIOD_19_OFFSET); - addr_hit[102] = (reg_addr == AXI_RT_READ_PERIOD_20_OFFSET); - addr_hit[103] = (reg_addr == AXI_RT_READ_PERIOD_21_OFFSET); - addr_hit[104] = (reg_addr == AXI_RT_READ_PERIOD_22_OFFSET); - addr_hit[105] = (reg_addr == AXI_RT_READ_PERIOD_23_OFFSET); - addr_hit[106] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_0_OFFSET); - addr_hit[107] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_1_OFFSET); - addr_hit[108] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_2_OFFSET); - addr_hit[109] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_3_OFFSET); - addr_hit[110] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_4_OFFSET); - addr_hit[111] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_5_OFFSET); - addr_hit[112] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_6_OFFSET); - addr_hit[113] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_7_OFFSET); - addr_hit[114] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_8_OFFSET); - addr_hit[115] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_9_OFFSET); - addr_hit[116] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_10_OFFSET); - addr_hit[117] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_11_OFFSET); - addr_hit[118] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_12_OFFSET); - addr_hit[119] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_13_OFFSET); - addr_hit[120] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_14_OFFSET); - addr_hit[121] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_15_OFFSET); - addr_hit[122] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_16_OFFSET); - addr_hit[123] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_17_OFFSET); - addr_hit[124] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_18_OFFSET); - addr_hit[125] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_19_OFFSET); - addr_hit[126] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_20_OFFSET); - addr_hit[127] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_21_OFFSET); - addr_hit[128] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_22_OFFSET); - addr_hit[129] = (reg_addr == AXI_RT_WRITE_BUDGET_LEFT_23_OFFSET); - addr_hit[130] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_0_OFFSET); - addr_hit[131] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_1_OFFSET); - addr_hit[132] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_2_OFFSET); - addr_hit[133] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_3_OFFSET); - addr_hit[134] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_4_OFFSET); - addr_hit[135] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_5_OFFSET); - addr_hit[136] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_6_OFFSET); - addr_hit[137] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_7_OFFSET); - addr_hit[138] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_8_OFFSET); - addr_hit[139] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_9_OFFSET); - addr_hit[140] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_10_OFFSET); - addr_hit[141] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_11_OFFSET); - addr_hit[142] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_12_OFFSET); - addr_hit[143] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_13_OFFSET); - addr_hit[144] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_14_OFFSET); - addr_hit[145] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_15_OFFSET); - addr_hit[146] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_16_OFFSET); - addr_hit[147] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_17_OFFSET); - addr_hit[148] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_18_OFFSET); - addr_hit[149] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_19_OFFSET); - addr_hit[150] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_20_OFFSET); - addr_hit[151] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_21_OFFSET); - addr_hit[152] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_22_OFFSET); - addr_hit[153] = (reg_addr == AXI_RT_READ_BUDGET_LEFT_23_OFFSET); - addr_hit[154] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_0_OFFSET); - addr_hit[155] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_1_OFFSET); - addr_hit[156] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_2_OFFSET); - addr_hit[157] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_3_OFFSET); - addr_hit[158] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_4_OFFSET); - addr_hit[159] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_5_OFFSET); - addr_hit[160] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_6_OFFSET); - addr_hit[161] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_7_OFFSET); - addr_hit[162] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_8_OFFSET); - addr_hit[163] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_9_OFFSET); - addr_hit[164] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_10_OFFSET); - addr_hit[165] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_11_OFFSET); - addr_hit[166] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_12_OFFSET); - addr_hit[167] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_13_OFFSET); - addr_hit[168] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_14_OFFSET); - addr_hit[169] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_15_OFFSET); - addr_hit[170] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_16_OFFSET); - addr_hit[171] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_17_OFFSET); - addr_hit[172] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_18_OFFSET); - addr_hit[173] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_19_OFFSET); - addr_hit[174] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_20_OFFSET); - addr_hit[175] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_21_OFFSET); - addr_hit[176] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_22_OFFSET); - addr_hit[177] = (reg_addr == AXI_RT_WRITE_PERIOD_LEFT_23_OFFSET); - addr_hit[178] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_0_OFFSET); - addr_hit[179] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_1_OFFSET); - addr_hit[180] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_2_OFFSET); - addr_hit[181] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_3_OFFSET); - addr_hit[182] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_4_OFFSET); - addr_hit[183] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_5_OFFSET); - addr_hit[184] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_6_OFFSET); - addr_hit[185] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_7_OFFSET); - addr_hit[186] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_8_OFFSET); - addr_hit[187] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_9_OFFSET); - addr_hit[188] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_10_OFFSET); - addr_hit[189] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_11_OFFSET); - addr_hit[190] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_12_OFFSET); - addr_hit[191] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_13_OFFSET); - addr_hit[192] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_14_OFFSET); - addr_hit[193] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_15_OFFSET); - addr_hit[194] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_16_OFFSET); - addr_hit[195] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_17_OFFSET); - addr_hit[196] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_18_OFFSET); - addr_hit[197] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_19_OFFSET); - addr_hit[198] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_20_OFFSET); - addr_hit[199] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_21_OFFSET); - addr_hit[200] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_22_OFFSET); - addr_hit[201] = (reg_addr == AXI_RT_READ_PERIOD_LEFT_23_OFFSET); - addr_hit[202] = (reg_addr == AXI_RT_ISOLATE_OFFSET); - addr_hit[203] = (reg_addr == AXI_RT_ISOLATED_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(AXI_RT_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(AXI_RT_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(AXI_RT_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(AXI_RT_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(AXI_RT_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(AXI_RT_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(AXI_RT_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(AXI_RT_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(AXI_RT_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(AXI_RT_PERMIT[ 9] & ~reg_be))) | - (addr_hit[ 10] & (|(AXI_RT_PERMIT[ 10] & ~reg_be))) | - (addr_hit[ 11] & (|(AXI_RT_PERMIT[ 11] & ~reg_be))) | - (addr_hit[ 12] & (|(AXI_RT_PERMIT[ 12] & ~reg_be))) | - (addr_hit[ 13] & (|(AXI_RT_PERMIT[ 13] & ~reg_be))) | - (addr_hit[ 14] & (|(AXI_RT_PERMIT[ 14] & ~reg_be))) | - (addr_hit[ 15] & (|(AXI_RT_PERMIT[ 15] & ~reg_be))) | - (addr_hit[ 16] & (|(AXI_RT_PERMIT[ 16] & ~reg_be))) | - (addr_hit[ 17] & (|(AXI_RT_PERMIT[ 17] & ~reg_be))) | - (addr_hit[ 18] & (|(AXI_RT_PERMIT[ 18] & ~reg_be))) | - (addr_hit[ 19] & (|(AXI_RT_PERMIT[ 19] & ~reg_be))) | - (addr_hit[ 20] & (|(AXI_RT_PERMIT[ 20] & ~reg_be))) | - (addr_hit[ 21] & (|(AXI_RT_PERMIT[ 21] & ~reg_be))) | - (addr_hit[ 22] & (|(AXI_RT_PERMIT[ 22] & ~reg_be))) | - (addr_hit[ 23] & (|(AXI_RT_PERMIT[ 23] & ~reg_be))) | - (addr_hit[ 24] & (|(AXI_RT_PERMIT[ 24] & ~reg_be))) | - (addr_hit[ 25] & (|(AXI_RT_PERMIT[ 25] & ~reg_be))) | - (addr_hit[ 26] & (|(AXI_RT_PERMIT[ 26] & ~reg_be))) | - (addr_hit[ 27] & (|(AXI_RT_PERMIT[ 27] & ~reg_be))) | - (addr_hit[ 28] & (|(AXI_RT_PERMIT[ 28] & ~reg_be))) | - (addr_hit[ 29] & (|(AXI_RT_PERMIT[ 29] & ~reg_be))) | - (addr_hit[ 30] & (|(AXI_RT_PERMIT[ 30] & ~reg_be))) | - (addr_hit[ 31] & (|(AXI_RT_PERMIT[ 31] & ~reg_be))) | - (addr_hit[ 32] & (|(AXI_RT_PERMIT[ 32] & ~reg_be))) | - (addr_hit[ 33] & (|(AXI_RT_PERMIT[ 33] & ~reg_be))) | - (addr_hit[ 34] & (|(AXI_RT_PERMIT[ 34] & ~reg_be))) | - (addr_hit[ 35] & (|(AXI_RT_PERMIT[ 35] & ~reg_be))) | - (addr_hit[ 36] & (|(AXI_RT_PERMIT[ 36] & ~reg_be))) | - (addr_hit[ 37] & (|(AXI_RT_PERMIT[ 37] & ~reg_be))) | - (addr_hit[ 38] & (|(AXI_RT_PERMIT[ 38] & ~reg_be))) | - (addr_hit[ 39] & (|(AXI_RT_PERMIT[ 39] & ~reg_be))) | - (addr_hit[ 40] & (|(AXI_RT_PERMIT[ 40] & ~reg_be))) | - (addr_hit[ 41] & (|(AXI_RT_PERMIT[ 41] & ~reg_be))) | - (addr_hit[ 42] & (|(AXI_RT_PERMIT[ 42] & ~reg_be))) | - (addr_hit[ 43] & (|(AXI_RT_PERMIT[ 43] & ~reg_be))) | - (addr_hit[ 44] & (|(AXI_RT_PERMIT[ 44] & ~reg_be))) | - (addr_hit[ 45] & (|(AXI_RT_PERMIT[ 45] & ~reg_be))) | - (addr_hit[ 46] & (|(AXI_RT_PERMIT[ 46] & ~reg_be))) | - (addr_hit[ 47] & (|(AXI_RT_PERMIT[ 47] & ~reg_be))) | - (addr_hit[ 48] & (|(AXI_RT_PERMIT[ 48] & ~reg_be))) | - (addr_hit[ 49] & (|(AXI_RT_PERMIT[ 49] & ~reg_be))) | - (addr_hit[ 50] & (|(AXI_RT_PERMIT[ 50] & ~reg_be))) | - (addr_hit[ 51] & (|(AXI_RT_PERMIT[ 51] & ~reg_be))) | - (addr_hit[ 52] & (|(AXI_RT_PERMIT[ 52] & ~reg_be))) | - (addr_hit[ 53] & (|(AXI_RT_PERMIT[ 53] & ~reg_be))) | - (addr_hit[ 54] & (|(AXI_RT_PERMIT[ 54] & ~reg_be))) | - (addr_hit[ 55] & (|(AXI_RT_PERMIT[ 55] & ~reg_be))) | - (addr_hit[ 56] & (|(AXI_RT_PERMIT[ 56] & ~reg_be))) | - (addr_hit[ 57] & (|(AXI_RT_PERMIT[ 57] & ~reg_be))) | - (addr_hit[ 58] & (|(AXI_RT_PERMIT[ 58] & ~reg_be))) | - (addr_hit[ 59] & (|(AXI_RT_PERMIT[ 59] & ~reg_be))) | - (addr_hit[ 60] & (|(AXI_RT_PERMIT[ 60] & ~reg_be))) | - (addr_hit[ 61] & (|(AXI_RT_PERMIT[ 61] & ~reg_be))) | - (addr_hit[ 62] & (|(AXI_RT_PERMIT[ 62] & ~reg_be))) | - (addr_hit[ 63] & (|(AXI_RT_PERMIT[ 63] & ~reg_be))) | - (addr_hit[ 64] & (|(AXI_RT_PERMIT[ 64] & ~reg_be))) | - (addr_hit[ 65] & (|(AXI_RT_PERMIT[ 65] & ~reg_be))) | - (addr_hit[ 66] & (|(AXI_RT_PERMIT[ 66] & ~reg_be))) | - (addr_hit[ 67] & (|(AXI_RT_PERMIT[ 67] & ~reg_be))) | - (addr_hit[ 68] & (|(AXI_RT_PERMIT[ 68] & ~reg_be))) | - (addr_hit[ 69] & (|(AXI_RT_PERMIT[ 69] & ~reg_be))) | - (addr_hit[ 70] & (|(AXI_RT_PERMIT[ 70] & ~reg_be))) | - (addr_hit[ 71] & (|(AXI_RT_PERMIT[ 71] & ~reg_be))) | - (addr_hit[ 72] & (|(AXI_RT_PERMIT[ 72] & ~reg_be))) | - (addr_hit[ 73] & (|(AXI_RT_PERMIT[ 73] & ~reg_be))) | - (addr_hit[ 74] & (|(AXI_RT_PERMIT[ 74] & ~reg_be))) | - (addr_hit[ 75] & (|(AXI_RT_PERMIT[ 75] & ~reg_be))) | - (addr_hit[ 76] & (|(AXI_RT_PERMIT[ 76] & ~reg_be))) | - (addr_hit[ 77] & (|(AXI_RT_PERMIT[ 77] & ~reg_be))) | - (addr_hit[ 78] & (|(AXI_RT_PERMIT[ 78] & ~reg_be))) | - (addr_hit[ 79] & (|(AXI_RT_PERMIT[ 79] & ~reg_be))) | - (addr_hit[ 80] & (|(AXI_RT_PERMIT[ 80] & ~reg_be))) | - (addr_hit[ 81] & (|(AXI_RT_PERMIT[ 81] & ~reg_be))) | - (addr_hit[ 82] & (|(AXI_RT_PERMIT[ 82] & ~reg_be))) | - (addr_hit[ 83] & (|(AXI_RT_PERMIT[ 83] & ~reg_be))) | - (addr_hit[ 84] & (|(AXI_RT_PERMIT[ 84] & ~reg_be))) | - (addr_hit[ 85] & (|(AXI_RT_PERMIT[ 85] & ~reg_be))) | - (addr_hit[ 86] & (|(AXI_RT_PERMIT[ 86] & ~reg_be))) | - (addr_hit[ 87] & (|(AXI_RT_PERMIT[ 87] & ~reg_be))) | - (addr_hit[ 88] & (|(AXI_RT_PERMIT[ 88] & ~reg_be))) | - (addr_hit[ 89] & (|(AXI_RT_PERMIT[ 89] & ~reg_be))) | - (addr_hit[ 90] & (|(AXI_RT_PERMIT[ 90] & ~reg_be))) | - (addr_hit[ 91] & (|(AXI_RT_PERMIT[ 91] & ~reg_be))) | - (addr_hit[ 92] & (|(AXI_RT_PERMIT[ 92] & ~reg_be))) | - (addr_hit[ 93] & (|(AXI_RT_PERMIT[ 93] & ~reg_be))) | - (addr_hit[ 94] & (|(AXI_RT_PERMIT[ 94] & ~reg_be))) | - (addr_hit[ 95] & (|(AXI_RT_PERMIT[ 95] & ~reg_be))) | - (addr_hit[ 96] & (|(AXI_RT_PERMIT[ 96] & ~reg_be))) | - (addr_hit[ 97] & (|(AXI_RT_PERMIT[ 97] & ~reg_be))) | - (addr_hit[ 98] & (|(AXI_RT_PERMIT[ 98] & ~reg_be))) | - (addr_hit[ 99] & (|(AXI_RT_PERMIT[ 99] & ~reg_be))) | - (addr_hit[100] & (|(AXI_RT_PERMIT[100] & ~reg_be))) | - (addr_hit[101] & (|(AXI_RT_PERMIT[101] & ~reg_be))) | - (addr_hit[102] & (|(AXI_RT_PERMIT[102] & ~reg_be))) | - (addr_hit[103] & (|(AXI_RT_PERMIT[103] & ~reg_be))) | - (addr_hit[104] & (|(AXI_RT_PERMIT[104] & ~reg_be))) | - (addr_hit[105] & (|(AXI_RT_PERMIT[105] & ~reg_be))) | - (addr_hit[106] & (|(AXI_RT_PERMIT[106] & ~reg_be))) | - (addr_hit[107] & (|(AXI_RT_PERMIT[107] & ~reg_be))) | - (addr_hit[108] & (|(AXI_RT_PERMIT[108] & ~reg_be))) | - (addr_hit[109] & (|(AXI_RT_PERMIT[109] & ~reg_be))) | - (addr_hit[110] & (|(AXI_RT_PERMIT[110] & ~reg_be))) | - (addr_hit[111] & (|(AXI_RT_PERMIT[111] & ~reg_be))) | - (addr_hit[112] & (|(AXI_RT_PERMIT[112] & ~reg_be))) | - (addr_hit[113] & (|(AXI_RT_PERMIT[113] & ~reg_be))) | - (addr_hit[114] & (|(AXI_RT_PERMIT[114] & ~reg_be))) | - (addr_hit[115] & (|(AXI_RT_PERMIT[115] & ~reg_be))) | - (addr_hit[116] & (|(AXI_RT_PERMIT[116] & ~reg_be))) | - (addr_hit[117] & (|(AXI_RT_PERMIT[117] & ~reg_be))) | - (addr_hit[118] & (|(AXI_RT_PERMIT[118] & ~reg_be))) | - (addr_hit[119] & (|(AXI_RT_PERMIT[119] & ~reg_be))) | - (addr_hit[120] & (|(AXI_RT_PERMIT[120] & ~reg_be))) | - (addr_hit[121] & (|(AXI_RT_PERMIT[121] & ~reg_be))) | - (addr_hit[122] & (|(AXI_RT_PERMIT[122] & ~reg_be))) | - (addr_hit[123] & (|(AXI_RT_PERMIT[123] & ~reg_be))) | - (addr_hit[124] & (|(AXI_RT_PERMIT[124] & ~reg_be))) | - (addr_hit[125] & (|(AXI_RT_PERMIT[125] & ~reg_be))) | - (addr_hit[126] & (|(AXI_RT_PERMIT[126] & ~reg_be))) | - (addr_hit[127] & (|(AXI_RT_PERMIT[127] & ~reg_be))) | - (addr_hit[128] & (|(AXI_RT_PERMIT[128] & ~reg_be))) | - (addr_hit[129] & (|(AXI_RT_PERMIT[129] & ~reg_be))) | - (addr_hit[130] & (|(AXI_RT_PERMIT[130] & ~reg_be))) | - (addr_hit[131] & (|(AXI_RT_PERMIT[131] & ~reg_be))) | - (addr_hit[132] & (|(AXI_RT_PERMIT[132] & ~reg_be))) | - (addr_hit[133] & (|(AXI_RT_PERMIT[133] & ~reg_be))) | - (addr_hit[134] & (|(AXI_RT_PERMIT[134] & ~reg_be))) | - (addr_hit[135] & (|(AXI_RT_PERMIT[135] & ~reg_be))) | - (addr_hit[136] & (|(AXI_RT_PERMIT[136] & ~reg_be))) | - (addr_hit[137] & (|(AXI_RT_PERMIT[137] & ~reg_be))) | - (addr_hit[138] & (|(AXI_RT_PERMIT[138] & ~reg_be))) | - (addr_hit[139] & (|(AXI_RT_PERMIT[139] & ~reg_be))) | - (addr_hit[140] & (|(AXI_RT_PERMIT[140] & ~reg_be))) | - (addr_hit[141] & (|(AXI_RT_PERMIT[141] & ~reg_be))) | - (addr_hit[142] & (|(AXI_RT_PERMIT[142] & ~reg_be))) | - (addr_hit[143] & (|(AXI_RT_PERMIT[143] & ~reg_be))) | - (addr_hit[144] & (|(AXI_RT_PERMIT[144] & ~reg_be))) | - (addr_hit[145] & (|(AXI_RT_PERMIT[145] & ~reg_be))) | - (addr_hit[146] & (|(AXI_RT_PERMIT[146] & ~reg_be))) | - (addr_hit[147] & (|(AXI_RT_PERMIT[147] & ~reg_be))) | - (addr_hit[148] & (|(AXI_RT_PERMIT[148] & ~reg_be))) | - (addr_hit[149] & (|(AXI_RT_PERMIT[149] & ~reg_be))) | - (addr_hit[150] & (|(AXI_RT_PERMIT[150] & ~reg_be))) | - (addr_hit[151] & (|(AXI_RT_PERMIT[151] & ~reg_be))) | - (addr_hit[152] & (|(AXI_RT_PERMIT[152] & ~reg_be))) | - (addr_hit[153] & (|(AXI_RT_PERMIT[153] & ~reg_be))) | - (addr_hit[154] & (|(AXI_RT_PERMIT[154] & ~reg_be))) | - (addr_hit[155] & (|(AXI_RT_PERMIT[155] & ~reg_be))) | - (addr_hit[156] & (|(AXI_RT_PERMIT[156] & ~reg_be))) | - (addr_hit[157] & (|(AXI_RT_PERMIT[157] & ~reg_be))) | - (addr_hit[158] & (|(AXI_RT_PERMIT[158] & ~reg_be))) | - (addr_hit[159] & (|(AXI_RT_PERMIT[159] & ~reg_be))) | - (addr_hit[160] & (|(AXI_RT_PERMIT[160] & ~reg_be))) | - (addr_hit[161] & (|(AXI_RT_PERMIT[161] & ~reg_be))) | - (addr_hit[162] & (|(AXI_RT_PERMIT[162] & ~reg_be))) | - (addr_hit[163] & (|(AXI_RT_PERMIT[163] & ~reg_be))) | - (addr_hit[164] & (|(AXI_RT_PERMIT[164] & ~reg_be))) | - (addr_hit[165] & (|(AXI_RT_PERMIT[165] & ~reg_be))) | - (addr_hit[166] & (|(AXI_RT_PERMIT[166] & ~reg_be))) | - (addr_hit[167] & (|(AXI_RT_PERMIT[167] & ~reg_be))) | - (addr_hit[168] & (|(AXI_RT_PERMIT[168] & ~reg_be))) | - (addr_hit[169] & (|(AXI_RT_PERMIT[169] & ~reg_be))) | - (addr_hit[170] & (|(AXI_RT_PERMIT[170] & ~reg_be))) | - (addr_hit[171] & (|(AXI_RT_PERMIT[171] & ~reg_be))) | - (addr_hit[172] & (|(AXI_RT_PERMIT[172] & ~reg_be))) | - (addr_hit[173] & (|(AXI_RT_PERMIT[173] & ~reg_be))) | - (addr_hit[174] & (|(AXI_RT_PERMIT[174] & ~reg_be))) | - (addr_hit[175] & (|(AXI_RT_PERMIT[175] & ~reg_be))) | - (addr_hit[176] & (|(AXI_RT_PERMIT[176] & ~reg_be))) | - (addr_hit[177] & (|(AXI_RT_PERMIT[177] & ~reg_be))) | - (addr_hit[178] & (|(AXI_RT_PERMIT[178] & ~reg_be))) | - (addr_hit[179] & (|(AXI_RT_PERMIT[179] & ~reg_be))) | - (addr_hit[180] & (|(AXI_RT_PERMIT[180] & ~reg_be))) | - (addr_hit[181] & (|(AXI_RT_PERMIT[181] & ~reg_be))) | - (addr_hit[182] & (|(AXI_RT_PERMIT[182] & ~reg_be))) | - (addr_hit[183] & (|(AXI_RT_PERMIT[183] & ~reg_be))) | - (addr_hit[184] & (|(AXI_RT_PERMIT[184] & ~reg_be))) | - (addr_hit[185] & (|(AXI_RT_PERMIT[185] & ~reg_be))) | - (addr_hit[186] & (|(AXI_RT_PERMIT[186] & ~reg_be))) | - (addr_hit[187] & (|(AXI_RT_PERMIT[187] & ~reg_be))) | - (addr_hit[188] & (|(AXI_RT_PERMIT[188] & ~reg_be))) | - (addr_hit[189] & (|(AXI_RT_PERMIT[189] & ~reg_be))) | - (addr_hit[190] & (|(AXI_RT_PERMIT[190] & ~reg_be))) | - (addr_hit[191] & (|(AXI_RT_PERMIT[191] & ~reg_be))) | - (addr_hit[192] & (|(AXI_RT_PERMIT[192] & ~reg_be))) | - (addr_hit[193] & (|(AXI_RT_PERMIT[193] & ~reg_be))) | - (addr_hit[194] & (|(AXI_RT_PERMIT[194] & ~reg_be))) | - (addr_hit[195] & (|(AXI_RT_PERMIT[195] & ~reg_be))) | - (addr_hit[196] & (|(AXI_RT_PERMIT[196] & ~reg_be))) | - (addr_hit[197] & (|(AXI_RT_PERMIT[197] & ~reg_be))) | - (addr_hit[198] & (|(AXI_RT_PERMIT[198] & ~reg_be))) | - (addr_hit[199] & (|(AXI_RT_PERMIT[199] & ~reg_be))) | - (addr_hit[200] & (|(AXI_RT_PERMIT[200] & ~reg_be))) | - (addr_hit[201] & (|(AXI_RT_PERMIT[201] & ~reg_be))) | - (addr_hit[202] & (|(AXI_RT_PERMIT[202] & ~reg_be))) | - (addr_hit[203] & (|(AXI_RT_PERMIT[203] & ~reg_be))))); - end - - assign rt_enable_enable_0_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_0_wd = reg_wdata[0]; - - assign rt_enable_enable_1_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_1_wd = reg_wdata[1]; - - assign rt_enable_enable_2_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_2_wd = reg_wdata[2]; - - assign rt_enable_enable_3_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_3_wd = reg_wdata[3]; - - assign rt_enable_enable_4_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_4_wd = reg_wdata[4]; - - assign rt_enable_enable_5_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_5_wd = reg_wdata[5]; - - assign rt_enable_enable_6_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_6_wd = reg_wdata[6]; - - assign rt_enable_enable_7_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_7_wd = reg_wdata[7]; - - assign rt_enable_enable_8_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_8_wd = reg_wdata[8]; - - assign rt_enable_enable_9_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_9_wd = reg_wdata[9]; - - assign rt_enable_enable_10_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_10_wd = reg_wdata[10]; - - assign rt_enable_enable_11_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_11_wd = reg_wdata[11]; - - assign rt_enable_enable_12_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_12_wd = reg_wdata[12]; - - assign rt_enable_enable_13_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_13_wd = reg_wdata[13]; - - assign rt_enable_enable_14_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_14_wd = reg_wdata[14]; - - assign rt_enable_enable_15_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_15_wd = reg_wdata[15]; - - assign rt_enable_enable_16_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_16_wd = reg_wdata[16]; - - assign rt_enable_enable_17_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_17_wd = reg_wdata[17]; - - assign rt_enable_enable_18_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_18_wd = reg_wdata[18]; - - assign rt_enable_enable_19_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_19_wd = reg_wdata[19]; - - assign rt_enable_enable_20_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_20_wd = reg_wdata[20]; - - assign rt_enable_enable_21_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_21_wd = reg_wdata[21]; - - assign rt_enable_enable_22_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_22_wd = reg_wdata[22]; - - assign rt_enable_enable_23_we = addr_hit[0] & reg_we & !reg_error; - assign rt_enable_enable_23_wd = reg_wdata[23]; - - assign rt_bypassed_bypassed_0_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_1_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_2_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_3_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_4_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_5_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_6_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_7_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_8_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_9_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_10_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_11_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_12_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_13_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_14_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_15_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_16_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_17_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_18_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_19_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_20_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_21_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_22_re = addr_hit[1] & reg_re & !reg_error; - - assign rt_bypassed_bypassed_23_re = addr_hit[1] & reg_re & !reg_error; - - assign len_limit_0_len_0_we = addr_hit[2] & reg_we & !reg_error; - assign len_limit_0_len_0_wd = reg_wdata[7:0]; - - assign len_limit_0_len_1_we = addr_hit[2] & reg_we & !reg_error; - assign len_limit_0_len_1_wd = reg_wdata[15:8]; - - assign len_limit_0_len_2_we = addr_hit[2] & reg_we & !reg_error; - assign len_limit_0_len_2_wd = reg_wdata[23:16]; - - assign len_limit_0_len_3_we = addr_hit[2] & reg_we & !reg_error; - assign len_limit_0_len_3_wd = reg_wdata[31:24]; - - assign len_limit_1_len_4_we = addr_hit[3] & reg_we & !reg_error; - assign len_limit_1_len_4_wd = reg_wdata[7:0]; - - assign len_limit_1_len_5_we = addr_hit[3] & reg_we & !reg_error; - assign len_limit_1_len_5_wd = reg_wdata[15:8]; - - assign len_limit_1_len_6_we = addr_hit[3] & reg_we & !reg_error; - assign len_limit_1_len_6_wd = reg_wdata[23:16]; - - assign len_limit_1_len_7_we = addr_hit[3] & reg_we & !reg_error; - assign len_limit_1_len_7_wd = reg_wdata[31:24]; - - assign len_limit_2_len_8_we = addr_hit[4] & reg_we & !reg_error; - assign len_limit_2_len_8_wd = reg_wdata[7:0]; - - assign len_limit_2_len_9_we = addr_hit[4] & reg_we & !reg_error; - assign len_limit_2_len_9_wd = reg_wdata[15:8]; - - assign len_limit_2_len_10_we = addr_hit[4] & reg_we & !reg_error; - assign len_limit_2_len_10_wd = reg_wdata[23:16]; - - assign len_limit_2_len_11_we = addr_hit[4] & reg_we & !reg_error; - assign len_limit_2_len_11_wd = reg_wdata[31:24]; - - assign len_limit_3_len_12_we = addr_hit[5] & reg_we & !reg_error; - assign len_limit_3_len_12_wd = reg_wdata[7:0]; - - assign len_limit_3_len_13_we = addr_hit[5] & reg_we & !reg_error; - assign len_limit_3_len_13_wd = reg_wdata[15:8]; - - assign len_limit_3_len_14_we = addr_hit[5] & reg_we & !reg_error; - assign len_limit_3_len_14_wd = reg_wdata[23:16]; - - assign len_limit_3_len_15_we = addr_hit[5] & reg_we & !reg_error; - assign len_limit_3_len_15_wd = reg_wdata[31:24]; - - assign len_limit_4_len_16_we = addr_hit[6] & reg_we & !reg_error; - assign len_limit_4_len_16_wd = reg_wdata[7:0]; - - assign len_limit_4_len_17_we = addr_hit[6] & reg_we & !reg_error; - assign len_limit_4_len_17_wd = reg_wdata[15:8]; - - assign len_limit_4_len_18_we = addr_hit[6] & reg_we & !reg_error; - assign len_limit_4_len_18_wd = reg_wdata[23:16]; - - assign len_limit_4_len_19_we = addr_hit[6] & reg_we & !reg_error; - assign len_limit_4_len_19_wd = reg_wdata[31:24]; - - assign len_limit_5_len_20_we = addr_hit[7] & reg_we & !reg_error; - assign len_limit_5_len_20_wd = reg_wdata[7:0]; - - assign len_limit_5_len_21_we = addr_hit[7] & reg_we & !reg_error; - assign len_limit_5_len_21_wd = reg_wdata[15:8]; - - assign len_limit_5_len_22_we = addr_hit[7] & reg_we & !reg_error; - assign len_limit_5_len_22_wd = reg_wdata[23:16]; - - assign len_limit_5_len_23_we = addr_hit[7] & reg_we & !reg_error; - assign len_limit_5_len_23_wd = reg_wdata[31:24]; - - assign imtu_enable_enable_0_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_0_wd = reg_wdata[0]; - - assign imtu_enable_enable_1_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_1_wd = reg_wdata[1]; - - assign imtu_enable_enable_2_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_2_wd = reg_wdata[2]; - - assign imtu_enable_enable_3_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_3_wd = reg_wdata[3]; - - assign imtu_enable_enable_4_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_4_wd = reg_wdata[4]; - - assign imtu_enable_enable_5_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_5_wd = reg_wdata[5]; - - assign imtu_enable_enable_6_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_6_wd = reg_wdata[6]; - - assign imtu_enable_enable_7_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_7_wd = reg_wdata[7]; - - assign imtu_enable_enable_8_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_8_wd = reg_wdata[8]; - - assign imtu_enable_enable_9_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_9_wd = reg_wdata[9]; - - assign imtu_enable_enable_10_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_10_wd = reg_wdata[10]; - - assign imtu_enable_enable_11_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_11_wd = reg_wdata[11]; - - assign imtu_enable_enable_12_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_12_wd = reg_wdata[12]; - - assign imtu_enable_enable_13_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_13_wd = reg_wdata[13]; - - assign imtu_enable_enable_14_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_14_wd = reg_wdata[14]; - - assign imtu_enable_enable_15_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_15_wd = reg_wdata[15]; - - assign imtu_enable_enable_16_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_16_wd = reg_wdata[16]; - - assign imtu_enable_enable_17_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_17_wd = reg_wdata[17]; - - assign imtu_enable_enable_18_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_18_wd = reg_wdata[18]; - - assign imtu_enable_enable_19_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_19_wd = reg_wdata[19]; - - assign imtu_enable_enable_20_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_20_wd = reg_wdata[20]; - - assign imtu_enable_enable_21_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_21_wd = reg_wdata[21]; - - assign imtu_enable_enable_22_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_22_wd = reg_wdata[22]; - - assign imtu_enable_enable_23_we = addr_hit[8] & reg_we & !reg_error; - assign imtu_enable_enable_23_wd = reg_wdata[23]; - - assign imtu_abort_abort_0_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_0_wd = reg_wdata[0]; - - assign imtu_abort_abort_1_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_1_wd = reg_wdata[1]; - - assign imtu_abort_abort_2_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_2_wd = reg_wdata[2]; - - assign imtu_abort_abort_3_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_3_wd = reg_wdata[3]; - - assign imtu_abort_abort_4_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_4_wd = reg_wdata[4]; - - assign imtu_abort_abort_5_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_5_wd = reg_wdata[5]; - - assign imtu_abort_abort_6_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_6_wd = reg_wdata[6]; - - assign imtu_abort_abort_7_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_7_wd = reg_wdata[7]; - - assign imtu_abort_abort_8_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_8_wd = reg_wdata[8]; - - assign imtu_abort_abort_9_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_9_wd = reg_wdata[9]; - - assign imtu_abort_abort_10_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_10_wd = reg_wdata[10]; - - assign imtu_abort_abort_11_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_11_wd = reg_wdata[11]; - - assign imtu_abort_abort_12_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_12_wd = reg_wdata[12]; - - assign imtu_abort_abort_13_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_13_wd = reg_wdata[13]; - - assign imtu_abort_abort_14_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_14_wd = reg_wdata[14]; - - assign imtu_abort_abort_15_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_15_wd = reg_wdata[15]; - - assign imtu_abort_abort_16_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_16_wd = reg_wdata[16]; - - assign imtu_abort_abort_17_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_17_wd = reg_wdata[17]; - - assign imtu_abort_abort_18_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_18_wd = reg_wdata[18]; - - assign imtu_abort_abort_19_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_19_wd = reg_wdata[19]; - - assign imtu_abort_abort_20_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_20_wd = reg_wdata[20]; - - assign imtu_abort_abort_21_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_21_wd = reg_wdata[21]; - - assign imtu_abort_abort_22_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_22_wd = reg_wdata[22]; - - assign imtu_abort_abort_23_we = addr_hit[9] & reg_we & !reg_error; - assign imtu_abort_abort_23_wd = reg_wdata[23]; - - assign write_budget_0_we = addr_hit[10] & reg_we & !reg_error; - assign write_budget_0_wd = reg_wdata[31:0]; - - assign write_budget_1_we = addr_hit[11] & reg_we & !reg_error; - assign write_budget_1_wd = reg_wdata[31:0]; - - assign write_budget_2_we = addr_hit[12] & reg_we & !reg_error; - assign write_budget_2_wd = reg_wdata[31:0]; - - assign write_budget_3_we = addr_hit[13] & reg_we & !reg_error; - assign write_budget_3_wd = reg_wdata[31:0]; - - assign write_budget_4_we = addr_hit[14] & reg_we & !reg_error; - assign write_budget_4_wd = reg_wdata[31:0]; - - assign write_budget_5_we = addr_hit[15] & reg_we & !reg_error; - assign write_budget_5_wd = reg_wdata[31:0]; - - assign write_budget_6_we = addr_hit[16] & reg_we & !reg_error; - assign write_budget_6_wd = reg_wdata[31:0]; - - assign write_budget_7_we = addr_hit[17] & reg_we & !reg_error; - assign write_budget_7_wd = reg_wdata[31:0]; - - assign write_budget_8_we = addr_hit[18] & reg_we & !reg_error; - assign write_budget_8_wd = reg_wdata[31:0]; - - assign write_budget_9_we = addr_hit[19] & reg_we & !reg_error; - assign write_budget_9_wd = reg_wdata[31:0]; - - assign write_budget_10_we = addr_hit[20] & reg_we & !reg_error; - assign write_budget_10_wd = reg_wdata[31:0]; - - assign write_budget_11_we = addr_hit[21] & reg_we & !reg_error; - assign write_budget_11_wd = reg_wdata[31:0]; - - assign write_budget_12_we = addr_hit[22] & reg_we & !reg_error; - assign write_budget_12_wd = reg_wdata[31:0]; - - assign write_budget_13_we = addr_hit[23] & reg_we & !reg_error; - assign write_budget_13_wd = reg_wdata[31:0]; - - assign write_budget_14_we = addr_hit[24] & reg_we & !reg_error; - assign write_budget_14_wd = reg_wdata[31:0]; - - assign write_budget_15_we = addr_hit[25] & reg_we & !reg_error; - assign write_budget_15_wd = reg_wdata[31:0]; - - assign write_budget_16_we = addr_hit[26] & reg_we & !reg_error; - assign write_budget_16_wd = reg_wdata[31:0]; - - assign write_budget_17_we = addr_hit[27] & reg_we & !reg_error; - assign write_budget_17_wd = reg_wdata[31:0]; - - assign write_budget_18_we = addr_hit[28] & reg_we & !reg_error; - assign write_budget_18_wd = reg_wdata[31:0]; - - assign write_budget_19_we = addr_hit[29] & reg_we & !reg_error; - assign write_budget_19_wd = reg_wdata[31:0]; - - assign write_budget_20_we = addr_hit[30] & reg_we & !reg_error; - assign write_budget_20_wd = reg_wdata[31:0]; - - assign write_budget_21_we = addr_hit[31] & reg_we & !reg_error; - assign write_budget_21_wd = reg_wdata[31:0]; - - assign write_budget_22_we = addr_hit[32] & reg_we & !reg_error; - assign write_budget_22_wd = reg_wdata[31:0]; - - assign write_budget_23_we = addr_hit[33] & reg_we & !reg_error; - assign write_budget_23_wd = reg_wdata[31:0]; - - assign read_budget_0_we = addr_hit[34] & reg_we & !reg_error; - assign read_budget_0_wd = reg_wdata[31:0]; - - assign read_budget_1_we = addr_hit[35] & reg_we & !reg_error; - assign read_budget_1_wd = reg_wdata[31:0]; - - assign read_budget_2_we = addr_hit[36] & reg_we & !reg_error; - assign read_budget_2_wd = reg_wdata[31:0]; - - assign read_budget_3_we = addr_hit[37] & reg_we & !reg_error; - assign read_budget_3_wd = reg_wdata[31:0]; - - assign read_budget_4_we = addr_hit[38] & reg_we & !reg_error; - assign read_budget_4_wd = reg_wdata[31:0]; - - assign read_budget_5_we = addr_hit[39] & reg_we & !reg_error; - assign read_budget_5_wd = reg_wdata[31:0]; - - assign read_budget_6_we = addr_hit[40] & reg_we & !reg_error; - assign read_budget_6_wd = reg_wdata[31:0]; - - assign read_budget_7_we = addr_hit[41] & reg_we & !reg_error; - assign read_budget_7_wd = reg_wdata[31:0]; - - assign read_budget_8_we = addr_hit[42] & reg_we & !reg_error; - assign read_budget_8_wd = reg_wdata[31:0]; - - assign read_budget_9_we = addr_hit[43] & reg_we & !reg_error; - assign read_budget_9_wd = reg_wdata[31:0]; - - assign read_budget_10_we = addr_hit[44] & reg_we & !reg_error; - assign read_budget_10_wd = reg_wdata[31:0]; - - assign read_budget_11_we = addr_hit[45] & reg_we & !reg_error; - assign read_budget_11_wd = reg_wdata[31:0]; - - assign read_budget_12_we = addr_hit[46] & reg_we & !reg_error; - assign read_budget_12_wd = reg_wdata[31:0]; - - assign read_budget_13_we = addr_hit[47] & reg_we & !reg_error; - assign read_budget_13_wd = reg_wdata[31:0]; - - assign read_budget_14_we = addr_hit[48] & reg_we & !reg_error; - assign read_budget_14_wd = reg_wdata[31:0]; - - assign read_budget_15_we = addr_hit[49] & reg_we & !reg_error; - assign read_budget_15_wd = reg_wdata[31:0]; - - assign read_budget_16_we = addr_hit[50] & reg_we & !reg_error; - assign read_budget_16_wd = reg_wdata[31:0]; - - assign read_budget_17_we = addr_hit[51] & reg_we & !reg_error; - assign read_budget_17_wd = reg_wdata[31:0]; - - assign read_budget_18_we = addr_hit[52] & reg_we & !reg_error; - assign read_budget_18_wd = reg_wdata[31:0]; - - assign read_budget_19_we = addr_hit[53] & reg_we & !reg_error; - assign read_budget_19_wd = reg_wdata[31:0]; - - assign read_budget_20_we = addr_hit[54] & reg_we & !reg_error; - assign read_budget_20_wd = reg_wdata[31:0]; - - assign read_budget_21_we = addr_hit[55] & reg_we & !reg_error; - assign read_budget_21_wd = reg_wdata[31:0]; - - assign read_budget_22_we = addr_hit[56] & reg_we & !reg_error; - assign read_budget_22_wd = reg_wdata[31:0]; - - assign read_budget_23_we = addr_hit[57] & reg_we & !reg_error; - assign read_budget_23_wd = reg_wdata[31:0]; - - assign write_period_0_we = addr_hit[58] & reg_we & !reg_error; - assign write_period_0_wd = reg_wdata[31:0]; - - assign write_period_1_we = addr_hit[59] & reg_we & !reg_error; - assign write_period_1_wd = reg_wdata[31:0]; - - assign write_period_2_we = addr_hit[60] & reg_we & !reg_error; - assign write_period_2_wd = reg_wdata[31:0]; - - assign write_period_3_we = addr_hit[61] & reg_we & !reg_error; - assign write_period_3_wd = reg_wdata[31:0]; - - assign write_period_4_we = addr_hit[62] & reg_we & !reg_error; - assign write_period_4_wd = reg_wdata[31:0]; - - assign write_period_5_we = addr_hit[63] & reg_we & !reg_error; - assign write_period_5_wd = reg_wdata[31:0]; - - assign write_period_6_we = addr_hit[64] & reg_we & !reg_error; - assign write_period_6_wd = reg_wdata[31:0]; - - assign write_period_7_we = addr_hit[65] & reg_we & !reg_error; - assign write_period_7_wd = reg_wdata[31:0]; - - assign write_period_8_we = addr_hit[66] & reg_we & !reg_error; - assign write_period_8_wd = reg_wdata[31:0]; - - assign write_period_9_we = addr_hit[67] & reg_we & !reg_error; - assign write_period_9_wd = reg_wdata[31:0]; - - assign write_period_10_we = addr_hit[68] & reg_we & !reg_error; - assign write_period_10_wd = reg_wdata[31:0]; - - assign write_period_11_we = addr_hit[69] & reg_we & !reg_error; - assign write_period_11_wd = reg_wdata[31:0]; - - assign write_period_12_we = addr_hit[70] & reg_we & !reg_error; - assign write_period_12_wd = reg_wdata[31:0]; - - assign write_period_13_we = addr_hit[71] & reg_we & !reg_error; - assign write_period_13_wd = reg_wdata[31:0]; - - assign write_period_14_we = addr_hit[72] & reg_we & !reg_error; - assign write_period_14_wd = reg_wdata[31:0]; - - assign write_period_15_we = addr_hit[73] & reg_we & !reg_error; - assign write_period_15_wd = reg_wdata[31:0]; - - assign write_period_16_we = addr_hit[74] & reg_we & !reg_error; - assign write_period_16_wd = reg_wdata[31:0]; - - assign write_period_17_we = addr_hit[75] & reg_we & !reg_error; - assign write_period_17_wd = reg_wdata[31:0]; - - assign write_period_18_we = addr_hit[76] & reg_we & !reg_error; - assign write_period_18_wd = reg_wdata[31:0]; - - assign write_period_19_we = addr_hit[77] & reg_we & !reg_error; - assign write_period_19_wd = reg_wdata[31:0]; - - assign write_period_20_we = addr_hit[78] & reg_we & !reg_error; - assign write_period_20_wd = reg_wdata[31:0]; - - assign write_period_21_we = addr_hit[79] & reg_we & !reg_error; - assign write_period_21_wd = reg_wdata[31:0]; - - assign write_period_22_we = addr_hit[80] & reg_we & !reg_error; - assign write_period_22_wd = reg_wdata[31:0]; - - assign write_period_23_we = addr_hit[81] & reg_we & !reg_error; - assign write_period_23_wd = reg_wdata[31:0]; - - assign read_period_0_we = addr_hit[82] & reg_we & !reg_error; - assign read_period_0_wd = reg_wdata[31:0]; - - assign read_period_1_we = addr_hit[83] & reg_we & !reg_error; - assign read_period_1_wd = reg_wdata[31:0]; - - assign read_period_2_we = addr_hit[84] & reg_we & !reg_error; - assign read_period_2_wd = reg_wdata[31:0]; - - assign read_period_3_we = addr_hit[85] & reg_we & !reg_error; - assign read_period_3_wd = reg_wdata[31:0]; - - assign read_period_4_we = addr_hit[86] & reg_we & !reg_error; - assign read_period_4_wd = reg_wdata[31:0]; - - assign read_period_5_we = addr_hit[87] & reg_we & !reg_error; - assign read_period_5_wd = reg_wdata[31:0]; - - assign read_period_6_we = addr_hit[88] & reg_we & !reg_error; - assign read_period_6_wd = reg_wdata[31:0]; - - assign read_period_7_we = addr_hit[89] & reg_we & !reg_error; - assign read_period_7_wd = reg_wdata[31:0]; - - assign read_period_8_we = addr_hit[90] & reg_we & !reg_error; - assign read_period_8_wd = reg_wdata[31:0]; - - assign read_period_9_we = addr_hit[91] & reg_we & !reg_error; - assign read_period_9_wd = reg_wdata[31:0]; - - assign read_period_10_we = addr_hit[92] & reg_we & !reg_error; - assign read_period_10_wd = reg_wdata[31:0]; - - assign read_period_11_we = addr_hit[93] & reg_we & !reg_error; - assign read_period_11_wd = reg_wdata[31:0]; - - assign read_period_12_we = addr_hit[94] & reg_we & !reg_error; - assign read_period_12_wd = reg_wdata[31:0]; - - assign read_period_13_we = addr_hit[95] & reg_we & !reg_error; - assign read_period_13_wd = reg_wdata[31:0]; - - assign read_period_14_we = addr_hit[96] & reg_we & !reg_error; - assign read_period_14_wd = reg_wdata[31:0]; - - assign read_period_15_we = addr_hit[97] & reg_we & !reg_error; - assign read_period_15_wd = reg_wdata[31:0]; - - assign read_period_16_we = addr_hit[98] & reg_we & !reg_error; - assign read_period_16_wd = reg_wdata[31:0]; - - assign read_period_17_we = addr_hit[99] & reg_we & !reg_error; - assign read_period_17_wd = reg_wdata[31:0]; - - assign read_period_18_we = addr_hit[100] & reg_we & !reg_error; - assign read_period_18_wd = reg_wdata[31:0]; - - assign read_period_19_we = addr_hit[101] & reg_we & !reg_error; - assign read_period_19_wd = reg_wdata[31:0]; - - assign read_period_20_we = addr_hit[102] & reg_we & !reg_error; - assign read_period_20_wd = reg_wdata[31:0]; - - assign read_period_21_we = addr_hit[103] & reg_we & !reg_error; - assign read_period_21_wd = reg_wdata[31:0]; - - assign read_period_22_we = addr_hit[104] & reg_we & !reg_error; - assign read_period_22_wd = reg_wdata[31:0]; - - assign read_period_23_we = addr_hit[105] & reg_we & !reg_error; - assign read_period_23_wd = reg_wdata[31:0]; - - assign write_budget_left_0_re = addr_hit[106] & reg_re & !reg_error; - - assign write_budget_left_1_re = addr_hit[107] & reg_re & !reg_error; - - assign write_budget_left_2_re = addr_hit[108] & reg_re & !reg_error; - - assign write_budget_left_3_re = addr_hit[109] & reg_re & !reg_error; - - assign write_budget_left_4_re = addr_hit[110] & reg_re & !reg_error; - - assign write_budget_left_5_re = addr_hit[111] & reg_re & !reg_error; - - assign write_budget_left_6_re = addr_hit[112] & reg_re & !reg_error; - - assign write_budget_left_7_re = addr_hit[113] & reg_re & !reg_error; - - assign write_budget_left_8_re = addr_hit[114] & reg_re & !reg_error; - - assign write_budget_left_9_re = addr_hit[115] & reg_re & !reg_error; - - assign write_budget_left_10_re = addr_hit[116] & reg_re & !reg_error; - - assign write_budget_left_11_re = addr_hit[117] & reg_re & !reg_error; - - assign write_budget_left_12_re = addr_hit[118] & reg_re & !reg_error; - - assign write_budget_left_13_re = addr_hit[119] & reg_re & !reg_error; - - assign write_budget_left_14_re = addr_hit[120] & reg_re & !reg_error; - - assign write_budget_left_15_re = addr_hit[121] & reg_re & !reg_error; - - assign write_budget_left_16_re = addr_hit[122] & reg_re & !reg_error; - - assign write_budget_left_17_re = addr_hit[123] & reg_re & !reg_error; - - assign write_budget_left_18_re = addr_hit[124] & reg_re & !reg_error; - - assign write_budget_left_19_re = addr_hit[125] & reg_re & !reg_error; - - assign write_budget_left_20_re = addr_hit[126] & reg_re & !reg_error; - - assign write_budget_left_21_re = addr_hit[127] & reg_re & !reg_error; - - assign write_budget_left_22_re = addr_hit[128] & reg_re & !reg_error; - - assign write_budget_left_23_re = addr_hit[129] & reg_re & !reg_error; - - assign read_budget_left_0_re = addr_hit[130] & reg_re & !reg_error; - - assign read_budget_left_1_re = addr_hit[131] & reg_re & !reg_error; - - assign read_budget_left_2_re = addr_hit[132] & reg_re & !reg_error; - - assign read_budget_left_3_re = addr_hit[133] & reg_re & !reg_error; - - assign read_budget_left_4_re = addr_hit[134] & reg_re & !reg_error; - - assign read_budget_left_5_re = addr_hit[135] & reg_re & !reg_error; - - assign read_budget_left_6_re = addr_hit[136] & reg_re & !reg_error; - - assign read_budget_left_7_re = addr_hit[137] & reg_re & !reg_error; - - assign read_budget_left_8_re = addr_hit[138] & reg_re & !reg_error; - - assign read_budget_left_9_re = addr_hit[139] & reg_re & !reg_error; - - assign read_budget_left_10_re = addr_hit[140] & reg_re & !reg_error; - - assign read_budget_left_11_re = addr_hit[141] & reg_re & !reg_error; - - assign read_budget_left_12_re = addr_hit[142] & reg_re & !reg_error; - - assign read_budget_left_13_re = addr_hit[143] & reg_re & !reg_error; - - assign read_budget_left_14_re = addr_hit[144] & reg_re & !reg_error; - - assign read_budget_left_15_re = addr_hit[145] & reg_re & !reg_error; - - assign read_budget_left_16_re = addr_hit[146] & reg_re & !reg_error; - - assign read_budget_left_17_re = addr_hit[147] & reg_re & !reg_error; - - assign read_budget_left_18_re = addr_hit[148] & reg_re & !reg_error; - - assign read_budget_left_19_re = addr_hit[149] & reg_re & !reg_error; - - assign read_budget_left_20_re = addr_hit[150] & reg_re & !reg_error; - - assign read_budget_left_21_re = addr_hit[151] & reg_re & !reg_error; - - assign read_budget_left_22_re = addr_hit[152] & reg_re & !reg_error; - - assign read_budget_left_23_re = addr_hit[153] & reg_re & !reg_error; - - assign write_period_left_0_re = addr_hit[154] & reg_re & !reg_error; - - assign write_period_left_1_re = addr_hit[155] & reg_re & !reg_error; - - assign write_period_left_2_re = addr_hit[156] & reg_re & !reg_error; - - assign write_period_left_3_re = addr_hit[157] & reg_re & !reg_error; - - assign write_period_left_4_re = addr_hit[158] & reg_re & !reg_error; - - assign write_period_left_5_re = addr_hit[159] & reg_re & !reg_error; - - assign write_period_left_6_re = addr_hit[160] & reg_re & !reg_error; - - assign write_period_left_7_re = addr_hit[161] & reg_re & !reg_error; - - assign write_period_left_8_re = addr_hit[162] & reg_re & !reg_error; - - assign write_period_left_9_re = addr_hit[163] & reg_re & !reg_error; - - assign write_period_left_10_re = addr_hit[164] & reg_re & !reg_error; - - assign write_period_left_11_re = addr_hit[165] & reg_re & !reg_error; - - assign write_period_left_12_re = addr_hit[166] & reg_re & !reg_error; - - assign write_period_left_13_re = addr_hit[167] & reg_re & !reg_error; - - assign write_period_left_14_re = addr_hit[168] & reg_re & !reg_error; - - assign write_period_left_15_re = addr_hit[169] & reg_re & !reg_error; - - assign write_period_left_16_re = addr_hit[170] & reg_re & !reg_error; - - assign write_period_left_17_re = addr_hit[171] & reg_re & !reg_error; - - assign write_period_left_18_re = addr_hit[172] & reg_re & !reg_error; - - assign write_period_left_19_re = addr_hit[173] & reg_re & !reg_error; - - assign write_period_left_20_re = addr_hit[174] & reg_re & !reg_error; - - assign write_period_left_21_re = addr_hit[175] & reg_re & !reg_error; - - assign write_period_left_22_re = addr_hit[176] & reg_re & !reg_error; - - assign write_period_left_23_re = addr_hit[177] & reg_re & !reg_error; - - assign read_period_left_0_re = addr_hit[178] & reg_re & !reg_error; - - assign read_period_left_1_re = addr_hit[179] & reg_re & !reg_error; - - assign read_period_left_2_re = addr_hit[180] & reg_re & !reg_error; - - assign read_period_left_3_re = addr_hit[181] & reg_re & !reg_error; - - assign read_period_left_4_re = addr_hit[182] & reg_re & !reg_error; - - assign read_period_left_5_re = addr_hit[183] & reg_re & !reg_error; - - assign read_period_left_6_re = addr_hit[184] & reg_re & !reg_error; - - assign read_period_left_7_re = addr_hit[185] & reg_re & !reg_error; - - assign read_period_left_8_re = addr_hit[186] & reg_re & !reg_error; - - assign read_period_left_9_re = addr_hit[187] & reg_re & !reg_error; - - assign read_period_left_10_re = addr_hit[188] & reg_re & !reg_error; - - assign read_period_left_11_re = addr_hit[189] & reg_re & !reg_error; - - assign read_period_left_12_re = addr_hit[190] & reg_re & !reg_error; - - assign read_period_left_13_re = addr_hit[191] & reg_re & !reg_error; - - assign read_period_left_14_re = addr_hit[192] & reg_re & !reg_error; - - assign read_period_left_15_re = addr_hit[193] & reg_re & !reg_error; - - assign read_period_left_16_re = addr_hit[194] & reg_re & !reg_error; - - assign read_period_left_17_re = addr_hit[195] & reg_re & !reg_error; - - assign read_period_left_18_re = addr_hit[196] & reg_re & !reg_error; - - assign read_period_left_19_re = addr_hit[197] & reg_re & !reg_error; - - assign read_period_left_20_re = addr_hit[198] & reg_re & !reg_error; - - assign read_period_left_21_re = addr_hit[199] & reg_re & !reg_error; - - assign read_period_left_22_re = addr_hit[200] & reg_re & !reg_error; - - assign read_period_left_23_re = addr_hit[201] & reg_re & !reg_error; - - assign isolate_isolate_0_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_1_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_2_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_3_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_4_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_5_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_6_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_7_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_8_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_9_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_10_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_11_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_12_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_13_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_14_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_15_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_16_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_17_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_18_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_19_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_20_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_21_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_22_re = addr_hit[202] & reg_re & !reg_error; - - assign isolate_isolate_23_re = addr_hit[202] & reg_re & !reg_error; - - assign isolated_isolated_0_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_1_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_2_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_3_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_4_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_5_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_6_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_7_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_8_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_9_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_10_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_11_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_12_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_13_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_14_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_15_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_16_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_17_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_18_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_19_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_20_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_21_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_22_re = addr_hit[203] & reg_re & !reg_error; - - assign isolated_isolated_23_re = addr_hit[203] & reg_re & !reg_error; - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = rt_enable_enable_0_qs; - reg_rdata_next[1] = rt_enable_enable_1_qs; - reg_rdata_next[2] = rt_enable_enable_2_qs; - reg_rdata_next[3] = rt_enable_enable_3_qs; - reg_rdata_next[4] = rt_enable_enable_4_qs; - reg_rdata_next[5] = rt_enable_enable_5_qs; - reg_rdata_next[6] = rt_enable_enable_6_qs; - reg_rdata_next[7] = rt_enable_enable_7_qs; - reg_rdata_next[8] = rt_enable_enable_8_qs; - reg_rdata_next[9] = rt_enable_enable_9_qs; - reg_rdata_next[10] = rt_enable_enable_10_qs; - reg_rdata_next[11] = rt_enable_enable_11_qs; - reg_rdata_next[12] = rt_enable_enable_12_qs; - reg_rdata_next[13] = rt_enable_enable_13_qs; - reg_rdata_next[14] = rt_enable_enable_14_qs; - reg_rdata_next[15] = rt_enable_enable_15_qs; - reg_rdata_next[16] = rt_enable_enable_16_qs; - reg_rdata_next[17] = rt_enable_enable_17_qs; - reg_rdata_next[18] = rt_enable_enable_18_qs; - reg_rdata_next[19] = rt_enable_enable_19_qs; - reg_rdata_next[20] = rt_enable_enable_20_qs; - reg_rdata_next[21] = rt_enable_enable_21_qs; - reg_rdata_next[22] = rt_enable_enable_22_qs; - reg_rdata_next[23] = rt_enable_enable_23_qs; - end - - addr_hit[1]: begin - reg_rdata_next[0] = rt_bypassed_bypassed_0_qs; - reg_rdata_next[1] = rt_bypassed_bypassed_1_qs; - reg_rdata_next[2] = rt_bypassed_bypassed_2_qs; - reg_rdata_next[3] = rt_bypassed_bypassed_3_qs; - reg_rdata_next[4] = rt_bypassed_bypassed_4_qs; - reg_rdata_next[5] = rt_bypassed_bypassed_5_qs; - reg_rdata_next[6] = rt_bypassed_bypassed_6_qs; - reg_rdata_next[7] = rt_bypassed_bypassed_7_qs; - reg_rdata_next[8] = rt_bypassed_bypassed_8_qs; - reg_rdata_next[9] = rt_bypassed_bypassed_9_qs; - reg_rdata_next[10] = rt_bypassed_bypassed_10_qs; - reg_rdata_next[11] = rt_bypassed_bypassed_11_qs; - reg_rdata_next[12] = rt_bypassed_bypassed_12_qs; - reg_rdata_next[13] = rt_bypassed_bypassed_13_qs; - reg_rdata_next[14] = rt_bypassed_bypassed_14_qs; - reg_rdata_next[15] = rt_bypassed_bypassed_15_qs; - reg_rdata_next[16] = rt_bypassed_bypassed_16_qs; - reg_rdata_next[17] = rt_bypassed_bypassed_17_qs; - reg_rdata_next[18] = rt_bypassed_bypassed_18_qs; - reg_rdata_next[19] = rt_bypassed_bypassed_19_qs; - reg_rdata_next[20] = rt_bypassed_bypassed_20_qs; - reg_rdata_next[21] = rt_bypassed_bypassed_21_qs; - reg_rdata_next[22] = rt_bypassed_bypassed_22_qs; - reg_rdata_next[23] = rt_bypassed_bypassed_23_qs; - end - - addr_hit[2]: begin - reg_rdata_next[7:0] = len_limit_0_len_0_qs; - reg_rdata_next[15:8] = len_limit_0_len_1_qs; - reg_rdata_next[23:16] = len_limit_0_len_2_qs; - reg_rdata_next[31:24] = len_limit_0_len_3_qs; - end - - addr_hit[3]: begin - reg_rdata_next[7:0] = len_limit_1_len_4_qs; - reg_rdata_next[15:8] = len_limit_1_len_5_qs; - reg_rdata_next[23:16] = len_limit_1_len_6_qs; - reg_rdata_next[31:24] = len_limit_1_len_7_qs; - end - - addr_hit[4]: begin - reg_rdata_next[7:0] = len_limit_2_len_8_qs; - reg_rdata_next[15:8] = len_limit_2_len_9_qs; - reg_rdata_next[23:16] = len_limit_2_len_10_qs; - reg_rdata_next[31:24] = len_limit_2_len_11_qs; - end - - addr_hit[5]: begin - reg_rdata_next[7:0] = len_limit_3_len_12_qs; - reg_rdata_next[15:8] = len_limit_3_len_13_qs; - reg_rdata_next[23:16] = len_limit_3_len_14_qs; - reg_rdata_next[31:24] = len_limit_3_len_15_qs; - end - - addr_hit[6]: begin - reg_rdata_next[7:0] = len_limit_4_len_16_qs; - reg_rdata_next[15:8] = len_limit_4_len_17_qs; - reg_rdata_next[23:16] = len_limit_4_len_18_qs; - reg_rdata_next[31:24] = len_limit_4_len_19_qs; - end - - addr_hit[7]: begin - reg_rdata_next[7:0] = len_limit_5_len_20_qs; - reg_rdata_next[15:8] = len_limit_5_len_21_qs; - reg_rdata_next[23:16] = len_limit_5_len_22_qs; - reg_rdata_next[31:24] = len_limit_5_len_23_qs; - end - - addr_hit[8]: begin - reg_rdata_next[0] = imtu_enable_enable_0_qs; - reg_rdata_next[1] = imtu_enable_enable_1_qs; - reg_rdata_next[2] = imtu_enable_enable_2_qs; - reg_rdata_next[3] = imtu_enable_enable_3_qs; - reg_rdata_next[4] = imtu_enable_enable_4_qs; - reg_rdata_next[5] = imtu_enable_enable_5_qs; - reg_rdata_next[6] = imtu_enable_enable_6_qs; - reg_rdata_next[7] = imtu_enable_enable_7_qs; - reg_rdata_next[8] = imtu_enable_enable_8_qs; - reg_rdata_next[9] = imtu_enable_enable_9_qs; - reg_rdata_next[10] = imtu_enable_enable_10_qs; - reg_rdata_next[11] = imtu_enable_enable_11_qs; - reg_rdata_next[12] = imtu_enable_enable_12_qs; - reg_rdata_next[13] = imtu_enable_enable_13_qs; - reg_rdata_next[14] = imtu_enable_enable_14_qs; - reg_rdata_next[15] = imtu_enable_enable_15_qs; - reg_rdata_next[16] = imtu_enable_enable_16_qs; - reg_rdata_next[17] = imtu_enable_enable_17_qs; - reg_rdata_next[18] = imtu_enable_enable_18_qs; - reg_rdata_next[19] = imtu_enable_enable_19_qs; - reg_rdata_next[20] = imtu_enable_enable_20_qs; - reg_rdata_next[21] = imtu_enable_enable_21_qs; - reg_rdata_next[22] = imtu_enable_enable_22_qs; - reg_rdata_next[23] = imtu_enable_enable_23_qs; - end - - addr_hit[9]: begin - reg_rdata_next[0] = imtu_abort_abort_0_qs; - reg_rdata_next[1] = imtu_abort_abort_1_qs; - reg_rdata_next[2] = imtu_abort_abort_2_qs; - reg_rdata_next[3] = imtu_abort_abort_3_qs; - reg_rdata_next[4] = imtu_abort_abort_4_qs; - reg_rdata_next[5] = imtu_abort_abort_5_qs; - reg_rdata_next[6] = imtu_abort_abort_6_qs; - reg_rdata_next[7] = imtu_abort_abort_7_qs; - reg_rdata_next[8] = imtu_abort_abort_8_qs; - reg_rdata_next[9] = imtu_abort_abort_9_qs; - reg_rdata_next[10] = imtu_abort_abort_10_qs; - reg_rdata_next[11] = imtu_abort_abort_11_qs; - reg_rdata_next[12] = imtu_abort_abort_12_qs; - reg_rdata_next[13] = imtu_abort_abort_13_qs; - reg_rdata_next[14] = imtu_abort_abort_14_qs; - reg_rdata_next[15] = imtu_abort_abort_15_qs; - reg_rdata_next[16] = imtu_abort_abort_16_qs; - reg_rdata_next[17] = imtu_abort_abort_17_qs; - reg_rdata_next[18] = imtu_abort_abort_18_qs; - reg_rdata_next[19] = imtu_abort_abort_19_qs; - reg_rdata_next[20] = imtu_abort_abort_20_qs; - reg_rdata_next[21] = imtu_abort_abort_21_qs; - reg_rdata_next[22] = imtu_abort_abort_22_qs; - reg_rdata_next[23] = imtu_abort_abort_23_qs; - end - - addr_hit[10]: begin - reg_rdata_next[31:0] = write_budget_0_qs; - end - - addr_hit[11]: begin - reg_rdata_next[31:0] = write_budget_1_qs; - end - - addr_hit[12]: begin - reg_rdata_next[31:0] = write_budget_2_qs; - end - - addr_hit[13]: begin - reg_rdata_next[31:0] = write_budget_3_qs; - end - - addr_hit[14]: begin - reg_rdata_next[31:0] = write_budget_4_qs; - end - - addr_hit[15]: begin - reg_rdata_next[31:0] = write_budget_5_qs; - end - - addr_hit[16]: begin - reg_rdata_next[31:0] = write_budget_6_qs; - end - - addr_hit[17]: begin - reg_rdata_next[31:0] = write_budget_7_qs; - end - - addr_hit[18]: begin - reg_rdata_next[31:0] = write_budget_8_qs; - end - - addr_hit[19]: begin - reg_rdata_next[31:0] = write_budget_9_qs; - end - - addr_hit[20]: begin - reg_rdata_next[31:0] = write_budget_10_qs; - end - - addr_hit[21]: begin - reg_rdata_next[31:0] = write_budget_11_qs; - end - - addr_hit[22]: begin - reg_rdata_next[31:0] = write_budget_12_qs; - end - - addr_hit[23]: begin - reg_rdata_next[31:0] = write_budget_13_qs; - end - - addr_hit[24]: begin - reg_rdata_next[31:0] = write_budget_14_qs; - end - - addr_hit[25]: begin - reg_rdata_next[31:0] = write_budget_15_qs; - end - - addr_hit[26]: begin - reg_rdata_next[31:0] = write_budget_16_qs; - end - - addr_hit[27]: begin - reg_rdata_next[31:0] = write_budget_17_qs; - end - - addr_hit[28]: begin - reg_rdata_next[31:0] = write_budget_18_qs; - end - - addr_hit[29]: begin - reg_rdata_next[31:0] = write_budget_19_qs; - end - - addr_hit[30]: begin - reg_rdata_next[31:0] = write_budget_20_qs; - end - - addr_hit[31]: begin - reg_rdata_next[31:0] = write_budget_21_qs; - end - - addr_hit[32]: begin - reg_rdata_next[31:0] = write_budget_22_qs; - end - - addr_hit[33]: begin - reg_rdata_next[31:0] = write_budget_23_qs; - end - - addr_hit[34]: begin - reg_rdata_next[31:0] = read_budget_0_qs; - end - - addr_hit[35]: begin - reg_rdata_next[31:0] = read_budget_1_qs; - end - - addr_hit[36]: begin - reg_rdata_next[31:0] = read_budget_2_qs; - end - - addr_hit[37]: begin - reg_rdata_next[31:0] = read_budget_3_qs; - end - - addr_hit[38]: begin - reg_rdata_next[31:0] = read_budget_4_qs; - end - - addr_hit[39]: begin - reg_rdata_next[31:0] = read_budget_5_qs; - end - - addr_hit[40]: begin - reg_rdata_next[31:0] = read_budget_6_qs; - end - - addr_hit[41]: begin - reg_rdata_next[31:0] = read_budget_7_qs; - end - - addr_hit[42]: begin - reg_rdata_next[31:0] = read_budget_8_qs; - end - - addr_hit[43]: begin - reg_rdata_next[31:0] = read_budget_9_qs; - end - - addr_hit[44]: begin - reg_rdata_next[31:0] = read_budget_10_qs; - end - - addr_hit[45]: begin - reg_rdata_next[31:0] = read_budget_11_qs; - end - - addr_hit[46]: begin - reg_rdata_next[31:0] = read_budget_12_qs; - end - - addr_hit[47]: begin - reg_rdata_next[31:0] = read_budget_13_qs; - end - - addr_hit[48]: begin - reg_rdata_next[31:0] = read_budget_14_qs; - end - - addr_hit[49]: begin - reg_rdata_next[31:0] = read_budget_15_qs; - end - - addr_hit[50]: begin - reg_rdata_next[31:0] = read_budget_16_qs; - end - - addr_hit[51]: begin - reg_rdata_next[31:0] = read_budget_17_qs; - end - - addr_hit[52]: begin - reg_rdata_next[31:0] = read_budget_18_qs; - end - - addr_hit[53]: begin - reg_rdata_next[31:0] = read_budget_19_qs; - end - - addr_hit[54]: begin - reg_rdata_next[31:0] = read_budget_20_qs; - end - - addr_hit[55]: begin - reg_rdata_next[31:0] = read_budget_21_qs; - end - - addr_hit[56]: begin - reg_rdata_next[31:0] = read_budget_22_qs; - end - - addr_hit[57]: begin - reg_rdata_next[31:0] = read_budget_23_qs; - end - - addr_hit[58]: begin - reg_rdata_next[31:0] = write_period_0_qs; - end - - addr_hit[59]: begin - reg_rdata_next[31:0] = write_period_1_qs; - end - - addr_hit[60]: begin - reg_rdata_next[31:0] = write_period_2_qs; - end - - addr_hit[61]: begin - reg_rdata_next[31:0] = write_period_3_qs; - end - - addr_hit[62]: begin - reg_rdata_next[31:0] = write_period_4_qs; - end - - addr_hit[63]: begin - reg_rdata_next[31:0] = write_period_5_qs; - end - - addr_hit[64]: begin - reg_rdata_next[31:0] = write_period_6_qs; - end - - addr_hit[65]: begin - reg_rdata_next[31:0] = write_period_7_qs; - end - - addr_hit[66]: begin - reg_rdata_next[31:0] = write_period_8_qs; - end - - addr_hit[67]: begin - reg_rdata_next[31:0] = write_period_9_qs; - end - - addr_hit[68]: begin - reg_rdata_next[31:0] = write_period_10_qs; - end - - addr_hit[69]: begin - reg_rdata_next[31:0] = write_period_11_qs; - end - - addr_hit[70]: begin - reg_rdata_next[31:0] = write_period_12_qs; - end - - addr_hit[71]: begin - reg_rdata_next[31:0] = write_period_13_qs; - end - - addr_hit[72]: begin - reg_rdata_next[31:0] = write_period_14_qs; - end - - addr_hit[73]: begin - reg_rdata_next[31:0] = write_period_15_qs; - end - - addr_hit[74]: begin - reg_rdata_next[31:0] = write_period_16_qs; - end - - addr_hit[75]: begin - reg_rdata_next[31:0] = write_period_17_qs; - end - - addr_hit[76]: begin - reg_rdata_next[31:0] = write_period_18_qs; - end - - addr_hit[77]: begin - reg_rdata_next[31:0] = write_period_19_qs; - end - - addr_hit[78]: begin - reg_rdata_next[31:0] = write_period_20_qs; - end - - addr_hit[79]: begin - reg_rdata_next[31:0] = write_period_21_qs; - end - - addr_hit[80]: begin - reg_rdata_next[31:0] = write_period_22_qs; - end - - addr_hit[81]: begin - reg_rdata_next[31:0] = write_period_23_qs; - end - - addr_hit[82]: begin - reg_rdata_next[31:0] = read_period_0_qs; - end - - addr_hit[83]: begin - reg_rdata_next[31:0] = read_period_1_qs; - end - - addr_hit[84]: begin - reg_rdata_next[31:0] = read_period_2_qs; - end - - addr_hit[85]: begin - reg_rdata_next[31:0] = read_period_3_qs; - end - - addr_hit[86]: begin - reg_rdata_next[31:0] = read_period_4_qs; - end - - addr_hit[87]: begin - reg_rdata_next[31:0] = read_period_5_qs; - end - - addr_hit[88]: begin - reg_rdata_next[31:0] = read_period_6_qs; - end - - addr_hit[89]: begin - reg_rdata_next[31:0] = read_period_7_qs; - end - - addr_hit[90]: begin - reg_rdata_next[31:0] = read_period_8_qs; - end - - addr_hit[91]: begin - reg_rdata_next[31:0] = read_period_9_qs; - end - - addr_hit[92]: begin - reg_rdata_next[31:0] = read_period_10_qs; - end - - addr_hit[93]: begin - reg_rdata_next[31:0] = read_period_11_qs; - end - - addr_hit[94]: begin - reg_rdata_next[31:0] = read_period_12_qs; - end - - addr_hit[95]: begin - reg_rdata_next[31:0] = read_period_13_qs; - end - - addr_hit[96]: begin - reg_rdata_next[31:0] = read_period_14_qs; - end - - addr_hit[97]: begin - reg_rdata_next[31:0] = read_period_15_qs; - end - - addr_hit[98]: begin - reg_rdata_next[31:0] = read_period_16_qs; - end - - addr_hit[99]: begin - reg_rdata_next[31:0] = read_period_17_qs; - end - - addr_hit[100]: begin - reg_rdata_next[31:0] = read_period_18_qs; - end - - addr_hit[101]: begin - reg_rdata_next[31:0] = read_period_19_qs; - end - - addr_hit[102]: begin - reg_rdata_next[31:0] = read_period_20_qs; - end - - addr_hit[103]: begin - reg_rdata_next[31:0] = read_period_21_qs; - end - - addr_hit[104]: begin - reg_rdata_next[31:0] = read_period_22_qs; - end - - addr_hit[105]: begin - reg_rdata_next[31:0] = read_period_23_qs; - end - - addr_hit[106]: begin - reg_rdata_next[31:0] = write_budget_left_0_qs; - end - - addr_hit[107]: begin - reg_rdata_next[31:0] = write_budget_left_1_qs; - end - - addr_hit[108]: begin - reg_rdata_next[31:0] = write_budget_left_2_qs; - end - - addr_hit[109]: begin - reg_rdata_next[31:0] = write_budget_left_3_qs; - end - - addr_hit[110]: begin - reg_rdata_next[31:0] = write_budget_left_4_qs; - end - - addr_hit[111]: begin - reg_rdata_next[31:0] = write_budget_left_5_qs; - end - - addr_hit[112]: begin - reg_rdata_next[31:0] = write_budget_left_6_qs; - end - - addr_hit[113]: begin - reg_rdata_next[31:0] = write_budget_left_7_qs; - end - - addr_hit[114]: begin - reg_rdata_next[31:0] = write_budget_left_8_qs; - end - - addr_hit[115]: begin - reg_rdata_next[31:0] = write_budget_left_9_qs; - end - - addr_hit[116]: begin - reg_rdata_next[31:0] = write_budget_left_10_qs; - end - - addr_hit[117]: begin - reg_rdata_next[31:0] = write_budget_left_11_qs; - end - - addr_hit[118]: begin - reg_rdata_next[31:0] = write_budget_left_12_qs; - end - - addr_hit[119]: begin - reg_rdata_next[31:0] = write_budget_left_13_qs; - end - - addr_hit[120]: begin - reg_rdata_next[31:0] = write_budget_left_14_qs; - end - - addr_hit[121]: begin - reg_rdata_next[31:0] = write_budget_left_15_qs; - end - - addr_hit[122]: begin - reg_rdata_next[31:0] = write_budget_left_16_qs; - end - - addr_hit[123]: begin - reg_rdata_next[31:0] = write_budget_left_17_qs; - end - - addr_hit[124]: begin - reg_rdata_next[31:0] = write_budget_left_18_qs; - end - - addr_hit[125]: begin - reg_rdata_next[31:0] = write_budget_left_19_qs; - end - - addr_hit[126]: begin - reg_rdata_next[31:0] = write_budget_left_20_qs; - end - - addr_hit[127]: begin - reg_rdata_next[31:0] = write_budget_left_21_qs; - end - - addr_hit[128]: begin - reg_rdata_next[31:0] = write_budget_left_22_qs; - end - - addr_hit[129]: begin - reg_rdata_next[31:0] = write_budget_left_23_qs; - end - - addr_hit[130]: begin - reg_rdata_next[31:0] = read_budget_left_0_qs; - end - - addr_hit[131]: begin - reg_rdata_next[31:0] = read_budget_left_1_qs; - end - - addr_hit[132]: begin - reg_rdata_next[31:0] = read_budget_left_2_qs; - end - - addr_hit[133]: begin - reg_rdata_next[31:0] = read_budget_left_3_qs; - end - - addr_hit[134]: begin - reg_rdata_next[31:0] = read_budget_left_4_qs; - end - - addr_hit[135]: begin - reg_rdata_next[31:0] = read_budget_left_5_qs; - end - - addr_hit[136]: begin - reg_rdata_next[31:0] = read_budget_left_6_qs; - end - - addr_hit[137]: begin - reg_rdata_next[31:0] = read_budget_left_7_qs; - end - - addr_hit[138]: begin - reg_rdata_next[31:0] = read_budget_left_8_qs; - end - - addr_hit[139]: begin - reg_rdata_next[31:0] = read_budget_left_9_qs; - end - - addr_hit[140]: begin - reg_rdata_next[31:0] = read_budget_left_10_qs; - end - - addr_hit[141]: begin - reg_rdata_next[31:0] = read_budget_left_11_qs; - end - - addr_hit[142]: begin - reg_rdata_next[31:0] = read_budget_left_12_qs; - end - - addr_hit[143]: begin - reg_rdata_next[31:0] = read_budget_left_13_qs; - end - - addr_hit[144]: begin - reg_rdata_next[31:0] = read_budget_left_14_qs; - end - - addr_hit[145]: begin - reg_rdata_next[31:0] = read_budget_left_15_qs; - end - - addr_hit[146]: begin - reg_rdata_next[31:0] = read_budget_left_16_qs; - end - - addr_hit[147]: begin - reg_rdata_next[31:0] = read_budget_left_17_qs; - end - - addr_hit[148]: begin - reg_rdata_next[31:0] = read_budget_left_18_qs; - end - - addr_hit[149]: begin - reg_rdata_next[31:0] = read_budget_left_19_qs; - end - - addr_hit[150]: begin - reg_rdata_next[31:0] = read_budget_left_20_qs; - end - - addr_hit[151]: begin - reg_rdata_next[31:0] = read_budget_left_21_qs; - end - - addr_hit[152]: begin - reg_rdata_next[31:0] = read_budget_left_22_qs; - end - - addr_hit[153]: begin - reg_rdata_next[31:0] = read_budget_left_23_qs; - end - - addr_hit[154]: begin - reg_rdata_next[31:0] = write_period_left_0_qs; - end - - addr_hit[155]: begin - reg_rdata_next[31:0] = write_period_left_1_qs; - end - - addr_hit[156]: begin - reg_rdata_next[31:0] = write_period_left_2_qs; - end - - addr_hit[157]: begin - reg_rdata_next[31:0] = write_period_left_3_qs; - end - - addr_hit[158]: begin - reg_rdata_next[31:0] = write_period_left_4_qs; - end - - addr_hit[159]: begin - reg_rdata_next[31:0] = write_period_left_5_qs; - end - - addr_hit[160]: begin - reg_rdata_next[31:0] = write_period_left_6_qs; - end - - addr_hit[161]: begin - reg_rdata_next[31:0] = write_period_left_7_qs; - end - - addr_hit[162]: begin - reg_rdata_next[31:0] = write_period_left_8_qs; - end - - addr_hit[163]: begin - reg_rdata_next[31:0] = write_period_left_9_qs; - end - - addr_hit[164]: begin - reg_rdata_next[31:0] = write_period_left_10_qs; - end - - addr_hit[165]: begin - reg_rdata_next[31:0] = write_period_left_11_qs; - end - - addr_hit[166]: begin - reg_rdata_next[31:0] = write_period_left_12_qs; - end - - addr_hit[167]: begin - reg_rdata_next[31:0] = write_period_left_13_qs; - end - - addr_hit[168]: begin - reg_rdata_next[31:0] = write_period_left_14_qs; - end - - addr_hit[169]: begin - reg_rdata_next[31:0] = write_period_left_15_qs; - end - - addr_hit[170]: begin - reg_rdata_next[31:0] = write_period_left_16_qs; - end - - addr_hit[171]: begin - reg_rdata_next[31:0] = write_period_left_17_qs; - end - - addr_hit[172]: begin - reg_rdata_next[31:0] = write_period_left_18_qs; - end - - addr_hit[173]: begin - reg_rdata_next[31:0] = write_period_left_19_qs; - end - - addr_hit[174]: begin - reg_rdata_next[31:0] = write_period_left_20_qs; - end - - addr_hit[175]: begin - reg_rdata_next[31:0] = write_period_left_21_qs; - end - - addr_hit[176]: begin - reg_rdata_next[31:0] = write_period_left_22_qs; - end - - addr_hit[177]: begin - reg_rdata_next[31:0] = write_period_left_23_qs; - end - - addr_hit[178]: begin - reg_rdata_next[31:0] = read_period_left_0_qs; - end - - addr_hit[179]: begin - reg_rdata_next[31:0] = read_period_left_1_qs; - end - - addr_hit[180]: begin - reg_rdata_next[31:0] = read_period_left_2_qs; - end - - addr_hit[181]: begin - reg_rdata_next[31:0] = read_period_left_3_qs; - end - - addr_hit[182]: begin - reg_rdata_next[31:0] = read_period_left_4_qs; - end - - addr_hit[183]: begin - reg_rdata_next[31:0] = read_period_left_5_qs; - end - - addr_hit[184]: begin - reg_rdata_next[31:0] = read_period_left_6_qs; - end - - addr_hit[185]: begin - reg_rdata_next[31:0] = read_period_left_7_qs; - end - - addr_hit[186]: begin - reg_rdata_next[31:0] = read_period_left_8_qs; - end - - addr_hit[187]: begin - reg_rdata_next[31:0] = read_period_left_9_qs; - end - - addr_hit[188]: begin - reg_rdata_next[31:0] = read_period_left_10_qs; - end - - addr_hit[189]: begin - reg_rdata_next[31:0] = read_period_left_11_qs; - end - - addr_hit[190]: begin - reg_rdata_next[31:0] = read_period_left_12_qs; - end - - addr_hit[191]: begin - reg_rdata_next[31:0] = read_period_left_13_qs; - end - - addr_hit[192]: begin - reg_rdata_next[31:0] = read_period_left_14_qs; - end - - addr_hit[193]: begin - reg_rdata_next[31:0] = read_period_left_15_qs; - end - - addr_hit[194]: begin - reg_rdata_next[31:0] = read_period_left_16_qs; - end - - addr_hit[195]: begin - reg_rdata_next[31:0] = read_period_left_17_qs; - end - - addr_hit[196]: begin - reg_rdata_next[31:0] = read_period_left_18_qs; - end - - addr_hit[197]: begin - reg_rdata_next[31:0] = read_period_left_19_qs; - end - - addr_hit[198]: begin - reg_rdata_next[31:0] = read_period_left_20_qs; - end - - addr_hit[199]: begin - reg_rdata_next[31:0] = read_period_left_21_qs; - end - - addr_hit[200]: begin - reg_rdata_next[31:0] = read_period_left_22_qs; - end - - addr_hit[201]: begin - reg_rdata_next[31:0] = read_period_left_23_qs; - end - - addr_hit[202]: begin - reg_rdata_next[0] = isolate_isolate_0_qs; - reg_rdata_next[1] = isolate_isolate_1_qs; - reg_rdata_next[2] = isolate_isolate_2_qs; - reg_rdata_next[3] = isolate_isolate_3_qs; - reg_rdata_next[4] = isolate_isolate_4_qs; - reg_rdata_next[5] = isolate_isolate_5_qs; - reg_rdata_next[6] = isolate_isolate_6_qs; - reg_rdata_next[7] = isolate_isolate_7_qs; - reg_rdata_next[8] = isolate_isolate_8_qs; - reg_rdata_next[9] = isolate_isolate_9_qs; - reg_rdata_next[10] = isolate_isolate_10_qs; - reg_rdata_next[11] = isolate_isolate_11_qs; - reg_rdata_next[12] = isolate_isolate_12_qs; - reg_rdata_next[13] = isolate_isolate_13_qs; - reg_rdata_next[14] = isolate_isolate_14_qs; - reg_rdata_next[15] = isolate_isolate_15_qs; - reg_rdata_next[16] = isolate_isolate_16_qs; - reg_rdata_next[17] = isolate_isolate_17_qs; - reg_rdata_next[18] = isolate_isolate_18_qs; - reg_rdata_next[19] = isolate_isolate_19_qs; - reg_rdata_next[20] = isolate_isolate_20_qs; - reg_rdata_next[21] = isolate_isolate_21_qs; - reg_rdata_next[22] = isolate_isolate_22_qs; - reg_rdata_next[23] = isolate_isolate_23_qs; - end - - addr_hit[203]: begin - reg_rdata_next[0] = isolated_isolated_0_qs; - reg_rdata_next[1] = isolated_isolated_1_qs; - reg_rdata_next[2] = isolated_isolated_2_qs; - reg_rdata_next[3] = isolated_isolated_3_qs; - reg_rdata_next[4] = isolated_isolated_4_qs; - reg_rdata_next[5] = isolated_isolated_5_qs; - reg_rdata_next[6] = isolated_isolated_6_qs; - reg_rdata_next[7] = isolated_isolated_7_qs; - reg_rdata_next[8] = isolated_isolated_8_qs; - reg_rdata_next[9] = isolated_isolated_9_qs; - reg_rdata_next[10] = isolated_isolated_10_qs; - reg_rdata_next[11] = isolated_isolated_11_qs; - reg_rdata_next[12] = isolated_isolated_12_qs; - reg_rdata_next[13] = isolated_isolated_13_qs; - reg_rdata_next[14] = isolated_isolated_14_qs; - reg_rdata_next[15] = isolated_isolated_15_qs; - reg_rdata_next[16] = isolated_isolated_16_qs; - reg_rdata_next[17] = isolated_isolated_17_qs; - reg_rdata_next[18] = isolated_isolated_18_qs; - reg_rdata_next[19] = isolated_isolated_19_qs; - reg_rdata_next[20] = isolated_isolated_20_qs; - reg_rdata_next[21] = isolated_isolated_21_qs; - reg_rdata_next[22] = isolated_isolated_22_qs; - reg_rdata_next[23] = isolated_isolated_23_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) - -endmodule - -module axi_rt_reg_top_intf -#( - parameter int AW = 10, - localparam int DW = 32 -) ( - input logic clk_i, - input logic rst_ni, - REG_BUS.in regbus_slave, - // To HW - output axi_rt_reg_pkg::axi_rt_reg2hw_t reg2hw, // Write - input axi_rt_reg_pkg::axi_rt_hw2reg_t hw2reg, // Read - // Config - input devmode_i // If 1, explicit error return for unmapped register access -); - localparam int unsigned STRB_WIDTH = DW/8; - -`include "register_interface/typedef.svh" -`include "register_interface/assign.svh" - - // Define structs for reg_bus - typedef logic [AW-1:0] addr_t; - typedef logic [DW-1:0] data_t; - typedef logic [STRB_WIDTH-1:0] strb_t; - `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) - - reg_bus_req_t s_reg_req; - reg_bus_rsp_t s_reg_rsp; - - // Assign SV interface to structs - `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) - `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) - - - - axi_rt_reg_top #( - .reg_req_t(reg_bus_req_t), - .reg_rsp_t(reg_bus_rsp_t), - .AW(AW) - ) i_regs ( - .clk_i, - .rst_ni, - .reg_req_i(s_reg_req), - .reg_rsp_o(s_reg_rsp), - .reg2hw, // Write - .hw2reg, // Read - .devmode_i - ); - -endmodule - - diff --git a/hw/regs/axi_rt_regs.hjson b/hw/regs/axi_rt_regs.hjson deleted file mode 100644 index ab03498d..00000000 --- a/hw/regs/axi_rt_regs.hjson +++ /dev/null @@ -1,248 +0,0 @@ -// Copyright 2022 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for details. -// -// Thomas Benz - - -{ - name: "axi_rt" - clock_primary: "clk_i" - bus_interfaces: [ - { protocol: "reg_iface", direction: "device" } - ], - regwidth: 32 - - param_list: [ - { name: "NumMst", - desc: "Number of masters", - type: "int", - default: "24" - } - ], - - registers: [ - - { multireg: - { name: "rt_enable" - desc: "Enable RT feature on master" - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "rt_enable" - resval: "0" - fields: [ - { bits: "0:0", name: "enable", desc: "Enable RT feature on master" } - ] - } - } - - { multireg: - { name: "rt_bypassed" - desc: "Is the RT inactive?" - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "rt_bypassed" - fields: [ - { bits: "0:0", name: "bypassed", desc: "Is the RT inactive?" } - ] - } - } - - { multireg: - { name: "len_limit" - desc: "Fragmentation of the bursts in beats." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "len_limit" - resval: "0" - fields: [ - { bits: "7:0", name: "len", desc: "Fragmentation of the bursts in beats." } - ] - } - } - - { multireg: - { name: "imtu_enable" - desc: "Enables the IMTU." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "imtu_enable" - resval: "0" - fields: [ - { bits: "0:0", name: "enable", desc: "Enables the IMTU." } - ] - } - } - - { multireg: - { name: "imtu_abort" - desc: "Resets both the period and the budget." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "imtu_abort" - resval: "0" - fields: [ - { bits: "0:0", name: "abort", desc: "Resets both the period and the budget." } - ] - } - } - - { multireg: - { name: "write_budget" - desc: "The budget for the writes." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "write_budget" - resval: "0" - fields: [ - { bits: "31:0", name: "write_budget", desc: "The budget for the writes." } - ] - } - } - - { multireg: - { name: "read_budget" - desc: "The budget for the reads." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "read_budget" - resval: "0" - fields: [ - { bits: "31:0", name: "read_budget", desc: "The budget for the reads." } - ] - } - } - - { multireg: - { name: "write_period" - desc: "The period for the writes." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "write_period" - resval: "0" - fields: [ - { bits: "31:0", name: "write_period", desc: "The period for the writes." } - ] - } - } - - { multireg: - { name: "read_period" - desc: "The period for the reads." - swaccess: "rw" - hwaccess: "hro" - count: "NumMst" - cname: "read_period" - resval: "0" - fields: [ - { bits: "31:0", name: "read_period", desc: "The period for the reads." } - ] - } - } - - { multireg: - { name: "write_budget_left" - desc: "The budget left for the writes." - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "write_budget_left" - resval: "0" - fields: [ - { bits: "31:0", name: "write_budget_left", desc: "The budget left for the writes." } - ] - } - } - - { multireg: - { name: "read_budget_left" - desc: "The budget left for the reads." - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "read_budget_left" - resval: "0" - fields: [ - { bits: "31:0", name: "read_budget_left", desc: "The budget left for the reads." } - ] - } - } - - { multireg: - { name: "write_period_left" - desc: "The period left for the writes." - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "write_period_left" - resval: "0" - fields: [ - { bits: "31:0", name: "write_period_left", desc: "The period left for the writes." } - ] - } - } - - { multireg: - { name: "read_period_left" - desc: "The period left for the reads." - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "read_period_left" - resval: "0" - fields: [ - { bits: "31:0", name: "read_period_left", desc: "The period left for the reads." } - ] - } - } - - { multireg: - { name: "isolate" - desc: "Is the interface requested to be isolated?" - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "isolate" - fields: [ - { bits: "0:0", name: "isolate", desc: "Is the interface requested to be isolated?" } - ] - } - } - - { multireg: - { name: "isolated" - desc: "Is the interface isolated?" - swaccess: "ro" - hwaccess: "hwo" - hwqe: "true" - hwext: "true" - count: "NumMst" - cname: "isolated" - fields: [ - { bits: "0:0", name: "isolated", desc: "Is the interface isolated?" } - ] - } - } - ] -} diff --git a/sw/include/params.h b/sw/include/params.h index 2acb5d4f..b1e6990f 100644 --- a/sw/include/params.h +++ b/sw/include/params.h @@ -25,6 +25,8 @@ extern void *__base_vga; extern void *__base_clint; extern void *__base_plic; extern void *__base_dma; +extern void *__base_axirt; +extern void *__base_axirtgrd; extern void *__base_spm; extern void *__base_dram; diff --git a/sw/include/regs/axi_rt.h b/sw/include/regs/axi_rt.h index 05b7b79f..fd0c549a 100644 --- a/sw/include/regs/axi_rt.h +++ b/sw/include/regs/axi_rt.h @@ -13,19 +13,34 @@ #ifdef __cplusplus extern "C" { #endif -// Number of masters -#define AXI_RT_PARAM_NUM_MST 24 +// Maximum number of managers. +#define AXI_RT_PARAM_NUM_MRG 8 + +// Configured number of subordinate regions. +#define AXI_RT_PARAM_NUM_SUB 2 + +// Configured number of required registers. +#define AXI_RT_PARAM_NUM_REG 16 // Register width #define AXI_RT_PARAM_REG_WIDTH 32 +// Value of the major_version. +#define AXI_RT_MAJOR_VERSION_REG_OFFSET 0x0 + +// Value of the minor_version. +#define AXI_RT_MINOR_VERSION_REG_OFFSET 0x4 + +// Value of the patch_version. +#define AXI_RT_PATCH_VERSION_REG_OFFSET 0x8 + // Enable RT feature on master (common parameters) #define AXI_RT_RT_ENABLE_ENABLE_FIELD_WIDTH 1 #define AXI_RT_RT_ENABLE_ENABLE_FIELDS_PER_REG 32 #define AXI_RT_RT_ENABLE_MULTIREG_COUNT 1 // Enable RT feature on master -#define AXI_RT_RT_ENABLE_REG_OFFSET 0x0 +#define AXI_RT_RT_ENABLE_REG_OFFSET 0xc #define AXI_RT_RT_ENABLE_ENABLE_0_BIT 0 #define AXI_RT_RT_ENABLE_ENABLE_1_BIT 1 #define AXI_RT_RT_ENABLE_ENABLE_2_BIT 2 @@ -34,22 +49,6 @@ extern "C" { #define AXI_RT_RT_ENABLE_ENABLE_5_BIT 5 #define AXI_RT_RT_ENABLE_ENABLE_6_BIT 6 #define AXI_RT_RT_ENABLE_ENABLE_7_BIT 7 -#define AXI_RT_RT_ENABLE_ENABLE_8_BIT 8 -#define AXI_RT_RT_ENABLE_ENABLE_9_BIT 9 -#define AXI_RT_RT_ENABLE_ENABLE_10_BIT 10 -#define AXI_RT_RT_ENABLE_ENABLE_11_BIT 11 -#define AXI_RT_RT_ENABLE_ENABLE_12_BIT 12 -#define AXI_RT_RT_ENABLE_ENABLE_13_BIT 13 -#define AXI_RT_RT_ENABLE_ENABLE_14_BIT 14 -#define AXI_RT_RT_ENABLE_ENABLE_15_BIT 15 -#define AXI_RT_RT_ENABLE_ENABLE_16_BIT 16 -#define AXI_RT_RT_ENABLE_ENABLE_17_BIT 17 -#define AXI_RT_RT_ENABLE_ENABLE_18_BIT 18 -#define AXI_RT_RT_ENABLE_ENABLE_19_BIT 19 -#define AXI_RT_RT_ENABLE_ENABLE_20_BIT 20 -#define AXI_RT_RT_ENABLE_ENABLE_21_BIT 21 -#define AXI_RT_RT_ENABLE_ENABLE_22_BIT 22 -#define AXI_RT_RT_ENABLE_ENABLE_23_BIT 23 // Is the RT inactive? (common parameters) #define AXI_RT_RT_BYPASSED_BYPASSED_FIELD_WIDTH 1 @@ -57,7 +56,7 @@ extern "C" { #define AXI_RT_RT_BYPASSED_MULTIREG_COUNT 1 // Is the RT inactive? -#define AXI_RT_RT_BYPASSED_REG_OFFSET 0x4 +#define AXI_RT_RT_BYPASSED_REG_OFFSET 0x10 #define AXI_RT_RT_BYPASSED_BYPASSED_0_BIT 0 #define AXI_RT_RT_BYPASSED_BYPASSED_1_BIT 1 #define AXI_RT_RT_BYPASSED_BYPASSED_2_BIT 2 @@ -66,30 +65,14 @@ extern "C" { #define AXI_RT_RT_BYPASSED_BYPASSED_5_BIT 5 #define AXI_RT_RT_BYPASSED_BYPASSED_6_BIT 6 #define AXI_RT_RT_BYPASSED_BYPASSED_7_BIT 7 -#define AXI_RT_RT_BYPASSED_BYPASSED_8_BIT 8 -#define AXI_RT_RT_BYPASSED_BYPASSED_9_BIT 9 -#define AXI_RT_RT_BYPASSED_BYPASSED_10_BIT 10 -#define AXI_RT_RT_BYPASSED_BYPASSED_11_BIT 11 -#define AXI_RT_RT_BYPASSED_BYPASSED_12_BIT 12 -#define AXI_RT_RT_BYPASSED_BYPASSED_13_BIT 13 -#define AXI_RT_RT_BYPASSED_BYPASSED_14_BIT 14 -#define AXI_RT_RT_BYPASSED_BYPASSED_15_BIT 15 -#define AXI_RT_RT_BYPASSED_BYPASSED_16_BIT 16 -#define AXI_RT_RT_BYPASSED_BYPASSED_17_BIT 17 -#define AXI_RT_RT_BYPASSED_BYPASSED_18_BIT 18 -#define AXI_RT_RT_BYPASSED_BYPASSED_19_BIT 19 -#define AXI_RT_RT_BYPASSED_BYPASSED_20_BIT 20 -#define AXI_RT_RT_BYPASSED_BYPASSED_21_BIT 21 -#define AXI_RT_RT_BYPASSED_BYPASSED_22_BIT 22 -#define AXI_RT_RT_BYPASSED_BYPASSED_23_BIT 23 // Fragmentation of the bursts in beats. (common parameters) #define AXI_RT_LEN_LIMIT_LEN_FIELD_WIDTH 8 #define AXI_RT_LEN_LIMIT_LEN_FIELDS_PER_REG 4 -#define AXI_RT_LEN_LIMIT_MULTIREG_COUNT 6 +#define AXI_RT_LEN_LIMIT_MULTIREG_COUNT 2 // Fragmentation of the bursts in beats. -#define AXI_RT_LEN_LIMIT_0_REG_OFFSET 0x8 +#define AXI_RT_LEN_LIMIT_0_REG_OFFSET 0x14 #define AXI_RT_LEN_LIMIT_0_LEN_0_MASK 0xff #define AXI_RT_LEN_LIMIT_0_LEN_0_OFFSET 0 #define AXI_RT_LEN_LIMIT_0_LEN_0_FIELD \ @@ -108,7 +91,7 @@ extern "C" { ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_0_LEN_3_MASK, .index = AXI_RT_LEN_LIMIT_0_LEN_3_OFFSET }) // Fragmentation of the bursts in beats. -#define AXI_RT_LEN_LIMIT_1_REG_OFFSET 0xc +#define AXI_RT_LEN_LIMIT_1_REG_OFFSET 0x18 #define AXI_RT_LEN_LIMIT_1_LEN_4_MASK 0xff #define AXI_RT_LEN_LIMIT_1_LEN_4_OFFSET 0 #define AXI_RT_LEN_LIMIT_1_LEN_4_FIELD \ @@ -126,89 +109,13 @@ extern "C" { #define AXI_RT_LEN_LIMIT_1_LEN_7_FIELD \ ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_1_LEN_7_MASK, .index = AXI_RT_LEN_LIMIT_1_LEN_7_OFFSET }) -// Fragmentation of the bursts in beats. -#define AXI_RT_LEN_LIMIT_2_REG_OFFSET 0x10 -#define AXI_RT_LEN_LIMIT_2_LEN_8_MASK 0xff -#define AXI_RT_LEN_LIMIT_2_LEN_8_OFFSET 0 -#define AXI_RT_LEN_LIMIT_2_LEN_8_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_2_LEN_8_MASK, .index = AXI_RT_LEN_LIMIT_2_LEN_8_OFFSET }) -#define AXI_RT_LEN_LIMIT_2_LEN_9_MASK 0xff -#define AXI_RT_LEN_LIMIT_2_LEN_9_OFFSET 8 -#define AXI_RT_LEN_LIMIT_2_LEN_9_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_2_LEN_9_MASK, .index = AXI_RT_LEN_LIMIT_2_LEN_9_OFFSET }) -#define AXI_RT_LEN_LIMIT_2_LEN_10_MASK 0xff -#define AXI_RT_LEN_LIMIT_2_LEN_10_OFFSET 16 -#define AXI_RT_LEN_LIMIT_2_LEN_10_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_2_LEN_10_MASK, .index = AXI_RT_LEN_LIMIT_2_LEN_10_OFFSET }) -#define AXI_RT_LEN_LIMIT_2_LEN_11_MASK 0xff -#define AXI_RT_LEN_LIMIT_2_LEN_11_OFFSET 24 -#define AXI_RT_LEN_LIMIT_2_LEN_11_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_2_LEN_11_MASK, .index = AXI_RT_LEN_LIMIT_2_LEN_11_OFFSET }) - -// Fragmentation of the bursts in beats. -#define AXI_RT_LEN_LIMIT_3_REG_OFFSET 0x14 -#define AXI_RT_LEN_LIMIT_3_LEN_12_MASK 0xff -#define AXI_RT_LEN_LIMIT_3_LEN_12_OFFSET 0 -#define AXI_RT_LEN_LIMIT_3_LEN_12_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_3_LEN_12_MASK, .index = AXI_RT_LEN_LIMIT_3_LEN_12_OFFSET }) -#define AXI_RT_LEN_LIMIT_3_LEN_13_MASK 0xff -#define AXI_RT_LEN_LIMIT_3_LEN_13_OFFSET 8 -#define AXI_RT_LEN_LIMIT_3_LEN_13_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_3_LEN_13_MASK, .index = AXI_RT_LEN_LIMIT_3_LEN_13_OFFSET }) -#define AXI_RT_LEN_LIMIT_3_LEN_14_MASK 0xff -#define AXI_RT_LEN_LIMIT_3_LEN_14_OFFSET 16 -#define AXI_RT_LEN_LIMIT_3_LEN_14_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_3_LEN_14_MASK, .index = AXI_RT_LEN_LIMIT_3_LEN_14_OFFSET }) -#define AXI_RT_LEN_LIMIT_3_LEN_15_MASK 0xff -#define AXI_RT_LEN_LIMIT_3_LEN_15_OFFSET 24 -#define AXI_RT_LEN_LIMIT_3_LEN_15_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_3_LEN_15_MASK, .index = AXI_RT_LEN_LIMIT_3_LEN_15_OFFSET }) - -// Fragmentation of the bursts in beats. -#define AXI_RT_LEN_LIMIT_4_REG_OFFSET 0x18 -#define AXI_RT_LEN_LIMIT_4_LEN_16_MASK 0xff -#define AXI_RT_LEN_LIMIT_4_LEN_16_OFFSET 0 -#define AXI_RT_LEN_LIMIT_4_LEN_16_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_4_LEN_16_MASK, .index = AXI_RT_LEN_LIMIT_4_LEN_16_OFFSET }) -#define AXI_RT_LEN_LIMIT_4_LEN_17_MASK 0xff -#define AXI_RT_LEN_LIMIT_4_LEN_17_OFFSET 8 -#define AXI_RT_LEN_LIMIT_4_LEN_17_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_4_LEN_17_MASK, .index = AXI_RT_LEN_LIMIT_4_LEN_17_OFFSET }) -#define AXI_RT_LEN_LIMIT_4_LEN_18_MASK 0xff -#define AXI_RT_LEN_LIMIT_4_LEN_18_OFFSET 16 -#define AXI_RT_LEN_LIMIT_4_LEN_18_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_4_LEN_18_MASK, .index = AXI_RT_LEN_LIMIT_4_LEN_18_OFFSET }) -#define AXI_RT_LEN_LIMIT_4_LEN_19_MASK 0xff -#define AXI_RT_LEN_LIMIT_4_LEN_19_OFFSET 24 -#define AXI_RT_LEN_LIMIT_4_LEN_19_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_4_LEN_19_MASK, .index = AXI_RT_LEN_LIMIT_4_LEN_19_OFFSET }) - -// Fragmentation of the bursts in beats. -#define AXI_RT_LEN_LIMIT_5_REG_OFFSET 0x1c -#define AXI_RT_LEN_LIMIT_5_LEN_20_MASK 0xff -#define AXI_RT_LEN_LIMIT_5_LEN_20_OFFSET 0 -#define AXI_RT_LEN_LIMIT_5_LEN_20_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_5_LEN_20_MASK, .index = AXI_RT_LEN_LIMIT_5_LEN_20_OFFSET }) -#define AXI_RT_LEN_LIMIT_5_LEN_21_MASK 0xff -#define AXI_RT_LEN_LIMIT_5_LEN_21_OFFSET 8 -#define AXI_RT_LEN_LIMIT_5_LEN_21_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_5_LEN_21_MASK, .index = AXI_RT_LEN_LIMIT_5_LEN_21_OFFSET }) -#define AXI_RT_LEN_LIMIT_5_LEN_22_MASK 0xff -#define AXI_RT_LEN_LIMIT_5_LEN_22_OFFSET 16 -#define AXI_RT_LEN_LIMIT_5_LEN_22_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_5_LEN_22_MASK, .index = AXI_RT_LEN_LIMIT_5_LEN_22_OFFSET }) -#define AXI_RT_LEN_LIMIT_5_LEN_23_MASK 0xff -#define AXI_RT_LEN_LIMIT_5_LEN_23_OFFSET 24 -#define AXI_RT_LEN_LIMIT_5_LEN_23_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_5_LEN_23_MASK, .index = AXI_RT_LEN_LIMIT_5_LEN_23_OFFSET }) - // Enables the IMTU. (common parameters) #define AXI_RT_IMTU_ENABLE_ENABLE_FIELD_WIDTH 1 #define AXI_RT_IMTU_ENABLE_ENABLE_FIELDS_PER_REG 32 #define AXI_RT_IMTU_ENABLE_MULTIREG_COUNT 1 // Enables the IMTU. -#define AXI_RT_IMTU_ENABLE_REG_OFFSET 0x20 +#define AXI_RT_IMTU_ENABLE_REG_OFFSET 0x1c #define AXI_RT_IMTU_ENABLE_ENABLE_0_BIT 0 #define AXI_RT_IMTU_ENABLE_ENABLE_1_BIT 1 #define AXI_RT_IMTU_ENABLE_ENABLE_2_BIT 2 @@ -217,22 +124,6 @@ extern "C" { #define AXI_RT_IMTU_ENABLE_ENABLE_5_BIT 5 #define AXI_RT_IMTU_ENABLE_ENABLE_6_BIT 6 #define AXI_RT_IMTU_ENABLE_ENABLE_7_BIT 7 -#define AXI_RT_IMTU_ENABLE_ENABLE_8_BIT 8 -#define AXI_RT_IMTU_ENABLE_ENABLE_9_BIT 9 -#define AXI_RT_IMTU_ENABLE_ENABLE_10_BIT 10 -#define AXI_RT_IMTU_ENABLE_ENABLE_11_BIT 11 -#define AXI_RT_IMTU_ENABLE_ENABLE_12_BIT 12 -#define AXI_RT_IMTU_ENABLE_ENABLE_13_BIT 13 -#define AXI_RT_IMTU_ENABLE_ENABLE_14_BIT 14 -#define AXI_RT_IMTU_ENABLE_ENABLE_15_BIT 15 -#define AXI_RT_IMTU_ENABLE_ENABLE_16_BIT 16 -#define AXI_RT_IMTU_ENABLE_ENABLE_17_BIT 17 -#define AXI_RT_IMTU_ENABLE_ENABLE_18_BIT 18 -#define AXI_RT_IMTU_ENABLE_ENABLE_19_BIT 19 -#define AXI_RT_IMTU_ENABLE_ENABLE_20_BIT 20 -#define AXI_RT_IMTU_ENABLE_ENABLE_21_BIT 21 -#define AXI_RT_IMTU_ENABLE_ENABLE_22_BIT 22 -#define AXI_RT_IMTU_ENABLE_ENABLE_23_BIT 23 // Resets both the period and the budget. (common parameters) #define AXI_RT_IMTU_ABORT_ABORT_FIELD_WIDTH 1 @@ -240,7 +131,7 @@ extern "C" { #define AXI_RT_IMTU_ABORT_MULTIREG_COUNT 1 // Resets both the period and the budget. -#define AXI_RT_IMTU_ABORT_REG_OFFSET 0x24 +#define AXI_RT_IMTU_ABORT_REG_OFFSET 0x20 #define AXI_RT_IMTU_ABORT_ABORT_0_BIT 0 #define AXI_RT_IMTU_ABORT_ABORT_1_BIT 1 #define AXI_RT_IMTU_ABORT_ABORT_2_BIT 2 @@ -249,638 +140,642 @@ extern "C" { #define AXI_RT_IMTU_ABORT_ABORT_5_BIT 5 #define AXI_RT_IMTU_ABORT_ABORT_6_BIT 6 #define AXI_RT_IMTU_ABORT_ABORT_7_BIT 7 -#define AXI_RT_IMTU_ABORT_ABORT_8_BIT 8 -#define AXI_RT_IMTU_ABORT_ABORT_9_BIT 9 -#define AXI_RT_IMTU_ABORT_ABORT_10_BIT 10 -#define AXI_RT_IMTU_ABORT_ABORT_11_BIT 11 -#define AXI_RT_IMTU_ABORT_ABORT_12_BIT 12 -#define AXI_RT_IMTU_ABORT_ABORT_13_BIT 13 -#define AXI_RT_IMTU_ABORT_ABORT_14_BIT 14 -#define AXI_RT_IMTU_ABORT_ABORT_15_BIT 15 -#define AXI_RT_IMTU_ABORT_ABORT_16_BIT 16 -#define AXI_RT_IMTU_ABORT_ABORT_17_BIT 17 -#define AXI_RT_IMTU_ABORT_ABORT_18_BIT 18 -#define AXI_RT_IMTU_ABORT_ABORT_19_BIT 19 -#define AXI_RT_IMTU_ABORT_ABORT_20_BIT 20 -#define AXI_RT_IMTU_ABORT_ABORT_21_BIT 21 -#define AXI_RT_IMTU_ABORT_ABORT_22_BIT 22 -#define AXI_RT_IMTU_ABORT_ABORT_23_BIT 23 - -// The budget for the writes. (common parameters) -#define AXI_RT_WRITE_BUDGET_WRITE_BUDGET_FIELD_WIDTH 32 -#define AXI_RT_WRITE_BUDGET_WRITE_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_BUDGET_MULTIREG_COUNT 24 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_0_REG_OFFSET 0x28 +// The lower 32bit of the start address. (common parameters) +#define AXI_RT_START_ADDR_SUB_LOW_WRITE_BUDGET_FIELD_WIDTH 32 +#define AXI_RT_START_ADDR_SUB_LOW_WRITE_BUDGET_FIELDS_PER_REG 1 +#define AXI_RT_START_ADDR_SUB_LOW_MULTIREG_COUNT 16 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_1_REG_OFFSET 0x2c +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_0_REG_OFFSET 0x24 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_2_REG_OFFSET 0x30 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_1_REG_OFFSET 0x28 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_3_REG_OFFSET 0x34 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_2_REG_OFFSET 0x2c -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_4_REG_OFFSET 0x38 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_3_REG_OFFSET 0x30 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_5_REG_OFFSET 0x3c +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_4_REG_OFFSET 0x34 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_6_REG_OFFSET 0x40 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_5_REG_OFFSET 0x38 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_7_REG_OFFSET 0x44 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_6_REG_OFFSET 0x3c -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_8_REG_OFFSET 0x48 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_7_REG_OFFSET 0x40 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_9_REG_OFFSET 0x4c +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_8_REG_OFFSET 0x44 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_10_REG_OFFSET 0x50 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_9_REG_OFFSET 0x48 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_11_REG_OFFSET 0x54 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_10_REG_OFFSET 0x4c -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_12_REG_OFFSET 0x58 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_11_REG_OFFSET 0x50 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_13_REG_OFFSET 0x5c +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_12_REG_OFFSET 0x54 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_14_REG_OFFSET 0x60 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_13_REG_OFFSET 0x58 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_15_REG_OFFSET 0x64 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_14_REG_OFFSET 0x5c -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_16_REG_OFFSET 0x68 +// The lower 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_LOW_15_REG_OFFSET 0x60 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_17_REG_OFFSET 0x6c +// The higher 32bit of the start address. (common parameters) +#define AXI_RT_START_ADDR_SUB_HIGH_WRITE_BUDGET_FIELD_WIDTH 32 +#define AXI_RT_START_ADDR_SUB_HIGH_WRITE_BUDGET_FIELDS_PER_REG 1 +#define AXI_RT_START_ADDR_SUB_HIGH_MULTIREG_COUNT 16 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_18_REG_OFFSET 0x70 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_0_REG_OFFSET 0x64 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_19_REG_OFFSET 0x74 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_1_REG_OFFSET 0x68 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_20_REG_OFFSET 0x78 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_2_REG_OFFSET 0x6c -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_21_REG_OFFSET 0x7c +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_3_REG_OFFSET 0x70 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_22_REG_OFFSET 0x80 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_4_REG_OFFSET 0x74 -// The budget for the writes. -#define AXI_RT_WRITE_BUDGET_23_REG_OFFSET 0x84 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_5_REG_OFFSET 0x78 -// The budget for the reads. (common parameters) -#define AXI_RT_READ_BUDGET_READ_BUDGET_FIELD_WIDTH 32 -#define AXI_RT_READ_BUDGET_READ_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_READ_BUDGET_MULTIREG_COUNT 24 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_6_REG_OFFSET 0x7c -// The budget for the reads. -#define AXI_RT_READ_BUDGET_0_REG_OFFSET 0x88 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_7_REG_OFFSET 0x80 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_1_REG_OFFSET 0x8c +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_8_REG_OFFSET 0x84 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_2_REG_OFFSET 0x90 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_9_REG_OFFSET 0x88 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_3_REG_OFFSET 0x94 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_10_REG_OFFSET 0x8c -// The budget for the reads. -#define AXI_RT_READ_BUDGET_4_REG_OFFSET 0x98 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_11_REG_OFFSET 0x90 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_5_REG_OFFSET 0x9c +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_12_REG_OFFSET 0x94 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_6_REG_OFFSET 0xa0 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_13_REG_OFFSET 0x98 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_7_REG_OFFSET 0xa4 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_14_REG_OFFSET 0x9c -// The budget for the reads. -#define AXI_RT_READ_BUDGET_8_REG_OFFSET 0xa8 +// The higher 32bit of the start address. +#define AXI_RT_START_ADDR_SUB_HIGH_15_REG_OFFSET 0xa0 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_9_REG_OFFSET 0xac +// The lower 32bit of the end address. (common parameters) +#define AXI_RT_END_ADDR_SUB_LOW_WRITE_BUDGET_FIELD_WIDTH 32 +#define AXI_RT_END_ADDR_SUB_LOW_WRITE_BUDGET_FIELDS_PER_REG 1 +#define AXI_RT_END_ADDR_SUB_LOW_MULTIREG_COUNT 16 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_10_REG_OFFSET 0xb0 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_0_REG_OFFSET 0xa4 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_11_REG_OFFSET 0xb4 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_1_REG_OFFSET 0xa8 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_12_REG_OFFSET 0xb8 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_2_REG_OFFSET 0xac -// The budget for the reads. -#define AXI_RT_READ_BUDGET_13_REG_OFFSET 0xbc +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_3_REG_OFFSET 0xb0 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_14_REG_OFFSET 0xc0 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_4_REG_OFFSET 0xb4 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_15_REG_OFFSET 0xc4 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_5_REG_OFFSET 0xb8 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_16_REG_OFFSET 0xc8 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_6_REG_OFFSET 0xbc -// The budget for the reads. -#define AXI_RT_READ_BUDGET_17_REG_OFFSET 0xcc +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_7_REG_OFFSET 0xc0 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_18_REG_OFFSET 0xd0 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_8_REG_OFFSET 0xc4 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_19_REG_OFFSET 0xd4 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_9_REG_OFFSET 0xc8 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_20_REG_OFFSET 0xd8 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_10_REG_OFFSET 0xcc -// The budget for the reads. -#define AXI_RT_READ_BUDGET_21_REG_OFFSET 0xdc +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_11_REG_OFFSET 0xd0 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_22_REG_OFFSET 0xe0 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_12_REG_OFFSET 0xd4 -// The budget for the reads. -#define AXI_RT_READ_BUDGET_23_REG_OFFSET 0xe4 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_13_REG_OFFSET 0xd8 -// The period for the writes. (common parameters) -#define AXI_RT_WRITE_PERIOD_WRITE_PERIOD_FIELD_WIDTH 32 -#define AXI_RT_WRITE_PERIOD_WRITE_PERIOD_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_PERIOD_MULTIREG_COUNT 24 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_14_REG_OFFSET 0xdc -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_0_REG_OFFSET 0xe8 +// The lower 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_LOW_15_REG_OFFSET 0xe0 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_1_REG_OFFSET 0xec +// The higher 32bit of the end address. (common parameters) +#define AXI_RT_END_ADDR_SUB_HIGH_WRITE_BUDGET_FIELD_WIDTH 32 +#define AXI_RT_END_ADDR_SUB_HIGH_WRITE_BUDGET_FIELDS_PER_REG 1 +#define AXI_RT_END_ADDR_SUB_HIGH_MULTIREG_COUNT 16 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_2_REG_OFFSET 0xf0 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_0_REG_OFFSET 0xe4 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_3_REG_OFFSET 0xf4 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_1_REG_OFFSET 0xe8 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_4_REG_OFFSET 0xf8 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_2_REG_OFFSET 0xec -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_5_REG_OFFSET 0xfc +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_3_REG_OFFSET 0xf0 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_6_REG_OFFSET 0x100 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_4_REG_OFFSET 0xf4 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_7_REG_OFFSET 0x104 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_5_REG_OFFSET 0xf8 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_8_REG_OFFSET 0x108 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_6_REG_OFFSET 0xfc -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_9_REG_OFFSET 0x10c +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_7_REG_OFFSET 0x100 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_10_REG_OFFSET 0x110 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_8_REG_OFFSET 0x104 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_11_REG_OFFSET 0x114 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_9_REG_OFFSET 0x108 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_12_REG_OFFSET 0x118 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_10_REG_OFFSET 0x10c -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_13_REG_OFFSET 0x11c +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_11_REG_OFFSET 0x110 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_14_REG_OFFSET 0x120 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_12_REG_OFFSET 0x114 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_15_REG_OFFSET 0x124 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_13_REG_OFFSET 0x118 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_16_REG_OFFSET 0x128 +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_14_REG_OFFSET 0x11c -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_17_REG_OFFSET 0x12c +// The higher 32bit of the end address. +#define AXI_RT_END_ADDR_SUB_HIGH_15_REG_OFFSET 0x120 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_18_REG_OFFSET 0x130 +// The budget for writes. (common parameters) +#define AXI_RT_WRITE_BUDGET_WRITE_BUDGET_FIELD_WIDTH 32 +#define AXI_RT_WRITE_BUDGET_WRITE_BUDGET_FIELDS_PER_REG 1 +#define AXI_RT_WRITE_BUDGET_MULTIREG_COUNT 16 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_19_REG_OFFSET 0x134 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_0_REG_OFFSET 0x124 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_20_REG_OFFSET 0x138 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_1_REG_OFFSET 0x128 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_21_REG_OFFSET 0x13c +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_2_REG_OFFSET 0x12c -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_22_REG_OFFSET 0x140 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_3_REG_OFFSET 0x130 -// The period for the writes. -#define AXI_RT_WRITE_PERIOD_23_REG_OFFSET 0x144 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_4_REG_OFFSET 0x134 -// The period for the reads. (common parameters) -#define AXI_RT_READ_PERIOD_READ_PERIOD_FIELD_WIDTH 32 -#define AXI_RT_READ_PERIOD_READ_PERIOD_FIELDS_PER_REG 1 -#define AXI_RT_READ_PERIOD_MULTIREG_COUNT 24 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_5_REG_OFFSET 0x138 -// The period for the reads. -#define AXI_RT_READ_PERIOD_0_REG_OFFSET 0x148 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_6_REG_OFFSET 0x13c -// The period for the reads. -#define AXI_RT_READ_PERIOD_1_REG_OFFSET 0x14c +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_7_REG_OFFSET 0x140 -// The period for the reads. -#define AXI_RT_READ_PERIOD_2_REG_OFFSET 0x150 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_8_REG_OFFSET 0x144 -// The period for the reads. -#define AXI_RT_READ_PERIOD_3_REG_OFFSET 0x154 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_9_REG_OFFSET 0x148 -// The period for the reads. -#define AXI_RT_READ_PERIOD_4_REG_OFFSET 0x158 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_10_REG_OFFSET 0x14c -// The period for the reads. -#define AXI_RT_READ_PERIOD_5_REG_OFFSET 0x15c +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_11_REG_OFFSET 0x150 -// The period for the reads. -#define AXI_RT_READ_PERIOD_6_REG_OFFSET 0x160 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_12_REG_OFFSET 0x154 -// The period for the reads. -#define AXI_RT_READ_PERIOD_7_REG_OFFSET 0x164 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_13_REG_OFFSET 0x158 -// The period for the reads. -#define AXI_RT_READ_PERIOD_8_REG_OFFSET 0x168 +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_14_REG_OFFSET 0x15c -// The period for the reads. -#define AXI_RT_READ_PERIOD_9_REG_OFFSET 0x16c +// The budget for writes. +#define AXI_RT_WRITE_BUDGET_15_REG_OFFSET 0x160 -// The period for the reads. -#define AXI_RT_READ_PERIOD_10_REG_OFFSET 0x170 +// The budget for reads. (common parameters) +#define AXI_RT_READ_BUDGET_READ_BUDGET_FIELD_WIDTH 32 +#define AXI_RT_READ_BUDGET_READ_BUDGET_FIELDS_PER_REG 1 +#define AXI_RT_READ_BUDGET_MULTIREG_COUNT 16 -// The period for the reads. -#define AXI_RT_READ_PERIOD_11_REG_OFFSET 0x174 +// The budget for reads. +#define AXI_RT_READ_BUDGET_0_REG_OFFSET 0x164 -// The period for the reads. -#define AXI_RT_READ_PERIOD_12_REG_OFFSET 0x178 +// The budget for reads. +#define AXI_RT_READ_BUDGET_1_REG_OFFSET 0x168 -// The period for the reads. -#define AXI_RT_READ_PERIOD_13_REG_OFFSET 0x17c +// The budget for reads. +#define AXI_RT_READ_BUDGET_2_REG_OFFSET 0x16c -// The period for the reads. -#define AXI_RT_READ_PERIOD_14_REG_OFFSET 0x180 +// The budget for reads. +#define AXI_RT_READ_BUDGET_3_REG_OFFSET 0x170 -// The period for the reads. -#define AXI_RT_READ_PERIOD_15_REG_OFFSET 0x184 +// The budget for reads. +#define AXI_RT_READ_BUDGET_4_REG_OFFSET 0x174 -// The period for the reads. -#define AXI_RT_READ_PERIOD_16_REG_OFFSET 0x188 +// The budget for reads. +#define AXI_RT_READ_BUDGET_5_REG_OFFSET 0x178 -// The period for the reads. -#define AXI_RT_READ_PERIOD_17_REG_OFFSET 0x18c +// The budget for reads. +#define AXI_RT_READ_BUDGET_6_REG_OFFSET 0x17c -// The period for the reads. -#define AXI_RT_READ_PERIOD_18_REG_OFFSET 0x190 +// The budget for reads. +#define AXI_RT_READ_BUDGET_7_REG_OFFSET 0x180 -// The period for the reads. -#define AXI_RT_READ_PERIOD_19_REG_OFFSET 0x194 +// The budget for reads. +#define AXI_RT_READ_BUDGET_8_REG_OFFSET 0x184 -// The period for the reads. -#define AXI_RT_READ_PERIOD_20_REG_OFFSET 0x198 +// The budget for reads. +#define AXI_RT_READ_BUDGET_9_REG_OFFSET 0x188 -// The period for the reads. -#define AXI_RT_READ_PERIOD_21_REG_OFFSET 0x19c +// The budget for reads. +#define AXI_RT_READ_BUDGET_10_REG_OFFSET 0x18c -// The period for the reads. -#define AXI_RT_READ_PERIOD_22_REG_OFFSET 0x1a0 +// The budget for reads. +#define AXI_RT_READ_BUDGET_11_REG_OFFSET 0x190 -// The period for the reads. -#define AXI_RT_READ_PERIOD_23_REG_OFFSET 0x1a4 +// The budget for reads. +#define AXI_RT_READ_BUDGET_12_REG_OFFSET 0x194 -// The budget left for the writes. (common parameters) -#define AXI_RT_WRITE_BUDGET_LEFT_WRITE_BUDGET_LEFT_FIELD_WIDTH 32 -#define AXI_RT_WRITE_BUDGET_LEFT_WRITE_BUDGET_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_BUDGET_LEFT_MULTIREG_COUNT 24 +// The budget for reads. +#define AXI_RT_READ_BUDGET_13_REG_OFFSET 0x198 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_0_REG_OFFSET 0x1a8 +// The budget for reads. +#define AXI_RT_READ_BUDGET_14_REG_OFFSET 0x19c -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_1_REG_OFFSET 0x1ac +// The budget for reads. +#define AXI_RT_READ_BUDGET_15_REG_OFFSET 0x1a0 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_2_REG_OFFSET 0x1b0 +// The period for writes. (common parameters) +#define AXI_RT_WRITE_PERIOD_WRITE_PERIOD_FIELD_WIDTH 32 +#define AXI_RT_WRITE_PERIOD_WRITE_PERIOD_FIELDS_PER_REG 1 +#define AXI_RT_WRITE_PERIOD_MULTIREG_COUNT 16 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_3_REG_OFFSET 0x1b4 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_0_REG_OFFSET 0x1a4 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_4_REG_OFFSET 0x1b8 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_1_REG_OFFSET 0x1a8 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_5_REG_OFFSET 0x1bc +// The period for writes. +#define AXI_RT_WRITE_PERIOD_2_REG_OFFSET 0x1ac -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_6_REG_OFFSET 0x1c0 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_3_REG_OFFSET 0x1b0 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_7_REG_OFFSET 0x1c4 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_4_REG_OFFSET 0x1b4 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_8_REG_OFFSET 0x1c8 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_5_REG_OFFSET 0x1b8 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_9_REG_OFFSET 0x1cc +// The period for writes. +#define AXI_RT_WRITE_PERIOD_6_REG_OFFSET 0x1bc -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_10_REG_OFFSET 0x1d0 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_7_REG_OFFSET 0x1c0 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_11_REG_OFFSET 0x1d4 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_8_REG_OFFSET 0x1c4 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_12_REG_OFFSET 0x1d8 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_9_REG_OFFSET 0x1c8 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_13_REG_OFFSET 0x1dc +// The period for writes. +#define AXI_RT_WRITE_PERIOD_10_REG_OFFSET 0x1cc -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_14_REG_OFFSET 0x1e0 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_11_REG_OFFSET 0x1d0 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_15_REG_OFFSET 0x1e4 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_12_REG_OFFSET 0x1d4 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_16_REG_OFFSET 0x1e8 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_13_REG_OFFSET 0x1d8 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_17_REG_OFFSET 0x1ec +// The period for writes. +#define AXI_RT_WRITE_PERIOD_14_REG_OFFSET 0x1dc -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_18_REG_OFFSET 0x1f0 +// The period for writes. +#define AXI_RT_WRITE_PERIOD_15_REG_OFFSET 0x1e0 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_19_REG_OFFSET 0x1f4 +// The period for reads. (common parameters) +#define AXI_RT_READ_PERIOD_READ_PERIOD_FIELD_WIDTH 32 +#define AXI_RT_READ_PERIOD_READ_PERIOD_FIELDS_PER_REG 1 +#define AXI_RT_READ_PERIOD_MULTIREG_COUNT 16 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_20_REG_OFFSET 0x1f8 +// The period for reads. +#define AXI_RT_READ_PERIOD_0_REG_OFFSET 0x1e4 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_21_REG_OFFSET 0x1fc +// The period for reads. +#define AXI_RT_READ_PERIOD_1_REG_OFFSET 0x1e8 -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_22_REG_OFFSET 0x200 +// The period for reads. +#define AXI_RT_READ_PERIOD_2_REG_OFFSET 0x1ec -// The budget left for the writes. -#define AXI_RT_WRITE_BUDGET_LEFT_23_REG_OFFSET 0x204 +// The period for reads. +#define AXI_RT_READ_PERIOD_3_REG_OFFSET 0x1f0 -// The budget left for the reads. (common parameters) -#define AXI_RT_READ_BUDGET_LEFT_READ_BUDGET_LEFT_FIELD_WIDTH 32 -#define AXI_RT_READ_BUDGET_LEFT_READ_BUDGET_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_READ_BUDGET_LEFT_MULTIREG_COUNT 24 +// The period for reads. +#define AXI_RT_READ_PERIOD_4_REG_OFFSET 0x1f4 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_0_REG_OFFSET 0x208 +// The period for reads. +#define AXI_RT_READ_PERIOD_5_REG_OFFSET 0x1f8 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_1_REG_OFFSET 0x20c +// The period for reads. +#define AXI_RT_READ_PERIOD_6_REG_OFFSET 0x1fc -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_2_REG_OFFSET 0x210 +// The period for reads. +#define AXI_RT_READ_PERIOD_7_REG_OFFSET 0x200 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_3_REG_OFFSET 0x214 +// The period for reads. +#define AXI_RT_READ_PERIOD_8_REG_OFFSET 0x204 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_4_REG_OFFSET 0x218 +// The period for reads. +#define AXI_RT_READ_PERIOD_9_REG_OFFSET 0x208 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_5_REG_OFFSET 0x21c +// The period for reads. +#define AXI_RT_READ_PERIOD_10_REG_OFFSET 0x20c -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_6_REG_OFFSET 0x220 +// The period for reads. +#define AXI_RT_READ_PERIOD_11_REG_OFFSET 0x210 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_7_REG_OFFSET 0x224 +// The period for reads. +#define AXI_RT_READ_PERIOD_12_REG_OFFSET 0x214 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_8_REG_OFFSET 0x228 +// The period for reads. +#define AXI_RT_READ_PERIOD_13_REG_OFFSET 0x218 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_9_REG_OFFSET 0x22c +// The period for reads. +#define AXI_RT_READ_PERIOD_14_REG_OFFSET 0x21c -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_10_REG_OFFSET 0x230 +// The period for reads. +#define AXI_RT_READ_PERIOD_15_REG_OFFSET 0x220 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_11_REG_OFFSET 0x234 +// The budget left for writes. (common parameters) +#define AXI_RT_WRITE_BUDGET_LEFT_WRITE_BUDGET_LEFT_FIELD_WIDTH 32 +#define AXI_RT_WRITE_BUDGET_LEFT_WRITE_BUDGET_LEFT_FIELDS_PER_REG 1 +#define AXI_RT_WRITE_BUDGET_LEFT_MULTIREG_COUNT 16 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_12_REG_OFFSET 0x238 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_0_REG_OFFSET 0x224 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_13_REG_OFFSET 0x23c +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_1_REG_OFFSET 0x228 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_14_REG_OFFSET 0x240 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_2_REG_OFFSET 0x22c -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_15_REG_OFFSET 0x244 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_3_REG_OFFSET 0x230 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_16_REG_OFFSET 0x248 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_4_REG_OFFSET 0x234 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_17_REG_OFFSET 0x24c +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_5_REG_OFFSET 0x238 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_18_REG_OFFSET 0x250 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_6_REG_OFFSET 0x23c -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_19_REG_OFFSET 0x254 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_7_REG_OFFSET 0x240 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_20_REG_OFFSET 0x258 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_8_REG_OFFSET 0x244 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_21_REG_OFFSET 0x25c +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_9_REG_OFFSET 0x248 -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_22_REG_OFFSET 0x260 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_10_REG_OFFSET 0x24c -// The budget left for the reads. -#define AXI_RT_READ_BUDGET_LEFT_23_REG_OFFSET 0x264 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_11_REG_OFFSET 0x250 -// The period left for the writes. (common parameters) -#define AXI_RT_WRITE_PERIOD_LEFT_WRITE_PERIOD_LEFT_FIELD_WIDTH 32 -#define AXI_RT_WRITE_PERIOD_LEFT_WRITE_PERIOD_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_PERIOD_LEFT_MULTIREG_COUNT 24 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_12_REG_OFFSET 0x254 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_0_REG_OFFSET 0x268 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_13_REG_OFFSET 0x258 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_1_REG_OFFSET 0x26c +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_14_REG_OFFSET 0x25c -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_2_REG_OFFSET 0x270 +// The budget left for writes. +#define AXI_RT_WRITE_BUDGET_LEFT_15_REG_OFFSET 0x260 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_3_REG_OFFSET 0x274 +// The budget left for reads. (common parameters) +#define AXI_RT_READ_BUDGET_LEFT_READ_BUDGET_LEFT_FIELD_WIDTH 32 +#define AXI_RT_READ_BUDGET_LEFT_READ_BUDGET_LEFT_FIELDS_PER_REG 1 +#define AXI_RT_READ_BUDGET_LEFT_MULTIREG_COUNT 16 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_4_REG_OFFSET 0x278 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_0_REG_OFFSET 0x264 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_5_REG_OFFSET 0x27c +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_1_REG_OFFSET 0x268 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_6_REG_OFFSET 0x280 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_2_REG_OFFSET 0x26c -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_7_REG_OFFSET 0x284 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_3_REG_OFFSET 0x270 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_8_REG_OFFSET 0x288 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_4_REG_OFFSET 0x274 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_9_REG_OFFSET 0x28c +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_5_REG_OFFSET 0x278 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_10_REG_OFFSET 0x290 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_6_REG_OFFSET 0x27c -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_11_REG_OFFSET 0x294 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_7_REG_OFFSET 0x280 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_12_REG_OFFSET 0x298 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_8_REG_OFFSET 0x284 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_13_REG_OFFSET 0x29c +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_9_REG_OFFSET 0x288 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_14_REG_OFFSET 0x2a0 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_10_REG_OFFSET 0x28c -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_15_REG_OFFSET 0x2a4 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_11_REG_OFFSET 0x290 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_16_REG_OFFSET 0x2a8 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_12_REG_OFFSET 0x294 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_17_REG_OFFSET 0x2ac +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_13_REG_OFFSET 0x298 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_18_REG_OFFSET 0x2b0 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_14_REG_OFFSET 0x29c -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_19_REG_OFFSET 0x2b4 +// The budget left for reads. +#define AXI_RT_READ_BUDGET_LEFT_15_REG_OFFSET 0x2a0 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_20_REG_OFFSET 0x2b8 +// The period left for writes. (common parameters) +#define AXI_RT_WRITE_PERIOD_LEFT_WRITE_PERIOD_LEFT_FIELD_WIDTH 32 +#define AXI_RT_WRITE_PERIOD_LEFT_WRITE_PERIOD_LEFT_FIELDS_PER_REG 1 +#define AXI_RT_WRITE_PERIOD_LEFT_MULTIREG_COUNT 16 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_21_REG_OFFSET 0x2bc +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_0_REG_OFFSET 0x2a4 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_22_REG_OFFSET 0x2c0 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_1_REG_OFFSET 0x2a8 -// The period left for the writes. -#define AXI_RT_WRITE_PERIOD_LEFT_23_REG_OFFSET 0x2c4 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_2_REG_OFFSET 0x2ac -// The period left for the reads. (common parameters) -#define AXI_RT_READ_PERIOD_LEFT_READ_PERIOD_LEFT_FIELD_WIDTH 32 -#define AXI_RT_READ_PERIOD_LEFT_READ_PERIOD_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_READ_PERIOD_LEFT_MULTIREG_COUNT 24 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_3_REG_OFFSET 0x2b0 + +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_4_REG_OFFSET 0x2b4 + +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_5_REG_OFFSET 0x2b8 + +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_6_REG_OFFSET 0x2bc -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_0_REG_OFFSET 0x2c8 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_7_REG_OFFSET 0x2c0 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_1_REG_OFFSET 0x2cc +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_8_REG_OFFSET 0x2c4 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_2_REG_OFFSET 0x2d0 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_9_REG_OFFSET 0x2c8 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_3_REG_OFFSET 0x2d4 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_10_REG_OFFSET 0x2cc -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_4_REG_OFFSET 0x2d8 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_11_REG_OFFSET 0x2d0 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_5_REG_OFFSET 0x2dc +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_12_REG_OFFSET 0x2d4 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_6_REG_OFFSET 0x2e0 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_13_REG_OFFSET 0x2d8 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_7_REG_OFFSET 0x2e4 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_14_REG_OFFSET 0x2dc -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_8_REG_OFFSET 0x2e8 +// The period left for writes. +#define AXI_RT_WRITE_PERIOD_LEFT_15_REG_OFFSET 0x2e0 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_9_REG_OFFSET 0x2ec +// The period left for reads. (common parameters) +#define AXI_RT_READ_PERIOD_LEFT_READ_PERIOD_LEFT_FIELD_WIDTH 32 +#define AXI_RT_READ_PERIOD_LEFT_READ_PERIOD_LEFT_FIELDS_PER_REG 1 +#define AXI_RT_READ_PERIOD_LEFT_MULTIREG_COUNT 16 + +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_0_REG_OFFSET 0x2e4 + +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_1_REG_OFFSET 0x2e8 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_10_REG_OFFSET 0x2f0 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_2_REG_OFFSET 0x2ec -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_11_REG_OFFSET 0x2f4 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_3_REG_OFFSET 0x2f0 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_12_REG_OFFSET 0x2f8 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_4_REG_OFFSET 0x2f4 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_13_REG_OFFSET 0x2fc +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_5_REG_OFFSET 0x2f8 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_14_REG_OFFSET 0x300 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_6_REG_OFFSET 0x2fc -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_15_REG_OFFSET 0x304 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_7_REG_OFFSET 0x300 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_16_REG_OFFSET 0x308 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_8_REG_OFFSET 0x304 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_17_REG_OFFSET 0x30c +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_9_REG_OFFSET 0x308 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_18_REG_OFFSET 0x310 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_10_REG_OFFSET 0x30c -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_19_REG_OFFSET 0x314 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_11_REG_OFFSET 0x310 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_20_REG_OFFSET 0x318 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_12_REG_OFFSET 0x314 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_21_REG_OFFSET 0x31c +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_13_REG_OFFSET 0x318 -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_22_REG_OFFSET 0x320 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_14_REG_OFFSET 0x31c -// The period left for the reads. -#define AXI_RT_READ_PERIOD_LEFT_23_REG_OFFSET 0x324 +// The period left for reads. +#define AXI_RT_READ_PERIOD_LEFT_15_REG_OFFSET 0x320 // Is the interface requested to be isolated? (common parameters) #define AXI_RT_ISOLATE_ISOLATE_FIELD_WIDTH 1 @@ -888,7 +783,7 @@ extern "C" { #define AXI_RT_ISOLATE_MULTIREG_COUNT 1 // Is the interface requested to be isolated? -#define AXI_RT_ISOLATE_REG_OFFSET 0x328 +#define AXI_RT_ISOLATE_REG_OFFSET 0x324 #define AXI_RT_ISOLATE_ISOLATE_0_BIT 0 #define AXI_RT_ISOLATE_ISOLATE_1_BIT 1 #define AXI_RT_ISOLATE_ISOLATE_2_BIT 2 @@ -897,22 +792,6 @@ extern "C" { #define AXI_RT_ISOLATE_ISOLATE_5_BIT 5 #define AXI_RT_ISOLATE_ISOLATE_6_BIT 6 #define AXI_RT_ISOLATE_ISOLATE_7_BIT 7 -#define AXI_RT_ISOLATE_ISOLATE_8_BIT 8 -#define AXI_RT_ISOLATE_ISOLATE_9_BIT 9 -#define AXI_RT_ISOLATE_ISOLATE_10_BIT 10 -#define AXI_RT_ISOLATE_ISOLATE_11_BIT 11 -#define AXI_RT_ISOLATE_ISOLATE_12_BIT 12 -#define AXI_RT_ISOLATE_ISOLATE_13_BIT 13 -#define AXI_RT_ISOLATE_ISOLATE_14_BIT 14 -#define AXI_RT_ISOLATE_ISOLATE_15_BIT 15 -#define AXI_RT_ISOLATE_ISOLATE_16_BIT 16 -#define AXI_RT_ISOLATE_ISOLATE_17_BIT 17 -#define AXI_RT_ISOLATE_ISOLATE_18_BIT 18 -#define AXI_RT_ISOLATE_ISOLATE_19_BIT 19 -#define AXI_RT_ISOLATE_ISOLATE_20_BIT 20 -#define AXI_RT_ISOLATE_ISOLATE_21_BIT 21 -#define AXI_RT_ISOLATE_ISOLATE_22_BIT 22 -#define AXI_RT_ISOLATE_ISOLATE_23_BIT 23 // Is the interface isolated? (common parameters) #define AXI_RT_ISOLATED_ISOLATED_FIELD_WIDTH 1 @@ -920,7 +799,7 @@ extern "C" { #define AXI_RT_ISOLATED_MULTIREG_COUNT 1 // Is the interface isolated? -#define AXI_RT_ISOLATED_REG_OFFSET 0x32c +#define AXI_RT_ISOLATED_REG_OFFSET 0x328 #define AXI_RT_ISOLATED_ISOLATED_0_BIT 0 #define AXI_RT_ISOLATED_ISOLATED_1_BIT 1 #define AXI_RT_ISOLATED_ISOLATED_2_BIT 2 @@ -929,22 +808,39 @@ extern "C" { #define AXI_RT_ISOLATED_ISOLATED_5_BIT 5 #define AXI_RT_ISOLATED_ISOLATED_6_BIT 6 #define AXI_RT_ISOLATED_ISOLATED_7_BIT 7 -#define AXI_RT_ISOLATED_ISOLATED_8_BIT 8 -#define AXI_RT_ISOLATED_ISOLATED_9_BIT 9 -#define AXI_RT_ISOLATED_ISOLATED_10_BIT 10 -#define AXI_RT_ISOLATED_ISOLATED_11_BIT 11 -#define AXI_RT_ISOLATED_ISOLATED_12_BIT 12 -#define AXI_RT_ISOLATED_ISOLATED_13_BIT 13 -#define AXI_RT_ISOLATED_ISOLATED_14_BIT 14 -#define AXI_RT_ISOLATED_ISOLATED_15_BIT 15 -#define AXI_RT_ISOLATED_ISOLATED_16_BIT 16 -#define AXI_RT_ISOLATED_ISOLATED_17_BIT 17 -#define AXI_RT_ISOLATED_ISOLATED_18_BIT 18 -#define AXI_RT_ISOLATED_ISOLATED_19_BIT 19 -#define AXI_RT_ISOLATED_ISOLATED_20_BIT 20 -#define AXI_RT_ISOLATED_ISOLATED_21_BIT 21 -#define AXI_RT_ISOLATED_ISOLATED_22_BIT 22 -#define AXI_RT_ISOLATED_ISOLATED_23_BIT 23 + +// Value of the num_managers parameter. +#define AXI_RT_NUM_MANAGERS_REG_OFFSET 0x32c + +// Value of the addr_width parameter. +#define AXI_RT_ADDR_WIDTH_REG_OFFSET 0x330 + +// Value of the data_width parameter. +#define AXI_RT_DATA_WIDTH_REG_OFFSET 0x334 + +// Value of the id_width parameter. +#define AXI_RT_ID_WIDTH_REG_OFFSET 0x338 + +// Value of the user_width parameter. +#define AXI_RT_USER_WIDTH_REG_OFFSET 0x33c + +// Value of the num_pending parameter. +#define AXI_RT_NUM_PENDING_REG_OFFSET 0x340 + +// Value of the w_buffer_depth parameter. +#define AXI_RT_W_BUFFER_DEPTH_REG_OFFSET 0x344 + +// Value of the num_addr_regions parameter. +#define AXI_RT_NUM_ADDR_REGIONS_REG_OFFSET 0x348 + +// Value of the period_width parameter. +#define AXI_RT_PERIOD_WIDTH_REG_OFFSET 0x34c + +// Value of the budget_width parameter. +#define AXI_RT_BUDGET_WIDTH_REG_OFFSET 0x350 + +// Value of the max_num_managers parameter. +#define AXI_RT_MAX_NUM_MANAGERS_REG_OFFSET 0x354 #ifdef __cplusplus } // extern "C" diff --git a/sw/link/common.ldh b/sw/link/common.ldh index 66080e4e..b9bdb43c 100644 --- a/sw/link/common.ldh +++ b/sw/link/common.ldh @@ -33,6 +33,8 @@ SECTIONS { __base_dma = 0x01000000; __base_bootrom = 0x02000000; __base_clint = 0x02040000; + __base_axirt = 0x020C0000; + __base_axirtgrd = 0x020C1ffc; __base_regs = 0x03000000; __base_llc = 0x03001000; __base_uart = 0x03002000; diff --git a/sw/sw.mk b/sw/sw.mk index 07ed3637..c4e0709d 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -38,10 +38,12 @@ CHS_SW_ALL += $(CHS_SW_LIBS) $(CHS_SW_GEN_HDRS) $(CHS_SW_TESTS) CHS_SW_DEPS_INCS = -I$(CHS_SW_DIR)/deps/printf CHS_SW_DEPS_INCS += -I$(CHS_LLC_DIR)/sw/include +CHS_SW_DEPS_INCS += -I$(AXIRTROOT)/sw/lib CHS_SW_DEPS_INCS += -I$(OTPROOT) CHS_SW_DEPS_INCS += -I$(OTPROOT)/sw/include CHS_SW_DEPS_SRCS = $(CHS_SW_DIR)/deps/printf/printf.c CHS_SW_DEPS_SRCS += $(CHS_LLC_DIR)/sw/lib/axi_llc_reg32.c +CHS_SW_DEPS_SRCS += $(AXIRTROOT)/sw/lib/axirt.c CHS_SW_DEPS_SRCS += $(wildcard $(OTPROOT)/sw/device/lib/base/*.c) CHS_SW_DEPS_SRCS += $(wildcard $(OTPROOT)/sw/device/lib/dif/*.c) CHS_SW_DEPS_SRCS += $(wildcard $(OTPROOT)/sw/device/lib/dif/autogen/*.c) @@ -80,7 +82,7 @@ $(eval $(call chs_sw_gen_hdr_rule,axi_vga,$(AXI_VGA_ROOT)/data/axi_vga.hjson $(A $(eval $(call chs_sw_gen_hdr_rule,idma,$(IDMA_ROOT)/src/frontends/register_64bit_2d/idma_reg64_2d_frontend.hjson)) $(eval $(call chs_sw_gen_hdr_rule,axi_llc,$(CHS_LLC_DIR)/data/axi_llc_regs.hjson)) $(eval $(call chs_sw_gen_hdr_rule,cheshire,$(CHS_ROOT)/hw/regs/cheshire_regs.hjson)) -$(eval $(call chs_sw_gen_hdr_rule,axi_rt,$(CHS_ROOT)/hw/regs/axi_rt_regs.hjson)) +$(eval $(call chs_sw_gen_hdr_rule,axi_rt,$(AXIRTROOT)/src/regs/axi_rt.hjson $(AXIRTROOT)/.generated)) # Generate headers for OT peripherals in the bendered repo itself CHS_SW_GEN_HDRS += $(OTPROOT)/.generated diff --git a/sw/tests/helloaxirt.c b/sw/tests/helloaxirt.c new file mode 100644 index 00000000..bc67fc9e --- /dev/null +++ b/sw/tests/helloaxirt.c @@ -0,0 +1,42 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Nicole Narr +// Christopher Reinwardt +// Thomas Benz +// +// Simple payload to test AXI-RT + +#include "regs/cheshire.h" +#include "dif/clint.h" +#include "dif/uart.h" +#include "axirt.h" +#include "regs/axi_rt.h" +#include "params.h" +#include "util.h" + +int main(void) { + char str[] = "Hello AXI-RT!\r\n"; + uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET); + uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500); + + // enable and configure axi rt + __axirt_claim(1, 1); + for (int m = 0; m < AXI_RT_PARAM_NUM_MRG; m++) { + __axirt_set_len_limit(8, m); + __axirt_set_region(0, 0xffffffff, 0, m); + __axirt_set_region(0x100000000, 0xffffffffffffffff, 1, m); + __axirt_set_budget(0x10000000, 0, m); + __axirt_set_budget(0x10000000, 1, m); + __axirt_set_period(0x10000000, 0, m); + __axirt_set_period(0x10000000, 1, m); + } + __axirt_enable(0xffffffff); + + // configure uart and write msg + uart_init(&__base_uart, reset_freq, 115200); + uart_write_str(&__base_uart, str, sizeof(str)); + uart_write_flush(&__base_uart); + return 0; +}