diff --git a/cheshire.mk b/cheshire.mk index d629a7ae..1114f279 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -96,7 +96,7 @@ $(OTPROOT)/.generated: $(CHS_ROOT)/hw/rv_plic.cfg.hjson flock -x $@ sh -c "cp $< $(dir $@)/src/rv_plic/; $(MAKE) -j1 otp" && touch $@ # AXI RT -AXIRT_NUM_MGRS ?= 8 +AXIRT_NUM_MGRS ?= 6 AXIRT_NUM_SUBS ?= 2 include $(AXIRTROOT)/axirt.mk $(AXIRTROOT)/.generated: diff --git a/sw/include/regs/axi_rt.h b/sw/include/regs/axi_rt.h index fd0c549a..a08f041b 100644 --- a/sw/include/regs/axi_rt.h +++ b/sw/include/regs/axi_rt.h @@ -14,13 +14,13 @@ extern "C" { #endif // Maximum number of managers. -#define AXI_RT_PARAM_NUM_MRG 8 +#define AXI_RT_PARAM_NUM_MRG 6 // Configured number of subordinate regions. #define AXI_RT_PARAM_NUM_SUB 2 // Configured number of required registers. -#define AXI_RT_PARAM_NUM_REG 16 +#define AXI_RT_PARAM_NUM_REG 12 // Register width #define AXI_RT_PARAM_REG_WIDTH 32 @@ -47,8 +47,6 @@ extern "C" { #define AXI_RT_RT_ENABLE_ENABLE_3_BIT 3 #define AXI_RT_RT_ENABLE_ENABLE_4_BIT 4 #define AXI_RT_RT_ENABLE_ENABLE_5_BIT 5 -#define AXI_RT_RT_ENABLE_ENABLE_6_BIT 6 -#define AXI_RT_RT_ENABLE_ENABLE_7_BIT 7 // Is the RT inactive? (common parameters) #define AXI_RT_RT_BYPASSED_BYPASSED_FIELD_WIDTH 1 @@ -63,8 +61,6 @@ extern "C" { #define AXI_RT_RT_BYPASSED_BYPASSED_3_BIT 3 #define AXI_RT_RT_BYPASSED_BYPASSED_4_BIT 4 #define AXI_RT_RT_BYPASSED_BYPASSED_5_BIT 5 -#define AXI_RT_RT_BYPASSED_BYPASSED_6_BIT 6 -#define AXI_RT_RT_BYPASSED_BYPASSED_7_BIT 7 // Fragmentation of the bursts in beats. (common parameters) #define AXI_RT_LEN_LIMIT_LEN_FIELD_WIDTH 8 @@ -100,14 +96,6 @@ extern "C" { #define AXI_RT_LEN_LIMIT_1_LEN_5_OFFSET 8 #define AXI_RT_LEN_LIMIT_1_LEN_5_FIELD \ ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_1_LEN_5_MASK, .index = AXI_RT_LEN_LIMIT_1_LEN_5_OFFSET }) -#define AXI_RT_LEN_LIMIT_1_LEN_6_MASK 0xff -#define AXI_RT_LEN_LIMIT_1_LEN_6_OFFSET 16 -#define AXI_RT_LEN_LIMIT_1_LEN_6_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_1_LEN_6_MASK, .index = AXI_RT_LEN_LIMIT_1_LEN_6_OFFSET }) -#define AXI_RT_LEN_LIMIT_1_LEN_7_MASK 0xff -#define AXI_RT_LEN_LIMIT_1_LEN_7_OFFSET 24 -#define AXI_RT_LEN_LIMIT_1_LEN_7_FIELD \ - ((bitfield_field32_t) { .mask = AXI_RT_LEN_LIMIT_1_LEN_7_MASK, .index = AXI_RT_LEN_LIMIT_1_LEN_7_OFFSET }) // Enables the IMTU. (common parameters) #define AXI_RT_IMTU_ENABLE_ENABLE_FIELD_WIDTH 1 @@ -122,8 +110,6 @@ extern "C" { #define AXI_RT_IMTU_ENABLE_ENABLE_3_BIT 3 #define AXI_RT_IMTU_ENABLE_ENABLE_4_BIT 4 #define AXI_RT_IMTU_ENABLE_ENABLE_5_BIT 5 -#define AXI_RT_IMTU_ENABLE_ENABLE_6_BIT 6 -#define AXI_RT_IMTU_ENABLE_ENABLE_7_BIT 7 // Resets both the period and the budget. (common parameters) #define AXI_RT_IMTU_ABORT_ABORT_FIELD_WIDTH 1 @@ -138,13 +124,11 @@ extern "C" { #define AXI_RT_IMTU_ABORT_ABORT_3_BIT 3 #define AXI_RT_IMTU_ABORT_ABORT_4_BIT 4 #define AXI_RT_IMTU_ABORT_ABORT_5_BIT 5 -#define AXI_RT_IMTU_ABORT_ABORT_6_BIT 6 -#define AXI_RT_IMTU_ABORT_ABORT_7_BIT 7 // The lower 32bit of the start address. (common parameters) #define AXI_RT_START_ADDR_SUB_LOW_WRITE_BUDGET_FIELD_WIDTH 32 #define AXI_RT_START_ADDR_SUB_LOW_WRITE_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_START_ADDR_SUB_LOW_MULTIREG_COUNT 16 +#define AXI_RT_START_ADDR_SUB_LOW_MULTIREG_COUNT 12 // The lower 32bit of the start address. #define AXI_RT_START_ADDR_SUB_LOW_0_REG_OFFSET 0x24 @@ -182,600 +166,456 @@ extern "C" { // The lower 32bit of the start address. #define AXI_RT_START_ADDR_SUB_LOW_11_REG_OFFSET 0x50 -// The lower 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_LOW_12_REG_OFFSET 0x54 - -// The lower 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_LOW_13_REG_OFFSET 0x58 - -// The lower 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_LOW_14_REG_OFFSET 0x5c - -// The lower 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_LOW_15_REG_OFFSET 0x60 - // The higher 32bit of the start address. (common parameters) #define AXI_RT_START_ADDR_SUB_HIGH_WRITE_BUDGET_FIELD_WIDTH 32 #define AXI_RT_START_ADDR_SUB_HIGH_WRITE_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_START_ADDR_SUB_HIGH_MULTIREG_COUNT 16 - -// The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_0_REG_OFFSET 0x64 - -// The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_1_REG_OFFSET 0x68 +#define AXI_RT_START_ADDR_SUB_HIGH_MULTIREG_COUNT 12 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_2_REG_OFFSET 0x6c +#define AXI_RT_START_ADDR_SUB_HIGH_0_REG_OFFSET 0x54 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_3_REG_OFFSET 0x70 +#define AXI_RT_START_ADDR_SUB_HIGH_1_REG_OFFSET 0x58 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_4_REG_OFFSET 0x74 +#define AXI_RT_START_ADDR_SUB_HIGH_2_REG_OFFSET 0x5c // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_5_REG_OFFSET 0x78 +#define AXI_RT_START_ADDR_SUB_HIGH_3_REG_OFFSET 0x60 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_6_REG_OFFSET 0x7c +#define AXI_RT_START_ADDR_SUB_HIGH_4_REG_OFFSET 0x64 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_7_REG_OFFSET 0x80 +#define AXI_RT_START_ADDR_SUB_HIGH_5_REG_OFFSET 0x68 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_8_REG_OFFSET 0x84 +#define AXI_RT_START_ADDR_SUB_HIGH_6_REG_OFFSET 0x6c // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_9_REG_OFFSET 0x88 +#define AXI_RT_START_ADDR_SUB_HIGH_7_REG_OFFSET 0x70 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_10_REG_OFFSET 0x8c +#define AXI_RT_START_ADDR_SUB_HIGH_8_REG_OFFSET 0x74 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_11_REG_OFFSET 0x90 +#define AXI_RT_START_ADDR_SUB_HIGH_9_REG_OFFSET 0x78 // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_12_REG_OFFSET 0x94 +#define AXI_RT_START_ADDR_SUB_HIGH_10_REG_OFFSET 0x7c // The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_13_REG_OFFSET 0x98 - -// The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_14_REG_OFFSET 0x9c - -// The higher 32bit of the start address. -#define AXI_RT_START_ADDR_SUB_HIGH_15_REG_OFFSET 0xa0 +#define AXI_RT_START_ADDR_SUB_HIGH_11_REG_OFFSET 0x80 // The lower 32bit of the end address. (common parameters) #define AXI_RT_END_ADDR_SUB_LOW_WRITE_BUDGET_FIELD_WIDTH 32 #define AXI_RT_END_ADDR_SUB_LOW_WRITE_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_END_ADDR_SUB_LOW_MULTIREG_COUNT 16 - -// The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_0_REG_OFFSET 0xa4 - -// The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_1_REG_OFFSET 0xa8 - -// The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_2_REG_OFFSET 0xac - -// The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_3_REG_OFFSET 0xb0 +#define AXI_RT_END_ADDR_SUB_LOW_MULTIREG_COUNT 12 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_4_REG_OFFSET 0xb4 +#define AXI_RT_END_ADDR_SUB_LOW_0_REG_OFFSET 0x84 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_5_REG_OFFSET 0xb8 +#define AXI_RT_END_ADDR_SUB_LOW_1_REG_OFFSET 0x88 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_6_REG_OFFSET 0xbc +#define AXI_RT_END_ADDR_SUB_LOW_2_REG_OFFSET 0x8c // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_7_REG_OFFSET 0xc0 +#define AXI_RT_END_ADDR_SUB_LOW_3_REG_OFFSET 0x90 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_8_REG_OFFSET 0xc4 +#define AXI_RT_END_ADDR_SUB_LOW_4_REG_OFFSET 0x94 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_9_REG_OFFSET 0xc8 +#define AXI_RT_END_ADDR_SUB_LOW_5_REG_OFFSET 0x98 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_10_REG_OFFSET 0xcc +#define AXI_RT_END_ADDR_SUB_LOW_6_REG_OFFSET 0x9c // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_11_REG_OFFSET 0xd0 +#define AXI_RT_END_ADDR_SUB_LOW_7_REG_OFFSET 0xa0 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_12_REG_OFFSET 0xd4 +#define AXI_RT_END_ADDR_SUB_LOW_8_REG_OFFSET 0xa4 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_13_REG_OFFSET 0xd8 +#define AXI_RT_END_ADDR_SUB_LOW_9_REG_OFFSET 0xa8 // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_14_REG_OFFSET 0xdc +#define AXI_RT_END_ADDR_SUB_LOW_10_REG_OFFSET 0xac // The lower 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_LOW_15_REG_OFFSET 0xe0 +#define AXI_RT_END_ADDR_SUB_LOW_11_REG_OFFSET 0xb0 // The higher 32bit of the end address. (common parameters) #define AXI_RT_END_ADDR_SUB_HIGH_WRITE_BUDGET_FIELD_WIDTH 32 #define AXI_RT_END_ADDR_SUB_HIGH_WRITE_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_END_ADDR_SUB_HIGH_MULTIREG_COUNT 16 +#define AXI_RT_END_ADDR_SUB_HIGH_MULTIREG_COUNT 12 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_0_REG_OFFSET 0xe4 +#define AXI_RT_END_ADDR_SUB_HIGH_0_REG_OFFSET 0xb4 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_1_REG_OFFSET 0xe8 +#define AXI_RT_END_ADDR_SUB_HIGH_1_REG_OFFSET 0xb8 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_2_REG_OFFSET 0xec +#define AXI_RT_END_ADDR_SUB_HIGH_2_REG_OFFSET 0xbc // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_3_REG_OFFSET 0xf0 +#define AXI_RT_END_ADDR_SUB_HIGH_3_REG_OFFSET 0xc0 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_4_REG_OFFSET 0xf4 +#define AXI_RT_END_ADDR_SUB_HIGH_4_REG_OFFSET 0xc4 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_5_REG_OFFSET 0xf8 +#define AXI_RT_END_ADDR_SUB_HIGH_5_REG_OFFSET 0xc8 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_6_REG_OFFSET 0xfc +#define AXI_RT_END_ADDR_SUB_HIGH_6_REG_OFFSET 0xcc // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_7_REG_OFFSET 0x100 +#define AXI_RT_END_ADDR_SUB_HIGH_7_REG_OFFSET 0xd0 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_8_REG_OFFSET 0x104 +#define AXI_RT_END_ADDR_SUB_HIGH_8_REG_OFFSET 0xd4 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_9_REG_OFFSET 0x108 +#define AXI_RT_END_ADDR_SUB_HIGH_9_REG_OFFSET 0xd8 // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_10_REG_OFFSET 0x10c +#define AXI_RT_END_ADDR_SUB_HIGH_10_REG_OFFSET 0xdc // The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_11_REG_OFFSET 0x110 - -// The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_12_REG_OFFSET 0x114 - -// The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_13_REG_OFFSET 0x118 - -// The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_14_REG_OFFSET 0x11c - -// The higher 32bit of the end address. -#define AXI_RT_END_ADDR_SUB_HIGH_15_REG_OFFSET 0x120 +#define AXI_RT_END_ADDR_SUB_HIGH_11_REG_OFFSET 0xe0 // The budget for writes. (common parameters) #define AXI_RT_WRITE_BUDGET_WRITE_BUDGET_FIELD_WIDTH 32 #define AXI_RT_WRITE_BUDGET_WRITE_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_BUDGET_MULTIREG_COUNT 16 - -// The budget for writes. -#define AXI_RT_WRITE_BUDGET_0_REG_OFFSET 0x124 - -// The budget for writes. -#define AXI_RT_WRITE_BUDGET_1_REG_OFFSET 0x128 +#define AXI_RT_WRITE_BUDGET_MULTIREG_COUNT 12 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_2_REG_OFFSET 0x12c +#define AXI_RT_WRITE_BUDGET_0_REG_OFFSET 0xe4 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_3_REG_OFFSET 0x130 +#define AXI_RT_WRITE_BUDGET_1_REG_OFFSET 0xe8 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_4_REG_OFFSET 0x134 +#define AXI_RT_WRITE_BUDGET_2_REG_OFFSET 0xec // The budget for writes. -#define AXI_RT_WRITE_BUDGET_5_REG_OFFSET 0x138 +#define AXI_RT_WRITE_BUDGET_3_REG_OFFSET 0xf0 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_6_REG_OFFSET 0x13c +#define AXI_RT_WRITE_BUDGET_4_REG_OFFSET 0xf4 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_7_REG_OFFSET 0x140 +#define AXI_RT_WRITE_BUDGET_5_REG_OFFSET 0xf8 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_8_REG_OFFSET 0x144 +#define AXI_RT_WRITE_BUDGET_6_REG_OFFSET 0xfc // The budget for writes. -#define AXI_RT_WRITE_BUDGET_9_REG_OFFSET 0x148 +#define AXI_RT_WRITE_BUDGET_7_REG_OFFSET 0x100 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_10_REG_OFFSET 0x14c +#define AXI_RT_WRITE_BUDGET_8_REG_OFFSET 0x104 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_11_REG_OFFSET 0x150 +#define AXI_RT_WRITE_BUDGET_9_REG_OFFSET 0x108 // The budget for writes. -#define AXI_RT_WRITE_BUDGET_12_REG_OFFSET 0x154 +#define AXI_RT_WRITE_BUDGET_10_REG_OFFSET 0x10c // The budget for writes. -#define AXI_RT_WRITE_BUDGET_13_REG_OFFSET 0x158 - -// The budget for writes. -#define AXI_RT_WRITE_BUDGET_14_REG_OFFSET 0x15c - -// The budget for writes. -#define AXI_RT_WRITE_BUDGET_15_REG_OFFSET 0x160 +#define AXI_RT_WRITE_BUDGET_11_REG_OFFSET 0x110 // The budget for reads. (common parameters) #define AXI_RT_READ_BUDGET_READ_BUDGET_FIELD_WIDTH 32 #define AXI_RT_READ_BUDGET_READ_BUDGET_FIELDS_PER_REG 1 -#define AXI_RT_READ_BUDGET_MULTIREG_COUNT 16 - -// The budget for reads. -#define AXI_RT_READ_BUDGET_0_REG_OFFSET 0x164 - -// The budget for reads. -#define AXI_RT_READ_BUDGET_1_REG_OFFSET 0x168 - -// The budget for reads. -#define AXI_RT_READ_BUDGET_2_REG_OFFSET 0x16c - -// The budget for reads. -#define AXI_RT_READ_BUDGET_3_REG_OFFSET 0x170 +#define AXI_RT_READ_BUDGET_MULTIREG_COUNT 12 // The budget for reads. -#define AXI_RT_READ_BUDGET_4_REG_OFFSET 0x174 +#define AXI_RT_READ_BUDGET_0_REG_OFFSET 0x114 // The budget for reads. -#define AXI_RT_READ_BUDGET_5_REG_OFFSET 0x178 +#define AXI_RT_READ_BUDGET_1_REG_OFFSET 0x118 // The budget for reads. -#define AXI_RT_READ_BUDGET_6_REG_OFFSET 0x17c +#define AXI_RT_READ_BUDGET_2_REG_OFFSET 0x11c // The budget for reads. -#define AXI_RT_READ_BUDGET_7_REG_OFFSET 0x180 +#define AXI_RT_READ_BUDGET_3_REG_OFFSET 0x120 // The budget for reads. -#define AXI_RT_READ_BUDGET_8_REG_OFFSET 0x184 +#define AXI_RT_READ_BUDGET_4_REG_OFFSET 0x124 // The budget for reads. -#define AXI_RT_READ_BUDGET_9_REG_OFFSET 0x188 +#define AXI_RT_READ_BUDGET_5_REG_OFFSET 0x128 // The budget for reads. -#define AXI_RT_READ_BUDGET_10_REG_OFFSET 0x18c +#define AXI_RT_READ_BUDGET_6_REG_OFFSET 0x12c // The budget for reads. -#define AXI_RT_READ_BUDGET_11_REG_OFFSET 0x190 +#define AXI_RT_READ_BUDGET_7_REG_OFFSET 0x130 // The budget for reads. -#define AXI_RT_READ_BUDGET_12_REG_OFFSET 0x194 +#define AXI_RT_READ_BUDGET_8_REG_OFFSET 0x134 // The budget for reads. -#define AXI_RT_READ_BUDGET_13_REG_OFFSET 0x198 +#define AXI_RT_READ_BUDGET_9_REG_OFFSET 0x138 // The budget for reads. -#define AXI_RT_READ_BUDGET_14_REG_OFFSET 0x19c +#define AXI_RT_READ_BUDGET_10_REG_OFFSET 0x13c // The budget for reads. -#define AXI_RT_READ_BUDGET_15_REG_OFFSET 0x1a0 +#define AXI_RT_READ_BUDGET_11_REG_OFFSET 0x140 // The period for writes. (common parameters) #define AXI_RT_WRITE_PERIOD_WRITE_PERIOD_FIELD_WIDTH 32 #define AXI_RT_WRITE_PERIOD_WRITE_PERIOD_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_PERIOD_MULTIREG_COUNT 16 +#define AXI_RT_WRITE_PERIOD_MULTIREG_COUNT 12 // The period for writes. -#define AXI_RT_WRITE_PERIOD_0_REG_OFFSET 0x1a4 +#define AXI_RT_WRITE_PERIOD_0_REG_OFFSET 0x144 // The period for writes. -#define AXI_RT_WRITE_PERIOD_1_REG_OFFSET 0x1a8 +#define AXI_RT_WRITE_PERIOD_1_REG_OFFSET 0x148 // The period for writes. -#define AXI_RT_WRITE_PERIOD_2_REG_OFFSET 0x1ac +#define AXI_RT_WRITE_PERIOD_2_REG_OFFSET 0x14c // The period for writes. -#define AXI_RT_WRITE_PERIOD_3_REG_OFFSET 0x1b0 +#define AXI_RT_WRITE_PERIOD_3_REG_OFFSET 0x150 // The period for writes. -#define AXI_RT_WRITE_PERIOD_4_REG_OFFSET 0x1b4 +#define AXI_RT_WRITE_PERIOD_4_REG_OFFSET 0x154 // The period for writes. -#define AXI_RT_WRITE_PERIOD_5_REG_OFFSET 0x1b8 +#define AXI_RT_WRITE_PERIOD_5_REG_OFFSET 0x158 // The period for writes. -#define AXI_RT_WRITE_PERIOD_6_REG_OFFSET 0x1bc +#define AXI_RT_WRITE_PERIOD_6_REG_OFFSET 0x15c // The period for writes. -#define AXI_RT_WRITE_PERIOD_7_REG_OFFSET 0x1c0 +#define AXI_RT_WRITE_PERIOD_7_REG_OFFSET 0x160 // The period for writes. -#define AXI_RT_WRITE_PERIOD_8_REG_OFFSET 0x1c4 +#define AXI_RT_WRITE_PERIOD_8_REG_OFFSET 0x164 // The period for writes. -#define AXI_RT_WRITE_PERIOD_9_REG_OFFSET 0x1c8 +#define AXI_RT_WRITE_PERIOD_9_REG_OFFSET 0x168 // The period for writes. -#define AXI_RT_WRITE_PERIOD_10_REG_OFFSET 0x1cc +#define AXI_RT_WRITE_PERIOD_10_REG_OFFSET 0x16c // The period for writes. -#define AXI_RT_WRITE_PERIOD_11_REG_OFFSET 0x1d0 - -// The period for writes. -#define AXI_RT_WRITE_PERIOD_12_REG_OFFSET 0x1d4 - -// The period for writes. -#define AXI_RT_WRITE_PERIOD_13_REG_OFFSET 0x1d8 - -// The period for writes. -#define AXI_RT_WRITE_PERIOD_14_REG_OFFSET 0x1dc - -// The period for writes. -#define AXI_RT_WRITE_PERIOD_15_REG_OFFSET 0x1e0 +#define AXI_RT_WRITE_PERIOD_11_REG_OFFSET 0x170 // The period for reads. (common parameters) #define AXI_RT_READ_PERIOD_READ_PERIOD_FIELD_WIDTH 32 #define AXI_RT_READ_PERIOD_READ_PERIOD_FIELDS_PER_REG 1 -#define AXI_RT_READ_PERIOD_MULTIREG_COUNT 16 - -// The period for reads. -#define AXI_RT_READ_PERIOD_0_REG_OFFSET 0x1e4 - -// The period for reads. -#define AXI_RT_READ_PERIOD_1_REG_OFFSET 0x1e8 +#define AXI_RT_READ_PERIOD_MULTIREG_COUNT 12 // The period for reads. -#define AXI_RT_READ_PERIOD_2_REG_OFFSET 0x1ec +#define AXI_RT_READ_PERIOD_0_REG_OFFSET 0x174 // The period for reads. -#define AXI_RT_READ_PERIOD_3_REG_OFFSET 0x1f0 +#define AXI_RT_READ_PERIOD_1_REG_OFFSET 0x178 // The period for reads. -#define AXI_RT_READ_PERIOD_4_REG_OFFSET 0x1f4 +#define AXI_RT_READ_PERIOD_2_REG_OFFSET 0x17c // The period for reads. -#define AXI_RT_READ_PERIOD_5_REG_OFFSET 0x1f8 +#define AXI_RT_READ_PERIOD_3_REG_OFFSET 0x180 // The period for reads. -#define AXI_RT_READ_PERIOD_6_REG_OFFSET 0x1fc +#define AXI_RT_READ_PERIOD_4_REG_OFFSET 0x184 // The period for reads. -#define AXI_RT_READ_PERIOD_7_REG_OFFSET 0x200 +#define AXI_RT_READ_PERIOD_5_REG_OFFSET 0x188 // The period for reads. -#define AXI_RT_READ_PERIOD_8_REG_OFFSET 0x204 +#define AXI_RT_READ_PERIOD_6_REG_OFFSET 0x18c // The period for reads. -#define AXI_RT_READ_PERIOD_9_REG_OFFSET 0x208 +#define AXI_RT_READ_PERIOD_7_REG_OFFSET 0x190 // The period for reads. -#define AXI_RT_READ_PERIOD_10_REG_OFFSET 0x20c +#define AXI_RT_READ_PERIOD_8_REG_OFFSET 0x194 // The period for reads. -#define AXI_RT_READ_PERIOD_11_REG_OFFSET 0x210 +#define AXI_RT_READ_PERIOD_9_REG_OFFSET 0x198 // The period for reads. -#define AXI_RT_READ_PERIOD_12_REG_OFFSET 0x214 +#define AXI_RT_READ_PERIOD_10_REG_OFFSET 0x19c // The period for reads. -#define AXI_RT_READ_PERIOD_13_REG_OFFSET 0x218 - -// The period for reads. -#define AXI_RT_READ_PERIOD_14_REG_OFFSET 0x21c - -// The period for reads. -#define AXI_RT_READ_PERIOD_15_REG_OFFSET 0x220 +#define AXI_RT_READ_PERIOD_11_REG_OFFSET 0x1a0 // The budget left for writes. (common parameters) #define AXI_RT_WRITE_BUDGET_LEFT_WRITE_BUDGET_LEFT_FIELD_WIDTH 32 #define AXI_RT_WRITE_BUDGET_LEFT_WRITE_BUDGET_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_BUDGET_LEFT_MULTIREG_COUNT 16 - -// The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_0_REG_OFFSET 0x224 - -// The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_1_REG_OFFSET 0x228 - -// The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_2_REG_OFFSET 0x22c - -// The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_3_REG_OFFSET 0x230 +#define AXI_RT_WRITE_BUDGET_LEFT_MULTIREG_COUNT 12 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_4_REG_OFFSET 0x234 +#define AXI_RT_WRITE_BUDGET_LEFT_0_REG_OFFSET 0x1a4 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_5_REG_OFFSET 0x238 +#define AXI_RT_WRITE_BUDGET_LEFT_1_REG_OFFSET 0x1a8 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_6_REG_OFFSET 0x23c +#define AXI_RT_WRITE_BUDGET_LEFT_2_REG_OFFSET 0x1ac // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_7_REG_OFFSET 0x240 +#define AXI_RT_WRITE_BUDGET_LEFT_3_REG_OFFSET 0x1b0 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_8_REG_OFFSET 0x244 +#define AXI_RT_WRITE_BUDGET_LEFT_4_REG_OFFSET 0x1b4 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_9_REG_OFFSET 0x248 +#define AXI_RT_WRITE_BUDGET_LEFT_5_REG_OFFSET 0x1b8 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_10_REG_OFFSET 0x24c +#define AXI_RT_WRITE_BUDGET_LEFT_6_REG_OFFSET 0x1bc // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_11_REG_OFFSET 0x250 +#define AXI_RT_WRITE_BUDGET_LEFT_7_REG_OFFSET 0x1c0 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_12_REG_OFFSET 0x254 +#define AXI_RT_WRITE_BUDGET_LEFT_8_REG_OFFSET 0x1c4 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_13_REG_OFFSET 0x258 +#define AXI_RT_WRITE_BUDGET_LEFT_9_REG_OFFSET 0x1c8 // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_14_REG_OFFSET 0x25c +#define AXI_RT_WRITE_BUDGET_LEFT_10_REG_OFFSET 0x1cc // The budget left for writes. -#define AXI_RT_WRITE_BUDGET_LEFT_15_REG_OFFSET 0x260 +#define AXI_RT_WRITE_BUDGET_LEFT_11_REG_OFFSET 0x1d0 // The budget left for reads. (common parameters) #define AXI_RT_READ_BUDGET_LEFT_READ_BUDGET_LEFT_FIELD_WIDTH 32 #define AXI_RT_READ_BUDGET_LEFT_READ_BUDGET_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_READ_BUDGET_LEFT_MULTIREG_COUNT 16 +#define AXI_RT_READ_BUDGET_LEFT_MULTIREG_COUNT 12 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_0_REG_OFFSET 0x264 +#define AXI_RT_READ_BUDGET_LEFT_0_REG_OFFSET 0x1d4 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_1_REG_OFFSET 0x268 +#define AXI_RT_READ_BUDGET_LEFT_1_REG_OFFSET 0x1d8 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_2_REG_OFFSET 0x26c +#define AXI_RT_READ_BUDGET_LEFT_2_REG_OFFSET 0x1dc // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_3_REG_OFFSET 0x270 +#define AXI_RT_READ_BUDGET_LEFT_3_REG_OFFSET 0x1e0 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_4_REG_OFFSET 0x274 +#define AXI_RT_READ_BUDGET_LEFT_4_REG_OFFSET 0x1e4 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_5_REG_OFFSET 0x278 +#define AXI_RT_READ_BUDGET_LEFT_5_REG_OFFSET 0x1e8 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_6_REG_OFFSET 0x27c +#define AXI_RT_READ_BUDGET_LEFT_6_REG_OFFSET 0x1ec // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_7_REG_OFFSET 0x280 +#define AXI_RT_READ_BUDGET_LEFT_7_REG_OFFSET 0x1f0 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_8_REG_OFFSET 0x284 +#define AXI_RT_READ_BUDGET_LEFT_8_REG_OFFSET 0x1f4 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_9_REG_OFFSET 0x288 +#define AXI_RT_READ_BUDGET_LEFT_9_REG_OFFSET 0x1f8 // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_10_REG_OFFSET 0x28c +#define AXI_RT_READ_BUDGET_LEFT_10_REG_OFFSET 0x1fc // The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_11_REG_OFFSET 0x290 - -// The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_12_REG_OFFSET 0x294 - -// The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_13_REG_OFFSET 0x298 - -// The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_14_REG_OFFSET 0x29c - -// The budget left for reads. -#define AXI_RT_READ_BUDGET_LEFT_15_REG_OFFSET 0x2a0 +#define AXI_RT_READ_BUDGET_LEFT_11_REG_OFFSET 0x200 // The period left for writes. (common parameters) #define AXI_RT_WRITE_PERIOD_LEFT_WRITE_PERIOD_LEFT_FIELD_WIDTH 32 #define AXI_RT_WRITE_PERIOD_LEFT_WRITE_PERIOD_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_WRITE_PERIOD_LEFT_MULTIREG_COUNT 16 - -// The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_0_REG_OFFSET 0x2a4 - -// The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_1_REG_OFFSET 0x2a8 +#define AXI_RT_WRITE_PERIOD_LEFT_MULTIREG_COUNT 12 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_2_REG_OFFSET 0x2ac +#define AXI_RT_WRITE_PERIOD_LEFT_0_REG_OFFSET 0x204 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_3_REG_OFFSET 0x2b0 +#define AXI_RT_WRITE_PERIOD_LEFT_1_REG_OFFSET 0x208 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_4_REG_OFFSET 0x2b4 +#define AXI_RT_WRITE_PERIOD_LEFT_2_REG_OFFSET 0x20c // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_5_REG_OFFSET 0x2b8 +#define AXI_RT_WRITE_PERIOD_LEFT_3_REG_OFFSET 0x210 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_6_REG_OFFSET 0x2bc +#define AXI_RT_WRITE_PERIOD_LEFT_4_REG_OFFSET 0x214 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_7_REG_OFFSET 0x2c0 +#define AXI_RT_WRITE_PERIOD_LEFT_5_REG_OFFSET 0x218 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_8_REG_OFFSET 0x2c4 +#define AXI_RT_WRITE_PERIOD_LEFT_6_REG_OFFSET 0x21c // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_9_REG_OFFSET 0x2c8 +#define AXI_RT_WRITE_PERIOD_LEFT_7_REG_OFFSET 0x220 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_10_REG_OFFSET 0x2cc +#define AXI_RT_WRITE_PERIOD_LEFT_8_REG_OFFSET 0x224 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_11_REG_OFFSET 0x2d0 +#define AXI_RT_WRITE_PERIOD_LEFT_9_REG_OFFSET 0x228 // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_12_REG_OFFSET 0x2d4 +#define AXI_RT_WRITE_PERIOD_LEFT_10_REG_OFFSET 0x22c // The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_13_REG_OFFSET 0x2d8 - -// The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_14_REG_OFFSET 0x2dc - -// The period left for writes. -#define AXI_RT_WRITE_PERIOD_LEFT_15_REG_OFFSET 0x2e0 +#define AXI_RT_WRITE_PERIOD_LEFT_11_REG_OFFSET 0x230 // The period left for reads. (common parameters) #define AXI_RT_READ_PERIOD_LEFT_READ_PERIOD_LEFT_FIELD_WIDTH 32 #define AXI_RT_READ_PERIOD_LEFT_READ_PERIOD_LEFT_FIELDS_PER_REG 1 -#define AXI_RT_READ_PERIOD_LEFT_MULTIREG_COUNT 16 - -// The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_0_REG_OFFSET 0x2e4 - -// The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_1_REG_OFFSET 0x2e8 - -// The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_2_REG_OFFSET 0x2ec - -// The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_3_REG_OFFSET 0x2f0 +#define AXI_RT_READ_PERIOD_LEFT_MULTIREG_COUNT 12 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_4_REG_OFFSET 0x2f4 +#define AXI_RT_READ_PERIOD_LEFT_0_REG_OFFSET 0x234 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_5_REG_OFFSET 0x2f8 +#define AXI_RT_READ_PERIOD_LEFT_1_REG_OFFSET 0x238 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_6_REG_OFFSET 0x2fc +#define AXI_RT_READ_PERIOD_LEFT_2_REG_OFFSET 0x23c // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_7_REG_OFFSET 0x300 +#define AXI_RT_READ_PERIOD_LEFT_3_REG_OFFSET 0x240 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_8_REG_OFFSET 0x304 +#define AXI_RT_READ_PERIOD_LEFT_4_REG_OFFSET 0x244 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_9_REG_OFFSET 0x308 +#define AXI_RT_READ_PERIOD_LEFT_5_REG_OFFSET 0x248 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_10_REG_OFFSET 0x30c +#define AXI_RT_READ_PERIOD_LEFT_6_REG_OFFSET 0x24c // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_11_REG_OFFSET 0x310 +#define AXI_RT_READ_PERIOD_LEFT_7_REG_OFFSET 0x250 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_12_REG_OFFSET 0x314 +#define AXI_RT_READ_PERIOD_LEFT_8_REG_OFFSET 0x254 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_13_REG_OFFSET 0x318 +#define AXI_RT_READ_PERIOD_LEFT_9_REG_OFFSET 0x258 // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_14_REG_OFFSET 0x31c +#define AXI_RT_READ_PERIOD_LEFT_10_REG_OFFSET 0x25c // The period left for reads. -#define AXI_RT_READ_PERIOD_LEFT_15_REG_OFFSET 0x320 +#define AXI_RT_READ_PERIOD_LEFT_11_REG_OFFSET 0x260 // Is the interface requested to be isolated? (common parameters) #define AXI_RT_ISOLATE_ISOLATE_FIELD_WIDTH 1 @@ -783,15 +623,13 @@ extern "C" { #define AXI_RT_ISOLATE_MULTIREG_COUNT 1 // Is the interface requested to be isolated? -#define AXI_RT_ISOLATE_REG_OFFSET 0x324 +#define AXI_RT_ISOLATE_REG_OFFSET 0x264 #define AXI_RT_ISOLATE_ISOLATE_0_BIT 0 #define AXI_RT_ISOLATE_ISOLATE_1_BIT 1 #define AXI_RT_ISOLATE_ISOLATE_2_BIT 2 #define AXI_RT_ISOLATE_ISOLATE_3_BIT 3 #define AXI_RT_ISOLATE_ISOLATE_4_BIT 4 #define AXI_RT_ISOLATE_ISOLATE_5_BIT 5 -#define AXI_RT_ISOLATE_ISOLATE_6_BIT 6 -#define AXI_RT_ISOLATE_ISOLATE_7_BIT 7 // Is the interface isolated? (common parameters) #define AXI_RT_ISOLATED_ISOLATED_FIELD_WIDTH 1 @@ -799,48 +637,46 @@ extern "C" { #define AXI_RT_ISOLATED_MULTIREG_COUNT 1 // Is the interface isolated? -#define AXI_RT_ISOLATED_REG_OFFSET 0x328 +#define AXI_RT_ISOLATED_REG_OFFSET 0x268 #define AXI_RT_ISOLATED_ISOLATED_0_BIT 0 #define AXI_RT_ISOLATED_ISOLATED_1_BIT 1 #define AXI_RT_ISOLATED_ISOLATED_2_BIT 2 #define AXI_RT_ISOLATED_ISOLATED_3_BIT 3 #define AXI_RT_ISOLATED_ISOLATED_4_BIT 4 #define AXI_RT_ISOLATED_ISOLATED_5_BIT 5 -#define AXI_RT_ISOLATED_ISOLATED_6_BIT 6 -#define AXI_RT_ISOLATED_ISOLATED_7_BIT 7 // Value of the num_managers parameter. -#define AXI_RT_NUM_MANAGERS_REG_OFFSET 0x32c +#define AXI_RT_NUM_MANAGERS_REG_OFFSET 0x26c // Value of the addr_width parameter. -#define AXI_RT_ADDR_WIDTH_REG_OFFSET 0x330 +#define AXI_RT_ADDR_WIDTH_REG_OFFSET 0x270 // Value of the data_width parameter. -#define AXI_RT_DATA_WIDTH_REG_OFFSET 0x334 +#define AXI_RT_DATA_WIDTH_REG_OFFSET 0x274 // Value of the id_width parameter. -#define AXI_RT_ID_WIDTH_REG_OFFSET 0x338 +#define AXI_RT_ID_WIDTH_REG_OFFSET 0x278 // Value of the user_width parameter. -#define AXI_RT_USER_WIDTH_REG_OFFSET 0x33c +#define AXI_RT_USER_WIDTH_REG_OFFSET 0x27c // Value of the num_pending parameter. -#define AXI_RT_NUM_PENDING_REG_OFFSET 0x340 +#define AXI_RT_NUM_PENDING_REG_OFFSET 0x280 // Value of the w_buffer_depth parameter. -#define AXI_RT_W_BUFFER_DEPTH_REG_OFFSET 0x344 +#define AXI_RT_W_BUFFER_DEPTH_REG_OFFSET 0x284 // Value of the num_addr_regions parameter. -#define AXI_RT_NUM_ADDR_REGIONS_REG_OFFSET 0x348 +#define AXI_RT_NUM_ADDR_REGIONS_REG_OFFSET 0x288 // Value of the period_width parameter. -#define AXI_RT_PERIOD_WIDTH_REG_OFFSET 0x34c +#define AXI_RT_PERIOD_WIDTH_REG_OFFSET 0x28c // Value of the budget_width parameter. -#define AXI_RT_BUDGET_WIDTH_REG_OFFSET 0x350 +#define AXI_RT_BUDGET_WIDTH_REG_OFFSET 0x290 // Value of the max_num_managers parameter. -#define AXI_RT_MAX_NUM_MANAGERS_REG_OFFSET 0x354 +#define AXI_RT_MAX_NUM_MANAGERS_REG_OFFSET 0x294 #ifdef __cplusplus } // extern "C"