diff --git a/bender-xilinx.mk b/bender-xilinx.mk new file mode 100644 index 00000000..fcbf5b24 --- /dev/null +++ b/bender-xilinx.mk @@ -0,0 +1,25 @@ +# Copyright 2021 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Author: Cyril Koenig + +# bender targets +xilinx_targs += -t fpga + +# bender defines +xilinx_defs += -D PULP_FPGA_EMUL + +# Conditionally add GEN_{island} to bender define +define check_enable_island +ifeq ($($(1)),1) +xilinx_defs += $(1) +endif +endef + +$(eval $(call check_enable_island,GEN_PULP_CLUSTER)) +$(eval $(call check_enable_island,GEN_SAFETY_ISLAND)) +$(eval $(call check_enable_island,GEN_SPATZ_CLUSTER)) +$(eval $(call check_enable_island,GEN_OPEN_TITAN)) + +# note : bender targets are later modified in xilinx.mk diff --git a/carfield.mk b/carfield.mk index 0d56818b..d95211d4 100644 --- a/carfield.mk +++ b/carfield.mk @@ -9,10 +9,12 @@ CAR_ROOT ?= . CHS_ROOT ?= $(CAR_ROOT)/cheshire CAR_SW_DIR := $(CAR_ROOT)/sw +CAR_XIL_DIR := $(CAR_ROOT)/target/xilinx # Bender BENDER ?= bender QUESTA ?= questa-2022.3 +VIVADO ?= vitis-2020.2 vivado TBENCH ?= tb_carfield_soc BOOTMODE ?= 0 # default passive bootmode PRELMODE ?= 1 # default serial link preload @@ -43,6 +45,10 @@ CHS_IMAGE ?= # (the following includes are mandatory) include $(CAR_ROOT)/bender-common.mk include $(CAR_ROOT)/bender-synth.mk +include $(CAR_ROOT)/bender-xilinx.mk + +print_stuff: + echo $(xilinx_defs) # Setup Virtual Environment for python scripts (reggen) VENVDIR?=$(WORKDIR)/.venv @@ -235,6 +241,16 @@ SPYGLASS_DEFS += $(synth_defs) lint: $(MAKE) -C scripts lint bender_defs="$(SPYGLASS_DEFS)" bender_targs="$(SPYGLASS_TARGS)" > make.log +############# +# Emulation # +############# + +include $(CAR_XIL_DIR)/xilinx.mk + +######## +# Help # +######## + # Setup Autodocumentation of the Makefile HELP_TITLE="Carfield Open-Source RTL" HELP_DESCRIPTION="Hardware generation and simulation targets for Carfield" diff --git a/target/xilinx/Makefile b/target/xilinx/xilinx.mk similarity index 51% rename from target/xilinx/Makefile rename to target/xilinx/xilinx.mk index ad4ec973..e49c8c27 100644 --- a/target/xilinx/Makefile +++ b/target/xilinx/xilinx.mk @@ -6,19 +6,10 @@ # Christopher Reinwardt # Cyril Koenig -BENDER ?= bender - PROJECT ?= carfield - # Board in {genesys2, zcu102, vcu128} BOARD ?= vcu128 -ip-dir := xilinx - -# Derive from board -bender-targets := -t fpga -t $(BOARD) -t cv64a6_imafdcsclic_sv39 -t cva6 -t mchan -t spatz -t cv32e40p_use_ff_regfile -bender-defines := -D FEATURE_ICACHE_STAT -D PRIVATE_ICACHE -D HIERARCHY_ICACHE_32BIT -D CLUSTER_ALIAS -D PULP_FPGA_EMUL - -VIVADO ?= vitis-2020.2 vivado +ip-dir := $(CAR_XIL_DIR)/xilinx # Select board specific variables ifeq ($(BOARD),vcu128) @@ -38,28 +29,17 @@ ifeq ($(BOARD),zcu102) ips-names := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio endif -# Derive from ips -ips := $(addsuffix .xci ,$(basename $(ips-names))) -bender-targets := $(bender-targets) $(addprefix -t ,$(basename $(ips))) - -# Select islands -ifeq ($(GEN_PULP_CLUSTER), 1) -bender-defines += -D GEN_PULP_CLUSTER=1 -endif -ifeq ($(GEN_SAFETY_ISLAND), 1) -bender-defines += -D GEN_SAFETY_ISLAND=1 -endif -ifeq ($(GEN_SPATZ_CLUSTER), 1) -bender-defines += -D GEN_SPATZ_CLUSTER=1 -endif -ifeq ($(GEN_OPEN_TITAN), 1) -bender-defines += -D GEN_OPEN_TITAN=1 -endif +# Location of ip outputs +ips := $(addprefix $(CAR_XIL_DIR)/,$(addsuffix .xci ,$(basename $(ips-names)))) +# Derive bender args from enabled ips +xilinx_targs := $(xilinx_targs) $(addprefix -t ,$(basename $(ips))) -out := out +# Outputs +out := $(CAR_XIL_DIR)/out bit := $(out)/$(PROJECT)_top_xilinx.bit mcs := $(out)/$(PROJECT)_top_xilinx.mcs +# Vivado variables VIVADOENV ?= PROJECT=$(PROJECT) \ BOARD=$(BOARD) \ XILINX_PART=$(XILINX_PART) \ @@ -67,61 +47,56 @@ VIVADOENV ?= PROJECT=$(PROJECT) \ PORT=$(XILINX_PORT) \ HOST=$(XILINX_HOST) \ FPGA_PATH=$(FPGA_PATH) \ - BIT=$(BIT) - -# select IIS-internal tool commands if we run on IIS machines -ifneq (,$(wildcard /etc/iis.version)) - VIVADO ?= vitis-2020.2 vivado -else - VIVADO ?= vivado -endif - + BIT=$(bit) MODE ?= gui VIVADOFLAGS ?= -nojournal -mode $(MODE) -source scripts/prologue.tcl -all: $(bit) +car-xil-all: $(bit) # Generate mcs from bitstream $(mcs): $(bit) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ + cd $(CAR_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/write_cfgmem.tcl -tclargs $@ $^ -$(bit): $(ips) scripts/add_sources.tcl +# Compile bitstream +$(bit): $(ips) $(CAR_XIL_DIR)/scripts/add_sources.tcl @mkdir -p $(out) - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/run.tcl + cd $(CAR_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/run.tcl cp $(PROJECT).runs/impl_1/$(PROJECT)* ./$(out) +# Generate ips %.xci: + @echo $@ + @echo $(CAR_XIL_DIR) @echo "Generating IP $(basename $@)" - cd $(ip-dir)/$(basename $@) && $(MAKE) clean && $(VIVADOENV) VIVADO="$(VIVADO)" $(MAKE) - cp $(ip-dir)/$(basename $@)/$(basename $@).srcs/sources_1/ip/$(basename $@)/$@ $@ + IP_NAME=$(basename $(notdir $@)) ; cd $(ip-dir)/$$IP_NAME && $(MAKE) clean && $(VIVADOENV) VIVADO="$(VIVADO)" $(MAKE) + IP_NAME=$(basename $(notdir $@)) ; cp $(ip-dir)/$$IP_NAME/$$IP_NAME.srcs/sources_1/ip/$$IP_NAME/$$IP_NAME.xci $@ -gui: +car-xil-gui: @echo "Starting $(vivado) GUI" - @$(VIVADOENV) $(VIVADO) -nojournal -mode gui $(PROJECT).xpr & + cd $(CAR_XIL_DIR) && @$(VIVADOENV) $(VIVADO) -nojournal -mode gui $(PROJECT).xpr & -program: #$(bit) +car-xil-program: #$(bit) @echo "Programming board $(BOARD) ($(XILINX_PART))" - $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl + cd $(CAR_XIL_DIR) && $(VIVADOENV) $(VIVADO) $(VIVADOFLAGS) -source scripts/program.tcl -clean: - rm -rf *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim +car-xil-clean: + cd $(CAR_XIL_DIR) && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif *.xci *.xpr .Xil/ $(out) $(PROJECT).srcs $(PROJECT).cache $(PROJECT).hw $(PROJECT).ioplanning $(PROJECT).ip_user_files $(PROJECT).runs $(PROJECT).sim -# Clean only top and copy back the IPs output here -rebuild_top: - ${MAKE} clean - rm -f scripts/add_sources.tcl - find xilinx -wholename "**/*.srcs/**/*.xci" | xargs -n 1 -I {} cp {} . +# Re-compile only top and not ips +car-xil-rebuild-top: + ${MAKE} car-xil-clean + find xilinx -wholename "**/*.srcs/**/*.xci" | xargs -n 1 -I {} cp {} $(CAR_XIL_DIR) ${MAKE} $(bit) # Bender -scripts/add_sources.tcl: ../../Bender.yml - $(BENDER) script vivado $(bender-targets) $(bender-defines) > $@ +$(CAR_XIL_DIR)/scripts/add_sources.tcl: Bender.yml + $(BENDER) script vivado $(common_targs) $(xilinx_targs) $(common_defs) $(xilinx_defs) > $@ cp $@ $@.bak - ./scripts/overrides.sh $@ + $(CAR_XIL_DIR)/scripts/overrides.sh $@ echo "" >> $@ echo "#Put the overrides folder at the head of the include list" >> $@ echo "set_property include_dirs [ \\" >> $@ echo " concat \"\$$ROOT/target/xilinx/src/overrides/include \" [get_property include_dirs [current_fileset]] \\" >> $@ echo "] [current_fileset]" >> $@ -.PHONY: clean sim +.PHONY: car-xil-gui car-xil-program car-xil-clean car-xil-rebuild-top car-xil-all