From c17897643628a47fefcffeb39e8abeb27dc36226 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Thu, 16 Nov 2023 13:06:47 +0100 Subject: [PATCH] script: Adjust synopsys script to follow synopsys error syntax --- src/script_fmt/synopsys_tcl.tera | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/script_fmt/synopsys_tcl.tera b/src/script_fmt/synopsys_tcl.tera index 06ee4eb4..e001b17d 100644 --- a/src/script_fmt/synopsys_tcl.tera +++ b/src/script_fmt/synopsys_tcl.tera @@ -7,7 +7,7 @@ set search_path $search_path_initial {% for incdir in group.incdirs %}{# Add group's include directories #}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}" {% endfor %} -{% if abort_on_error %}if {[catch { {% endif %}{# Catch errors immediately +{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately #}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{# Analyze command for SystemVerilog or VHDL #} {% for define in group.defines %}{# Add group's defines #}{% if loop.first %}-define { \ @@ -18,7 +18,7 @@ set search_path $search_path_initial {% for file in group.files %}{# Add group's files #}{{ ' ' }}"{{ file | replace(from=root, to='$ROOT') }}" \ {% endfor %}] -{% if abort_on_error %}}]} {return 1}{% endif %} +{% if abort_on_error %}]} {return 1}{% endif %} {% endfor %} {% else %}{# compilation_mode == 'common' #}{# Common block for all files #}{% for file in all_verilog %}{# Loop over verilog files @@ -26,7 +26,7 @@ set search_path $search_path_initial {% for incdir in all_incdirs %}{# Add all include directories #}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}" {% endfor %} -{% if abort_on_error %}if {[catch { {% endif %}{# Catch errors immediately +{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately #}analyze -format sv \{# Analyze command for SystemVerilog #} {% for define in all_defines %}{# Add all defines } @@ -37,14 +37,14 @@ set search_path $search_path_initial {% endif %}{% endfor %}[list \ {% endif %}{{ ' ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{# Add all verilog files #} {% if loop.last %}] -{% if abort_on_error %}}]} {return 1}{% endif %} +{% if abort_on_error %}]} {return 1}{% endif %} {% endif %}{% endfor %} {% for file in all_vhdl %}{% if loop.first %}{# Loop over all VHDL files -#}{% if abort_on_error %}if {[catch { {% endif %}{# Catch errors immediately +#}{% if abort_on_error %}if {0 == [{% endif %}{# Catch errors immediately #}analyze -format vhdl \{# Analyze command for VHDL #} [list \ {% endif %}{{ ' ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{# Add all VHDL files #} {% if loop.last %}] -{% if abort_on_error %}}]} {return 1}{% endif %} +{% if abort_on_error %}]} {return 1}{% endif %} {% endif %}{% endfor %} {% endif %}set search_path $search_path_initial