diff --git a/src/cmd/script.rs b/src/cmd/script.rs
index 6a55cd12..5a3787de 100644
--- a/src/cmd/script.rs
+++ b/src/cmd/script.rs
@@ -320,17 +320,17 @@ pub fn run(sess: &Session, matches: &ArgMatches) -> Result<()> {
 
     // Generate the corresponding output.
     match format.as_str() {
-        "flist" => emit_template(sess, FLIST_TPL, matches, targets, srcs),
-        "vsim" => emit_template(sess, VSIM_TCL_TPL, matches, targets, srcs),
-        "vcs" => emit_template(sess, VCS_SH_TPL, matches, targets, srcs),
-        "verilator" => emit_template(sess, VERILATOR_SH_TPL, matches, targets, srcs),
-        "synopsys" => emit_template(sess, SYNOPSYS_TCL_TPL, matches, targets, srcs),
-        "formality" => emit_template(sess, FORMALITY_TCL_TPL, matches, targets, srcs),
-        "riviera" => emit_template(sess, RIVIERA_TCL_TPL, matches, targets, srcs),
-        "genus" => emit_template(sess, GENUS_TCL_TPL, matches, targets, srcs),
-        "vivado" => emit_template(sess, VIVADO_TCL_TPL, matches, targets, srcs),
-        "vivado-sim" => emit_template(sess, VIVADO_TCL_TPL, matches, targets, srcs),
-        "precision" => emit_template(sess, PRECISION_TCL_TPL, matches, targets, srcs),
+        "flist" => emit_template(sess, include_str!("../script_fmt/flist.tera"), matches, targets, srcs),
+        "vsim" => emit_template(sess, include_str!("../script_fmt/vsim_tcl.tera"), matches, targets, srcs),
+        "vcs" => emit_template(sess, include_str!("../script_fmt/vcs_sh.tera"), matches, targets, srcs),
+        "verilator" => emit_template(sess, include_str!("../script_fmt/verilator_sh.tera"), matches, targets, srcs),
+        "synopsys" => emit_template(sess, include_str!("../script_fmt/synopsys_tcl.tera"), matches, targets, srcs),
+        "formality" => emit_template(sess, include_str!("../script_fmt/formality_tcl.tera"), matches, targets, srcs),
+        "riviera" => emit_template(sess, include_str!("../script_fmt/riviera_tcl.tera"), matches, targets, srcs),
+        "genus" => emit_template(sess, include_str!("../script_fmt/genus_tcl.tera"), matches, targets, srcs),
+        "vivado" => emit_template(sess, include_str!("../script_fmt/vivado_tcl.tera"), matches, targets, srcs),
+        "vivado-sim" => emit_template(sess, include_str!("../script_fmt/vivado_tcl.tera"), matches, targets, srcs),
+        "precision" => emit_template(sess, include_str!("../script_fmt/precision_tcl.tera"), matches, targets, srcs),
         "template" => {
             let custom_tpl_path = Path::new(matches.get_one::<String>("template").unwrap());
             let custom_tpl_str =
@@ -598,528 +598,3 @@ struct TplSrcStruct {
     files: Vec<PathBuf>,
     file_type: String,
 }
-
-static FLIST_TPL: &str = "\
-{% for incdir in all_incdirs %}\
-    {% if relativize_path %}\
-        +incdir+{{ incdir | replace(from=root, to='') }}\n\
-    {% else %}\
-        +incdir+{{ incdir }}\n\
-    {% endif %}\
-{% endfor %}\
-{% for define in all_defines %}\
-    +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\n\
-{% endfor %}\
-{% for file in all_files %}\
-    {% if relativize_path %}\
-        {% if file is starting_with(root) %}\
-            {{ file | replace(from=root, to='') | trim_start_matches(pat='/') }}\n\
-        {% else %}\
-            {{ file }}\n\
-        {% endif %}\
-    {% else %}\
-        {{ file }}\n\
-    {% endif %}\
-{% endfor %}";
-
-static VSIM_TCL_TPL: &str = "\
-# {{ HEADER_AUTOGEN }}
-set ROOT \"{{ root }}\"
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\n\
-        {% if abort_on_error %}if {[catch { {% endif %}\
-        {% if group.file_type == 'verilog' %}vlog -incr -sv \\\n    \
-            {% for tmp_arg in vlog_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-            {% for define in group.defines %}\
-                +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \\\n    \
-            {% endfor %}\
-            {% for incdir in group.incdirs %}\
-                \"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}\" \\\n    \
-            {% endfor %}\
-        {% elif group.file_type == 'vhdl' %}vcom -2008 \\\n    \
-            {% for tmp_arg in vcom_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        {% for file in group.files %}\
-            \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% endif %}\
-        {% endfor %}\
-        {% if abort_on_error %}\\\n}]} {return 1}\
-        {% endif %}\n\
-    {% endfor %}\
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}\
-            {% if abort_on_error %}if {[catch { {% endif %}\
-            vlog -incr -sv \\\n    \
-            {% for tmp_arg in vlog_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-            {% for define in all_defines %}\
-                +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \\\n    \
-            {% endfor %}\
-            {% for incdir in all_incdirs %}\
-                \"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}\" \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% endif %}\
-        {% if loop.last %}\
-            {% if abort_on_error %} \\\n}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}\
-            {% if abort_on_error %}if {[catch { {% endif %}\
-            vcom -2008 \\\n    \
-            {% for tmp_arg in vcom_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% endif %}\
-        {% if loop.last %}\n\
-            {% if abort_on_error %}\n}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\
-{% endif %}";
-
-static VCS_SH_TPL: &str = "\
-#!/usr/bin/env bash
-# {{ HEADER_AUTOGEN }}
-ROOT=\"{{ root }}\"
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\n\
-        {% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \\\n    \
-            -full64 \\\n    \
-            {% for tmp_arg in vlog_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-            {% for define in group.defines %}\
-                +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \\\n    \
-            {% endfor %}\
-            {% for incdir in group.incdirs %}\
-                \"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}\" \\\n    \
-            {% endfor %}\
-        {% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \\\n    \
-            {% for tmp_arg in vcom_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        {% for file in group.files %}\
-            \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% endif %}\
-        {% endfor %}\n\
-    {% endfor %}
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}{{ vlogan_bin }} -sverilog \\\n    \
-            -full64 \\\n    \
-            {% for tmp_arg in vlog_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-            {% for define in all_defines %}\
-                +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \\\n    \
-            {% endfor %}\
-            {% for incdir in all_incdirs %}\
-                \"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}\" \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% endif %}\
-        {% if loop.last %}\n{% endif %}\
-    {% endfor %}\n\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}{{ vhdlan_bin }} \\\n    \
-            {% for tmp_arg in vcom_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% endif %}\
-        {% if loop.last %}\n{% endif %}\
-    {% endfor %}\n\
-{% endif %}";
-
-static VERILATOR_SH_TPL: &str = "\
-{% for group in srcs %}\
-    {% if group.file_type == 'verilog' %}\n\
-        {% for tmp_arg in vlog_args %}\
-            {{ tmp_arg }}\n\
-        {% endfor %}\
-        {% for define in group.defines %}\
-            +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\n\
-        {% endfor %}\
-        {% for incdir in group.incdirs %}\
-            +incdir+{{ incdir | replace(from=root, to='$ROOT') }}\n\
-        {% endfor %}\
-        {% for file in group.files %}\
-            {{ file }}\n\
-        {% endfor %}\
-    {% endif %}\
-{% endfor %}";
-
-static SYNOPSYS_TCL_TPL: &str = "\
-# {{HEADER_AUTOGEN}}
-set ROOT \"{{ root }}\"
-set search_path_initial $search_path
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\n\
-        set search_path $search_path_initial\n\
-        {% for incdir in group.incdirs %}\
-            lappend search_path \"$ROOT{{ incdir | replace(from=root, to='') }}\"\n\
-        {% endfor %}\n\
-        {% if abort_on_error %}if {[catch { {% endif %}analyze -format \
-        {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \\\n    \
-        {% for define in group.defines %}\
-            {% if loop.first %}-define { \\\n        {% endif %}\
-            {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-            {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-        {% endfor %}\
-        [list \\\n    \
-        {% for file in group.files %}\
-            {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% endfor %}\
-        ]\n\
-        {% if abort_on_error %}}]} {return 1}\
-        {% endif %}\n\
-    {% endfor %}\n\
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}\
-            set search_path $search_path_initial\n\
-            {% for incdir in all_incdirs %}\
-                lappend search_path \"$ROOT{{ incdir | replace(from=root, to='') }}\"\n\
-            {% endfor %}\n\
-            {% if abort_on_error %}if {[catch { {% endif %}analyze -format sv \\\n    \
-            {% for define in all_defines %}\
-                {% if loop.first %}-define { \\\n        {% endif %}\
-                {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-                {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-            {% endfor %}\
-            [list \\\n    \
-        {% endif %}\
-        {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% if loop.last %}\
-            ]\n\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}
-            {% if abort_on_error %}if {[catch { {% endif %}analyze -format vhdl \\\n    \
-            [list \\\n    \
-        {% endif %}\
-        {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% if loop.last %}\
-            ]\n\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-{% endif %}\
-set search_path $search_path_initial\n";
-
-static FORMALITY_TCL_TPL: &str = "\
-# {{HEADER_AUTOGEN}}
-set ROOT \"{{ root }}\"
-set search_path_initial $search_path
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\n\
-        set search_path $search_path_initial\n\
-        {% for incdir in group.incdirs %}\
-            lappend search_path \"$ROOT{{ incdir | replace(from=root, to='') }}\"\n\
-        {% endfor %}\n\
-        {% if abort_on_error %}if {[catch { {% endif %}\
-        {% if group.file_type == 'verilog' %}read_sverilog{% elif group.file_type == 'vhdl' %}read_vhdl{% endif %} -r \\\n    \
-        {% for define in group.defines %}\
-            {% if loop.first %}-define { \\\n        {% endif %}\
-            {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-            {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-        {% endfor %}\
-        [list \\\n    \
-        {% for file in group.files %}\
-            {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% endfor %}\
-        ]\n\
-        {% if abort_on_error %}}]} {return 1}\
-        {% endif %}\n\
-    {% endfor %}\n\
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}\
-            set search_path $search_path_initial\n\
-            {% for incdir in all_incdirs %}\
-                lappend search_path \"$ROOT{{ incdir | replace(from=root, to='') }}\"\n\
-            {% endfor %}\n\
-            {% if abort_on_error %}if {[catch { {% endif %}read_sverilog -r \\\n    \
-            {% for define in all_defines %}\
-                {% if loop.first %}-define { \\\n        {% endif %}\
-                {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-                {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-            {% endfor %}\
-            [list \\\n    \
-        {% endif %}\
-        {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% if loop.last %}\
-            ]\n\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}
-            {% if abort_on_error %}if {[catch { {% endif %}read_vhdl -r \\\n    \
-            [list \\\n    \
-        {% endif %}\
-        {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% if loop.last %}\
-            ]\n\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-{% endif %}\
-set search_path $search_path_initial\n";
-
-static GENUS_TCL_TPL: &str = "\
-# {{ HEADER_AUTOGEN }}
-if [ info exists search_path ] {{ '{{' }}
-  set search_path_initial $search_path
-{{ '}}' }}
-set ROOT = \"{{ root }}\"
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\n\
-        set search_path $search_path_initial\n\
-        {% for incdir in group.incdirs %}\
-            lappend search_path \"$ROOT{{ incdir | replace(from=root, to='') }}\"\n\
-        {% endfor %}\
-        set_db init_hdl_search_path $search_path\n\n\
-        {% if group.file_type == 'verilog' %}read_hdl -language sv \\\n    \
-        {% elif group.file_type == 'vhdl' %}read_hdl -language vhdl \\\n    \
-        {% endif %}\
-        {% for define in group.defines %}\
-            {% if loop.first %}-define { \\\n        {% endif %}\
-            {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-            {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-        {% endfor %}\
-        [list \\\n    \
-        {% for file in group.files %}\
-            {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% endfor %}\
-        ]\n\
-    {% endfor %}
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}\
-            set search_path $search_path_initial\n\
-            {% for incdir in all_incdirs %}\
-                lappend search_path \"$ROOT{{ incdir | replace(from=root, to='') }}\"\n\
-            {% endfor %}\n\
-            set_db init_hdl_search_path $search_path\n\n\
-            {% if abort_on_error %}if {[catch { {% endif %}read_hdl -language sv \\\n    \
-            {% for define in all_defines %}\
-                {% if loop.first %}-define { \\\n        {% endif %}\
-                {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-                {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-            {% endfor %}\
-            [list \\\n    \
-        {% endif %}\
-        {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% if loop.last %}\
-            ]\n\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}
-            {% if abort_on_error %}if {[catch { {% endif %}read_hdl -language vhdl \\\n    \
-            [list \\\n    \
-        {% endif %}\
-        {{ '    ' }}\"{{ file | replace(from=root, to='$ROOT') }}\" \\\n    \
-        {% if loop.last %}\
-            ]\n\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-{% endif %}\
-set search_path $search_path_initial\n";
-
-static VIVADO_TCL_TPL: &str = "\
-# {{ HEADER_AUTOGEN }}
-set ROOT \"{{ root }}\"
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\
-        add_files -norecurse -fileset [current_fileset] [list \\\n    \
-        {% for file in group.files %}\
-            {{ file | replace(from=root, to='$ROOT') }} \\\n{% if not loop.last %}    {% endif %}\
-        {% endfor %}\
-        ]\n\
-    {% endfor %}\
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_files %}\
-        {% if loop.first %}\
-            add_files -norecurse -fileset [current_fileset] [list \\\n    \
-        {% endif %}\
-        {{ file | replace(from=root, to='$ROOT') }} \\\n{% if not loop.last %}    {% endif %}\
-        {% if loop.last %}\
-            ]\n\
-        {% endif %}\
-    {% endfor %}\
-{% endif %}\
-{% for arg in vivado_filesets %}\
-    {% for incdir in all_incdirs %}\
-        {% if loop.first %}\nset_property include_dirs [list \\\n    {% endif %}\
-        {{incdir | replace(from=root, to='$ROOT') }}\
-        {%if loop.last %} \\\n] [current_fileset{{ arg }}]\n{% else %} \\\n    {% endif %}\
-    {% endfor %}\
-{% endfor %}\
-{% for arg in vivado_filesets %}\
-    {% for define in all_defines %}\
-        {% if loop.first %}\nset_property verilog_define [list \\\n    {% endif %}\
-        {{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-        {% if loop.last %} \\\n] [current_fileset{{ arg }}]\n{% else %} \\\n    {% endif %}\
-    {% endfor %}\
-{% endfor %}";
-
-static RIVIERA_TCL_TPL: &str = "\
-# {{ HEADER_AUTOGEN }}
-set ROOT \"{{ root }}\"
-vlib work
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\
-        {% if abort_on_error %}if {[catch { {% endif %}\
-        {% if group.file_type == 'verilog' %}vlog -sv \\\n    \
-            {% for tmp_arg in vlog_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-            {% for define in group.defines %}\
-                +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \\\n    \
-            {% endfor %}\
-            {% for incdir in group.incdirs %}\
-                \"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}\" \\\n    \
-            {% endfor %}\
-        {% elif group.file_type == 'vhdl' %}vcom -2008 \\\n    \
-            {% for tmp_arg in vcom_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        {% for file in group.files %}\
-            \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% else %}\\\n{% endif %}\
-        {% endfor %}\
-        {% if abort_on_error %}}]} {return 1}\
-        {% endif %}\n\n\
-    {% endfor %}
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}\
-            {% if abort_on_error %}if {[catch { {% endif %}\
-            vlog -sv \\\n    \
-            {% for tmp_arg in vlog_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-            {% for define in all_defines %}\
-                +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \\\n    \
-            {% endfor %}\
-            {% for incdir in all_incdirs %}\
-                \"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}\" \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% else %}\\\n{% endif %}\
-        {% if loop.last %}\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\n\
-        {% endif %}\
-    {% endfor %}\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}\
-            {% if abort_on_error %}if {[catch { {% endif %}\
-            vcom -2008 \\\n    \
-            {% for tmp_arg in vcom_args %}\
-                {{ tmp_arg }} \\\n    \
-            {% endfor %}\
-        {% endif %}\
-        \"{{ file | replace(from=root, to='$ROOT') }}\" {% if not loop.last %}\\\n    {% else %}\\\n{% endif %}\
-        {% if loop.last %}\
-            {% if abort_on_error %}}]} {return 1}\
-            {% endif %}\n\n\
-        {% endif %}\
-    {% endfor %}\
-{% endif %}";
-
-static PRECISION_TCL_TPL: &str = "\
-# {{ HEADER_AUTOGEN }}
-# Precision does not take relative paths into account when specifying include dirs.
-# Define the common ROOT anyway if needed for patching file paths.
-set ROOT {{ root }}
-set_input_dir $ROOT
-setup_design -search_path $ROOT
-{% for define in all_defines %}\
-    {% if loop.first %}\
-    \n# Set globally all defines for the (S)Verilog sources.\n\
-    setup_design -defines { \\\n    {% endif %}\
-    +define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}\
-    {% if loop.last %}\n\n{% else %} \\\n    {% endif %}\
-{% endfor %}\
-{% if compilation_mode == 'separate' %}\
-    {% for group in srcs %}\
-        {% if abort_on_error %}if {[catch { {% endif %}\
-        add_input_file \\\n    \
-        {% if group.file_type == 'verilog' %}\
-            -format SystemVerilog2012 \\\n    \
-            {% for incdir in group.incdirs %}\
-                {% if loop.first %}-search_path { \\\n        {% endif %}\
-                    {{ incdir }}\
-                {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-            {% endfor %}\
-        {% elif group.file_type == 'vhdl' %}\
-            -format vhdl_2008 \\\n    \
-        {% endif %}\
-        { \\\n        \
-        {% for file in group.files %}\
-            {{ file }}\
-            {% if loop.last %} \\\n    {% else %} \\\n        {% endif %}\
-        {% endfor %}\
-        } \\\n\
-        {% if abort_on_error %}}]} {return 1}\n\
-        {% endif %}\n\
-    {% endfor %}\n
-{% else %}{# compilation_mode == 'common' #}\
-    {% for file in all_verilog %}\
-        {% if loop.first %}\
-            {% if abort_on_error %}if {[catch { {% endif %}\
-            add_input_file \\\n    \
-            -format SystemVerilog2012 \\\n    \
-            {% for incdir in all_incdirs %}\
-                {% if loop.first %}-search_path { \\\n        {% endif %}\
-                    {{ incdir }}\
-                {% if loop.last %} \\\n    } \\\n    {% else %} \\\n        {% endif %}\
-            {% endfor %}\
-            { \\\n        \
-        {% endif %}\
-        {{ file }}\
-        {% if loop.last %} \\\n    {% else %} \\\n        {% endif %}\
-        {% if loop.last %}\
-            } \\\n\
-            {% if abort_on_error %}}]} {return 1}\n\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-    {% for file in all_vhdl %}\
-        {% if loop.first %}\
-            {% if abort_on_error %}if {[catch { {% endif %}\
-            add_input_file \\\n    \
-            -format vhdl_2008 \\\n    \
-        { \\\n        \
-        {% endif %}\
-        {{ file }}\
-        {% if loop.last %} \\\n    {% else %} \\\n        {% endif %}\
-        {% if loop.last %}\
-            } \\\n\
-            {% if abort_on_error %}}]} {return 1}\n\
-            {% endif %}\n\
-        {% endif %}\
-    {% endfor %}\n\
-{% endif %}";
diff --git a/src/script_fmt/flist.tera b/src/script_fmt/flist.tera
new file mode 100644
index 00000000..d8efcc04
--- /dev/null
+++ b/src/script_fmt/flist.tera
@@ -0,0 +1,21 @@
+{% for incdir in all_incdirs %}{#                                             loop over all include directories
+#}{% if relativize_path %}{#                                                  make path relative if necessary
+#}+incdir+{{ incdir | replace(from=root, to='') }}
+{% else %}{#
+#}+incdir+{{ incdir }}
+{% endif %}{#
+#}{% endfor %}{#
+#}{% for define in all_defines %}{#                                           loop over all defines
+#}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}
+{% endfor %}{#
+#}{% for file in all_files %}{#                                               loop over all files
+#}{% if relativize_path %}{#                                                  make path relative if necessary
+#}{% if file is starting_with(root) %}{#                                      keep path unless it starts with common root
+#}{{ file | replace(from=root, to='') | trim_start_matches(pat='/') }}
+{% else %}{#
+#}{{ file }}
+{% endif %}{#
+#}{% else %}{#
+#}{{ file }}
+{% endif %}{#
+#}{% endfor %}
diff --git a/src/script_fmt/formality_tcl.tera b/src/script_fmt/formality_tcl.tera
new file mode 100644
index 00000000..8786e5bb
--- /dev/null
+++ b/src/script_fmt/formality_tcl.tera
@@ -0,0 +1,37 @@
+# {{HEADER_AUTOGEN}}
+set ROOT "{{ root }}"
+set search_path_initial $search_path
+{% if compilation_mode == 'separate' %}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}read_sverilog{% elif group.file_type == 'vhdl' %}read_vhdl{% endif %} -r \
+    {% for define in group.defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}read_sverilog -r \
+    {% for define in all_defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}read_vhdl -r \
+    [list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial
diff --git a/src/script_fmt/genus_tcl.tera b/src/script_fmt/genus_tcl.tera
new file mode 100644
index 00000000..e46a504e
--- /dev/null
+++ b/src/script_fmt/genus_tcl.tera
@@ -0,0 +1,43 @@
+# {{ HEADER_AUTOGEN }}
+if [ info exists search_path ] {{ '{{' }}
+  set search_path_initial $search_path
+{{ '}}' }}
+set ROOT = "{{ root }}"
+{% if compilation_mode == 'separate' %}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}set_db init_hdl_search_path $search_path
+
+{% if group.file_type == 'verilog' %}read_hdl -language sv \
+    {% elif group.file_type == 'vhdl' %}read_hdl -language vhdl \
+    {% endif %}{% for define in group.defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}]
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+set_db init_hdl_search_path $search_path
+
+{% if abort_on_error %}if {[catch { {% endif %}read_hdl -language sv \
+    {% for define in all_defines %}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}
+{% if abort_on_error %}if {[catch { {% endif %}read_hdl -language vhdl \
+    [list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial
diff --git a/src/script_fmt/precision_tcl.tera b/src/script_fmt/precision_tcl.tera
new file mode 100644
index 00000000..5be2da6e
--- /dev/null
+++ b/src/script_fmt/precision_tcl.tera
@@ -0,0 +1,49 @@
+# {{ HEADER_AUTOGEN }}
+# Precision does not take relative paths into account when specifying include dirs.
+# Define the common ROOT anyway if needed for patching file paths.
+set ROOT {{ root }}
+set_input_dir $ROOT
+setup_design -search_path $ROOT
+{% for define in all_defines %}{% if loop.first %}
+# Set globally all defines for the (S)Verilog sources.
+setup_design -defines { \
+    {% endif %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %}
+
+{% else %} \
+    {% endif %}{% endfor %}{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
+    {% if group.file_type == 'verilog' %}-format SystemVerilog2012 \
+    {% for incdir in group.incdirs %}{% if loop.first %}-search_path { \
+        {% endif %}{{ incdir }}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}{% elif group.file_type == 'vhdl' %}-format vhdl_2008 \
+    {% endif %}{ \
+        {% for file in group.files %}{{ file }}{% if loop.last %} \
+    {% else %} \
+        {% endif %}{% endfor %}} \
+{% if abort_on_error %}}]} {return 1}
+{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
+    -format SystemVerilog2012 \
+    {% for incdir in all_incdirs %}{% if loop.first %}-search_path { \
+        {% endif %}{{ incdir }}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}{ \
+        {% endif %}{{ file }}{% if loop.last %} \
+    {% else %} \
+        {% endif %}{% if loop.last %}} \
+{% if abort_on_error %}}]} {return 1}
+{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}add_input_file \
+    -format vhdl_2008 \
+    { \
+        {% endif %}{{ file }}{% if loop.last %} \
+    {% else %} \
+        {% endif %}{% if loop.last %}} \
+{% if abort_on_error %}}]} {return 1}
+{% endif %}
+{% endif %}{% endfor %}
+{% endif %}
diff --git a/src/script_fmt/riviera_tcl.tera b/src/script_fmt/riviera_tcl.tera
new file mode 100644
index 00000000..9748af4c
--- /dev/null
+++ b/src/script_fmt/riviera_tcl.tera
@@ -0,0 +1,28 @@
+# {{ HEADER_AUTOGEN }}
+set ROOT "{{ root }}"
+vlib work
+{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}vlog -sv \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% elif group.file_type == 'vhdl' %}vcom -2008 \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% else %}\
+{% endif %}{% endfor %}{% if abort_on_error %}}]} {return 1}{% endif %}
+
+{% endfor %}{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% else %}\
+{% endif %}{% if loop.last %}{% if abort_on_error %}}]} {return 1}{% endif %}
+
+{% endif %}{% endfor %}{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vcom -2008 \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% else %}\
+{% endif %}{% if loop.last %}{% if abort_on_error %}}]} {return 1}{% endif %}
+
+{% endif %}{% endfor %}{% endif %}
diff --git a/src/script_fmt/synopsys_tcl.tera b/src/script_fmt/synopsys_tcl.tera
new file mode 100644
index 00000000..06ee4eb4
--- /dev/null
+++ b/src/script_fmt/synopsys_tcl.tera
@@ -0,0 +1,50 @@
+# {{HEADER_AUTOGEN}}
+set ROOT "{{ root }}"
+set search_path_initial $search_path
+{% if compilation_mode == 'separate' %}{#                                                                           Individual block for each source file group
+#}{% for group in srcs %}
+set search_path $search_path_initial
+{% for incdir in group.incdirs %}{#                                                                                 Add group's include directories
+#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}{#                                                                      Catch errors immediately
+#}analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \{#    Analyze command for SystemVerilog or VHDL #}
+    {% for define in group.defines %}{#                                                                             Add group's defines
+#}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% for file in group.files %}{#                                                                                 Add group's files
+#}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{#                                                                      Common block for all files
+#}{% for file in all_verilog %}{#                                                                                   Loop over verilog files
+#}{% if loop.first %}set search_path $search_path_initial
+{% for incdir in all_incdirs %}{#                                                                                   Add all include directories
+#}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
+{% endfor %}
+{% if abort_on_error %}if {[catch { {% endif %}{#                                                                      Catch errors immediately
+#}analyze -format sv \{#                                                                                            Analyze command for SystemVerilog #}
+    {% for define in all_defines %}{#                                                                               Add all defines
+}
+#}{% if loop.first %}-define { \
+        {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
+    } \
+    {% else %} \
+        {% endif %}{% endfor %}[list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{#                                        Add all verilog files #}
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{#                                                                     Loop over all VHDL files
+#}{% if abort_on_error %}if {[catch { {% endif %}{#                                                                    Catch errors immediately
+#}analyze -format vhdl \{#                                                                                          Analyze command for VHDL #}
+    [list \
+    {% endif %}{{ '    ' }}"{{ file | replace(from=root, to='$ROOT') }}" \{#                                        Add all VHDL files #}
+    {% if loop.last %}]
+{% if abort_on_error %}}]} {return 1}{% endif %}
+{% endif %}{% endfor %}
+{% endif %}set search_path $search_path_initial
diff --git a/src/script_fmt/vcs_sh.tera b/src/script_fmt/vcs_sh.tera
new file mode 100644
index 00000000..6479db1e
--- /dev/null
+++ b/src/script_fmt/vcs_sh.tera
@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+# {{ HEADER_AUTOGEN }}
+ROOT="{{ root }}"
+{% if compilation_mode == 'separate' %}{% for group in srcs %}
+{% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \
+    -full64 \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% endfor %}
+{% endfor %}
+{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{{ vlogan_bin }} -sverilog \
+    -full64 \
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% if loop.last %}
+{% endif %}{% endfor %}
+{% for file in all_vhdl %}{% if loop.first %}{{ vhdlan_bin }} \
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% if loop.last %}
+{% endif %}{% endfor %}
+{% endif %}
diff --git a/src/script_fmt/verilator_sh.tera b/src/script_fmt/verilator_sh.tera
new file mode 100644
index 00000000..706b362e
--- /dev/null
+++ b/src/script_fmt/verilator_sh.tera
@@ -0,0 +1,6 @@
+{% for group in srcs %}{% if group.file_type == 'verilog' %}
+{% for tmp_arg in vlog_args %}{{ tmp_arg }}
+{% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}
+{% endfor %}{% for incdir in group.incdirs %}+incdir+{{ incdir | replace(from=root, to='$ROOT') }}
+{% endfor %}{% for file in group.files %}{{ file }}
+{% endfor %}{% endif %}{% endfor %}
diff --git a/src/script_fmt/vivado_tcl.tera b/src/script_fmt/vivado_tcl.tera
new file mode 100644
index 00000000..3fa39c9a
--- /dev/null
+++ b/src/script_fmt/vivado_tcl.tera
@@ -0,0 +1,28 @@
+# {{ HEADER_AUTOGEN }}
+set ROOT "{{ root }}"
+{% if compilation_mode == 'separate' %}{#                                                               Individual block for each source file group
+#}{% for group in srcs %}add_files -norecurse -fileset [current_fileset] [list \{#                      Add files command #}
+    {% for file in group.files %}{{ file | replace(from=root, to='$ROOT') }} \{#                        Add group's files #}
+{% if not loop.last %}    {% endif %}{% endfor %}]
+{% endfor %}{% else %}{# compilation_mode == 'common' #}{#                                              Common block for all files
+#}{% for file in all_files %}{#                                                                         Loop over all files
+#}{% if loop.first %}add_files -norecurse -fileset [current_fileset] [list \{#                          Add files command #}
+    {% endif %}{{ file | replace(from=root, to='$ROOT') }} \{#                                          Add all files #}
+{% if not loop.last %}    {% endif %}{% if loop.last %}]
+{% endif %}{% endfor %}{% endif %}{#
+#}{% for arg in vivado_filesets %}{#                                                                    Loop over vivado arguments
+#}{% for incdir in all_incdirs %}{#                                                                     Loop over include directories
+#}{% if loop.first %}
+set_property include_dirs [list \
+    {% endif %}{{incdir | replace(from=root, to='$ROOT') }}{%if loop.last %} \{#                        Add all include directories #}
+] [current_fileset{{ arg }}]{#                                                                          Add all arguments #}
+{% else %} \
+    {% endif %}{% endfor %}{% endfor %}{#
+#}{% for arg in vivado_filesets %}{#                                                                    Loop over vivado arguments
+#}{% for define in all_defines %}{#                                                                     Loop over defines
+#}{% if loop.first %}
+set_property verilog_define [list \
+    {% endif %}{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \{#  Add all defines #}
+] [current_fileset{{ arg }}]{#                                                                          Add all arguments #}
+{% else %} \
+    {% endif %}{% endfor %}{% endfor %}
diff --git a/src/script_fmt/vsim_tcl.tera b/src/script_fmt/vsim_tcl.tera
new file mode 100644
index 00000000..2b9f4b53
--- /dev/null
+++ b/src/script_fmt/vsim_tcl.tera
@@ -0,0 +1,46 @@
+# {{ HEADER_AUTOGEN }}
+set ROOT "{{ root }}"
+{% if compilation_mode == 'separate' %}{#                                                                       Individual block for each source file group
+#}{% for group in srcs %}
+{% if abort_on_error %}if {[catch { {% endif %}{#                                                               Catch errors immediately
+#}{% if group.file_type == 'verilog' %}vlog -incr -sv \{#                                                       Compile verilog (& systemverilog) files with vlog -sv #}
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{#                                                                                              Add all vlog arguments
+#}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{#                                                                                              Add group's defines
+#}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{#                                                                                              Add group's include directories
+#}{% elif group.file_type == 'vhdl' %}vcom -2008 \{#                                                            Compile VHDL files with vcom #}
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{#                                                                                              Add all vcom arguments
+#}{% endif %}{#
+#}{% for file in group.files %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{% endfor %}{#                                                                                   Add group's files
+#}{% if abort_on_error %}\
+}]} {return 1}{% endif %}
+{% endfor %}{#
+#}{% else %}{# compilation_mode == 'common' #}{#                                                                Common block for all files
+#}{% for file in all_verilog %}{% if loop.first %}{#                                                            Loop over verilog files
+#}{% if abort_on_error %}if {[catch { {% endif %}{#                                                             Catch errors immediately
+#}vlog -incr -sv \{#                                                                                            Compile verilog (& systemverilog) files with vlog -sv #}
+    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
+    {% endfor %}{#                                                                                              Add all vlog arguments
+#}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \
+    {% endfor %}{#                                                                                              Add all defines
+#}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
+    {% endfor %}{#                                                                                              Add all include directories
+#}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{#                                                                                               Add all verilog files
+#}{% if loop.last %}{% if abort_on_error %} \
+}]} {return 1}{% endif %}
+{% endif %}{% endfor %}{#
+#}{% for file in all_vhdl %}{% if loop.first %}{#                                                               Loop over VHDL files
+#}{% if abort_on_error %}if {[catch { {% endif %}{#                                                             Catch errors immediately
+#}vcom -2008 \{#                                                                                                Compile VHDL files with vcom #}
+    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
+    {% endfor %}{#                                                                                              Add all vcom arguments
+#}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
+    {% endif %}{#                                                                                               Add all VHDL files
+#}{% if loop.last %}{% if abort_on_error %} \
+}]} {return 1}{% endif %}
+{% endif %}{% endfor %}{% endif %}