From 82b7e08386e908fc89e54cf18bb2a1d047b923d2 Mon Sep 17 00:00:00 2001 From: Samuel Riedel Date: Mon, 22 Apr 2024 11:35:26 +0200 Subject: [PATCH] Put vcs and vsim defines in quotes Fixes #162 --- CHANGELOG.md | 2 ++ src/script_fmt/riviera_tcl.tera | 4 ++-- src/script_fmt/vcs_sh.tera | 4 ++-- src/script_fmt/vsim_tcl.tera | 4 ++-- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c666d5f5..4adb1b66 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,8 @@ All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). ## Unreleased +### Fixed +- Put `vcs`, `vsim`, and `riviera` defines in quotes. ## 0.28.1 - 2024-02-22 ### Added diff --git a/src/script_fmt/riviera_tcl.tera b/src/script_fmt/riviera_tcl.tera index 9748af4c..c8a5dd88 100644 --- a/src/script_fmt/riviera_tcl.tera +++ b/src/script_fmt/riviera_tcl.tera @@ -3,7 +3,7 @@ set ROOT "{{ root }}" vlib work {% if compilation_mode == 'separate' %}{% for group in srcs %}{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}vlog -sv \ {% for tmp_arg in vlog_args %}{{ tmp_arg }} \ - {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \ + {% endfor %}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \ {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \ {% endfor %}{% elif group.file_type == 'vhdl' %}vcom -2008 \ {% for tmp_arg in vcom_args %}{{ tmp_arg }} \ @@ -13,7 +13,7 @@ vlib work {% endfor %}{% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \ {% for tmp_arg in vlog_args %}{{ tmp_arg }} \ - {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \ + {% endfor %}{% for define in all_defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \ {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \ {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\ {% else %}\ diff --git a/src/script_fmt/vcs_sh.tera b/src/script_fmt/vcs_sh.tera index 6479db1e..fd3b34c7 100644 --- a/src/script_fmt/vcs_sh.tera +++ b/src/script_fmt/vcs_sh.tera @@ -5,7 +5,7 @@ ROOT="{{ root }}" {% if group.file_type == 'verilog' %}{{ vlogan_bin }} -sverilog \ -full64 \ {% for tmp_arg in vlog_args %}{{ tmp_arg }} \ - {% endfor %}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \ + {% endfor %}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \ {% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \ {% endfor %}{% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \ {% for tmp_arg in vcom_args %}{{ tmp_arg }} \ @@ -15,7 +15,7 @@ ROOT="{{ root }}" {% else %}{# compilation_mode == 'common' #}{% for file in all_verilog %}{% if loop.first %}{{ vlogan_bin }} -sverilog \ -full64 \ {% for tmp_arg in vlog_args %}{{ tmp_arg }} \ - {% endfor %}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \ + {% endfor %}{% for define in all_defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \ {% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \ {% endfor %}{% endif %}"{{ file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\ {% endif %}{% if loop.last %} diff --git a/src/script_fmt/vsim_tcl.tera b/src/script_fmt/vsim_tcl.tera index 2b9f4b53..8d2ee5be 100644 --- a/src/script_fmt/vsim_tcl.tera +++ b/src/script_fmt/vsim_tcl.tera @@ -6,7 +6,7 @@ set ROOT "{{ root }}" #}{% if group.file_type == 'verilog' %}vlog -incr -sv \{# Compile verilog (& systemverilog) files with vlog -sv #} {% for tmp_arg in vlog_args %}{{ tmp_arg }} \ {% endfor %}{# Add all vlog arguments -#}{% for define in group.defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \ +#}{% for define in group.defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \ {% endfor %}{# Add group's defines #}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \ {% endfor %}{# Add group's include directories @@ -25,7 +25,7 @@ set ROOT "{{ root }}" #}vlog -incr -sv \{# Compile verilog (& systemverilog) files with vlog -sv #} {% for tmp_arg in vlog_args %}{{ tmp_arg }} \ {% endfor %}{# Add all vlog arguments -#}{% for define in all_defines %}+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %} \ +#}{% for define in all_defines %}"+define+{{ define.0 | upper }}{% if define.1 %}={{ define.1 }}{% endif %}" \ {% endfor %}{# Add all defines #}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \ {% endfor %}{# Add all include directories