diff --git a/CHANGELOG.md b/CHANGELOG.md index 75ed059c4..6ea190f79 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ### Added ### Changed +- `axi_err_slv`: Add optional parameter to define data returned by read response. The parameter + defaults to a 64-bit value, so buses with data width larger than or equal to 64 bit see an + additional 32-bit value in error responses compared to the prior version. Other than that, this + change is fully backward compatible. ### Fixed diff --git a/src/axi_err_slv.sv b/src/axi_err_slv.sv index 3a1356e51..b3a8b9cd1 100644 --- a/src/axi_err_slv.sv +++ b/src/axi_err_slv.sv @@ -14,12 +14,14 @@ // it. This module optionally supports ATOPs if the `ATOPs` parameter is set. module axi_err_slv #( - parameter int unsigned AxiIdWidth = 0, // AXI ID Width - parameter type req_t = logic, // AXI 4 request struct, with atop field - parameter type resp_t = logic, // AXI 4 response struct - parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. - parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. - parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling + parameter int unsigned AxiIdWidth = 0, // AXI ID Width + parameter type req_t = logic, // AXI 4 request struct, with atop field + parameter type resp_t = logic, // AXI 4 response struct + parameter axi_pkg::resp_t Resp = axi_pkg::RESP_DECERR, // Error generated by this slave. + parameter int unsigned RespWidth = 32'd64, // Data response width, gets zero extended or truncated to r.data. + parameter logic [RespWidth-1:0] RespData = 64'hCA11AB1EBADCAB1E, // Hexvalue for data return value + parameter bit ATOPs = 1'b1, // Activate support for ATOPs. Set to 1 if this slave could ever get an atomic AXI transaction. + parameter int unsigned MaxTrans = 1 // Maximum # of accepted transactions before stalling ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low @@ -188,7 +190,7 @@ module axi_err_slv #( // r_channel err_resp.r = '0; err_resp.r.id = r_fifo_data.id; - err_resp.r.data = 32'hBADCAB1E; + err_resp.r.data = RespData; err_resp.r.resp = Resp; err_resp.r_valid = 1'b0; // control