diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index b861aaf41..02abe60fe 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -102,16 +102,13 @@ exec_test() { for MST_ID_USE in 3 5; do MST_ID=5 for DATA_WIDTH in 64 256; do - for PIPE in 0 1; do - call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \ - -gTbNumMasters=$NUM_MST \ - -gTbNumSlaves=$NUM_SLV \ - -gTbAxiIdWidthMasters=$MST_ID \ - -gTbAxiIdUsed=$MST_ID_USE \ - -gTbAxiDataWidth=$DATA_WIDTH \ - -gTbPipeline=$PIPE \ - -gTbEnAtop=$GEN_ATOP - done + call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \ + -gTbNumMasters=$NUM_MST \ + -gTbNumSlaves=$NUM_SLV \ + -gTbAxiIdWidthMasters=$MST_ID \ + -gTbAxiIdUsed=$MST_ID_USE \ + -gTbAxiDataWidth=$DATA_WIDTH \ + -gTbEnableAtops=$GEN_ATOP done done done diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index 75795cc8c..8699664b6 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -40,10 +40,8 @@ module tb_axi_xbar #( parameter int unsigned TbAxiIdUsed = 32'd3, /// Data width of the AXI channels. parameter int unsigned TbAxiDataWidth = 32'd64, - /// Pipeline stages in the xbar itself. (Between Demux and mux) - parameter int unsigned TbPipeline = 32'd1, /// Eanable ATOP generation - parameter bit TbEnAtop = 1'b1 + parameter bit TbEnableAtops = 1'b1 ); // TB timing parameters @@ -55,26 +53,20 @@ module tb_axi_xbar #( localparam int unsigned TbAxiIdWidthSlaves = TbAxiIdWidthMasters + $clog2(TbNumMasters); localparam int unsigned TbAxiAddrWidth = 32'd32; localparam int unsigned TbAxiStrbWidth = TbAxiDataWidth / 8; - localparam int unsigned TbAxiUserWidth = 5; - // In the bench can change this variables which are set here freely, - localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ - NoSlvPorts: TbNumMasters, - NoMstPorts: TbNumSlaves, - MaxMstTrans: 10, - MaxSlvTrans: 6, - FallThrough: 1'b0, - LatencyMode: axi_pkg::CUT_ALL_AX, - PipelineStages: TbPipeline, - AxiIdWidthSlvPorts: TbAxiIdWidthMasters, - AxiIdUsedSlvPorts: TbAxiIdUsed, - AxiAddrWidth: TbAxiAddrWidth, - AxiDataWidth: TbAxiDataWidth, - NoAddrRules: TbNumSlaves - }; + localparam int unsigned TbAxiUserWidth = 32'd5; + // In the bench can change these variables which are set here freely, + // Set all XBAR parameter here, even if they do not change per default. + // Makes sure that they are properly propageted through the interface wrapper. + localparam int unsigned TbSlvPortMaxTxns = 32'd10; + localparam int unsigned TbMstPortMaxTxns = 32'd6; + localparam int unsigned TbFallThrough = 1'b0; + localparam int unsigned TbLatencyMode = axi_pkg::NO_LATENCY; + localparam int unsigned TbNumAddrRules = TbNumSlaves; + typedef logic [TbAxiIdWidthMasters-1:0] id_mst_t; typedef logic [TbAxiIdWidthSlaves-1:0] id_slv_t; typedef logic [TbAxiAddrWidth-1:0] addr_t; - typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + typedef axi_pkg::xbar_rule_32_t tb_addr_rule_t; // Has to be the same width as axi addr typedef logic [TbAxiDataWidth-1:0] data_t; typedef logic [TbAxiStrbWidth-1:0] strb_t; typedef logic [TbAxiUserWidth-1:0] user_t; @@ -96,11 +88,11 @@ module tb_axi_xbar #( `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t) // Each slave has its own address range: - localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = addr_map_gen(); + localparam tb_addr_rule_t [TbNumAddrRules-1:0] AddrMap = addr_map_gen(); - function rule_t [xbar_cfg.NoAddrRules-1:0] addr_map_gen (); - for (int unsigned i = 0; i < xbar_cfg.NoAddrRules; i++) begin - addr_map_gen[i] = rule_t'{ + function tb_addr_rule_t [TbNumAddrRules-1:0] addr_map_gen (); + for (int unsigned i = 0; i < TbNumAddrRules; i++) begin + addr_map_gen[i] = tb_addr_rule_t'{ idx: unsigned'(i), start_addr: i * 32'h0000_2000, end_addr: (i+1) * 32'h0000_2000, @@ -121,7 +113,7 @@ module tb_axi_xbar #( // Maximum number of read and write transactions in flight .MAX_READ_TXNS ( 20 ), .MAX_WRITE_TXNS ( 20 ), - .AXI_ATOPS ( TbEnAtop ) + .AXI_ATOPS ( TbEnableAtops ) ) axi_rand_master_t; typedef axi_test::axi_rand_slave #( // AXI interface parameters @@ -158,23 +150,24 @@ module tb_axi_xbar #( .AXI_DATA_WIDTH ( TbAxiDataWidth ), .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), .AXI_USER_WIDTH ( TbAxiUserWidth ) - ) master [TbNumMasters-1:0] (); + ) master [TbNumMasters] (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), .AXI_DATA_WIDTH ( TbAxiDataWidth ), .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), .AXI_USER_WIDTH ( TbAxiUserWidth ) - ) master_dv [TbNumMasters-1:0] (clk); + ) master_dv [TbNumMasters] (clk); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), .AXI_DATA_WIDTH ( TbAxiDataWidth ), .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), .AXI_USER_WIDTH ( TbAxiUserWidth ) - ) master_monitor_dv [TbNumMasters-1:0] (clk); - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_conn_dv_masters + ) master_monitor_dv [TbNumMasters] (clk); + for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_conn_dv_masters `AXI_ASSIGN (master[i], master_dv[i]) + `AXI_ASSIGN_MONITOR(master_monitor_dv[i], master[i]) `AXI_ASSIGN_TO_REQ(masters_req[i], master[i]) - `AXI_ASSIGN_FROM_RESP(master[i], masters_resp[i]) + `AXI_ASSIGN_TO_RESP(masters_resp[i], master[i]) end AXI_BUS #( @@ -182,34 +175,35 @@ module tb_axi_xbar #( .AXI_DATA_WIDTH ( TbAxiDataWidth ), .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), .AXI_USER_WIDTH ( TbAxiUserWidth ) - ) slave [TbNumSlaves-1:0] (); + ) slave [TbNumSlaves] (); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), .AXI_DATA_WIDTH ( TbAxiDataWidth ), .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), .AXI_USER_WIDTH ( TbAxiUserWidth ) - ) slave_dv [TbNumSlaves-1:0](clk); + ) slave_dv [TbNumSlaves](clk); AXI_BUS_DV #( .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), .AXI_DATA_WIDTH ( TbAxiDataWidth ), .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), .AXI_USER_WIDTH ( TbAxiUserWidth ) - ) slave_monitor_dv [TbNumSlaves-1:0](clk); - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_conn_dv_slaves + ) slave_monitor_dv [TbNumSlaves](clk); + for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_conn_dv_slaves `AXI_ASSIGN(slave_dv[i], slave[i]) - `AXI_ASSIGN_FROM_REQ(slave[i], slaves_req[i]) + `AXI_ASSIGN_MONITOR(slave_monitor_dv[i], slave[i]) + `AXI_ASSIGN_TO_REQ(slaves_req[i], slave[i]) `AXI_ASSIGN_TO_RESP(slaves_resp[i], slave[i]) end // ------------------------------- // AXI Rand Masters and Slaves // ------------------------------- // Masters control simulation run time - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_rand_master + for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_rand_master initial begin static axi_rand_master_t axi_rand_master = new ( master_dv[i] ); end_of_sim[i] <= 1'b0; axi_rand_master.add_memory_region(AddrMap[0].start_addr, - AddrMap[xbar_cfg.NoAddrRules-1].end_addr, + AddrMap[TbNumAddrRules-1].end_addr, axi_pkg::DEVICE_NONBUFFERABLE); axi_rand_master.reset(); @(posedge rst_n); @@ -218,7 +212,7 @@ module tb_axi_xbar #( end end - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_rand_slave + for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_rand_slave initial begin static axi_rand_slave_t axi_rand_slave = new( slave_dv[i] ); axi_rand_slave.reset(); @@ -229,23 +223,23 @@ module tb_axi_xbar #( initial begin : proc_monitor static tb_axi_xbar_pkg::axi_xbar_monitor #( - .AxiAddrWidth ( TbAxiAddrWidth ), - .AxiDataWidth ( TbAxiDataWidth ), - .AxiIdWidthMasters ( TbAxiIdWidthMasters ), - .AxiIdWidthSlaves ( TbAxiIdWidthSlaves ), - .AxiUserWidth ( TbAxiUserWidth ), - .NoMasters ( TbNumMasters ), - .NoSlaves ( TbNumSlaves ), - .NoAddrRules ( xbar_cfg.NoAddrRules ), - .rule_t ( rule_t ), - .AddrMap ( AddrMap ), - .TimeTest ( TestTime ) + .AddrWidth ( TbAxiAddrWidth ), + .DataWidth ( TbAxiDataWidth ), + .SlvPortIdWidth ( TbAxiIdWidthMasters ), + .MstPortIdWidth ( TbAxiIdWidthSlaves ), + .UserWidth ( TbAxiUserWidth ), + .NumSlvPorts ( TbNumMasters ), + .NumMstPorts ( TbNumSlaves ), + .NumAddrRules ( TbNumAddrRules ), + .rule_t ( tb_addr_rule_t ), + .AddrMap ( AddrMap ), + .TestTime ( TestTime ) ) monitor = new( master_monitor_dv, slave_monitor_dv ); fork monitor.run(); do begin #TestTime; - if(end_of_sim == '1) begin + if (end_of_sim == '1) begin monitor.print_result(); $stop(); end @@ -268,37 +262,34 @@ module tb_axi_xbar #( //----------------------------------- // DUT //----------------------------------- - axi_xbar #( - .Cfg ( xbar_cfg ), - .slv_aw_chan_t( aw_chan_mst_t ), - .mst_aw_chan_t( aw_chan_slv_t ), - .w_chan_t ( w_chan_t ), - .slv_b_chan_t ( b_chan_mst_t ), - .mst_b_chan_t ( b_chan_slv_t ), - .slv_ar_chan_t( ar_chan_mst_t ), - .mst_ar_chan_t( ar_chan_slv_t ), - .slv_r_chan_t ( r_chan_mst_t ), - .mst_r_chan_t ( r_chan_slv_t ), - .slv_req_t ( mst_req_t ), - .slv_resp_t ( mst_resp_t ), - .mst_req_t ( slv_req_t ), - .mst_resp_t ( slv_resp_t ), - .rule_t ( rule_t ) + axi_xbar_intf #( + .NumSlvPorts ( TbNumMasters ), + .NumMstPorts ( TbNumSlaves ), + .SlvPortIdWidth ( TbAxiIdWidthMasters ), + .SlvPortIdWidthUsed ( TbAxiIdUsed ), + .AddrWidth ( TbAxiAddrWidth ), + .DataWidth ( TbAxiDataWidth ), + .UserWidth ( TbAxiUserWidth ), + .SlvPortMaxTxns ( TbSlvPortMaxTxns ), + .MstPortMaxTxns ( TbMstPortMaxTxns ), + .FallThrough ( TbFallThrough ), + .LatencyMode ( TbLatencyMode ), + .NumAddrRules ( TbNumAddrRules ), + .EnableAtops ( TbEnableAtops ), + .rule_t ( tb_addr_rule_t ) ) i_xbar_dut ( .clk_i ( clk ), .rst_ni ( rst_n ), .test_i ( 1'b0 ), - .slv_ports_req_i ( masters_req ), - .slv_ports_resp_o ( masters_resp ), - .mst_ports_req_o ( slaves_req ), - .mst_ports_resp_i ( slaves_resp ), + .slv_ports ( master ), + .mst_ports ( slave ), .addr_map_i ( AddrMap ), .en_default_mst_port_i ( '0 ), - .default_mst_port_i ( '0 ) + .default_mst_ports_i ( '0 ) ); // logger for master modules - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_master_logger + for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_master_logger axi_chan_logger #( .TestTime ( TestTime ), // Time after clock, where sampling happens .LoggerName( $sformatf("axi_logger_master_%0d", i)), @@ -334,7 +325,7 @@ module tb_axi_xbar #( ); end // logger for slave modules - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_slave_logger + for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_slave_logger axi_chan_logger #( .TestTime ( TestTime ), // Time after clock, where sampling happens .LoggerName( $sformatf("axi_logger_slave_%0d",i)), @@ -369,100 +360,4 @@ module tb_axi_xbar #( .r_ready_i ( slaves_req[i].r_ready ) ); end - - - for (genvar i = 0; i < TbNumMasters; i++) begin : gen_connect_master_monitor - assign master_monitor_dv[i].aw_id = master[i].aw_id ; - assign master_monitor_dv[i].aw_addr = master[i].aw_addr ; - assign master_monitor_dv[i].aw_len = master[i].aw_len ; - assign master_monitor_dv[i].aw_size = master[i].aw_size ; - assign master_monitor_dv[i].aw_burst = master[i].aw_burst ; - assign master_monitor_dv[i].aw_lock = master[i].aw_lock ; - assign master_monitor_dv[i].aw_cache = master[i].aw_cache ; - assign master_monitor_dv[i].aw_prot = master[i].aw_prot ; - assign master_monitor_dv[i].aw_qos = master[i].aw_qos ; - assign master_monitor_dv[i].aw_region = master[i].aw_region; - assign master_monitor_dv[i].aw_atop = master[i].aw_atop ; - assign master_monitor_dv[i].aw_user = master[i].aw_user ; - assign master_monitor_dv[i].aw_valid = master[i].aw_valid ; - assign master_monitor_dv[i].aw_ready = master[i].aw_ready ; - assign master_monitor_dv[i].w_data = master[i].w_data ; - assign master_monitor_dv[i].w_strb = master[i].w_strb ; - assign master_monitor_dv[i].w_last = master[i].w_last ; - assign master_monitor_dv[i].w_user = master[i].w_user ; - assign master_monitor_dv[i].w_valid = master[i].w_valid ; - assign master_monitor_dv[i].w_ready = master[i].w_ready ; - assign master_monitor_dv[i].b_id = master[i].b_id ; - assign master_monitor_dv[i].b_resp = master[i].b_resp ; - assign master_monitor_dv[i].b_user = master[i].b_user ; - assign master_monitor_dv[i].b_valid = master[i].b_valid ; - assign master_monitor_dv[i].b_ready = master[i].b_ready ; - assign master_monitor_dv[i].ar_id = master[i].ar_id ; - assign master_monitor_dv[i].ar_addr = master[i].ar_addr ; - assign master_monitor_dv[i].ar_len = master[i].ar_len ; - assign master_monitor_dv[i].ar_size = master[i].ar_size ; - assign master_monitor_dv[i].ar_burst = master[i].ar_burst ; - assign master_monitor_dv[i].ar_lock = master[i].ar_lock ; - assign master_monitor_dv[i].ar_cache = master[i].ar_cache ; - assign master_monitor_dv[i].ar_prot = master[i].ar_prot ; - assign master_monitor_dv[i].ar_qos = master[i].ar_qos ; - assign master_monitor_dv[i].ar_region = master[i].ar_region; - assign master_monitor_dv[i].ar_user = master[i].ar_user ; - assign master_monitor_dv[i].ar_valid = master[i].ar_valid ; - assign master_monitor_dv[i].ar_ready = master[i].ar_ready ; - assign master_monitor_dv[i].r_id = master[i].r_id ; - assign master_monitor_dv[i].r_data = master[i].r_data ; - assign master_monitor_dv[i].r_resp = master[i].r_resp ; - assign master_monitor_dv[i].r_last = master[i].r_last ; - assign master_monitor_dv[i].r_user = master[i].r_user ; - assign master_monitor_dv[i].r_valid = master[i].r_valid ; - assign master_monitor_dv[i].r_ready = master[i].r_ready ; - end - for (genvar i = 0; i < TbNumSlaves; i++) begin : gen_connect_slave_monitor - assign slave_monitor_dv[i].aw_id = slave[i].aw_id ; - assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ; - assign slave_monitor_dv[i].aw_len = slave[i].aw_len ; - assign slave_monitor_dv[i].aw_size = slave[i].aw_size ; - assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ; - assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ; - assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ; - assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ; - assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ; - assign slave_monitor_dv[i].aw_region = slave[i].aw_region; - assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ; - assign slave_monitor_dv[i].aw_user = slave[i].aw_user ; - assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ; - assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ; - assign slave_monitor_dv[i].w_data = slave[i].w_data ; - assign slave_monitor_dv[i].w_strb = slave[i].w_strb ; - assign slave_monitor_dv[i].w_last = slave[i].w_last ; - assign slave_monitor_dv[i].w_user = slave[i].w_user ; - assign slave_monitor_dv[i].w_valid = slave[i].w_valid ; - assign slave_monitor_dv[i].w_ready = slave[i].w_ready ; - assign slave_monitor_dv[i].b_id = slave[i].b_id ; - assign slave_monitor_dv[i].b_resp = slave[i].b_resp ; - assign slave_monitor_dv[i].b_user = slave[i].b_user ; - assign slave_monitor_dv[i].b_valid = slave[i].b_valid ; - assign slave_monitor_dv[i].b_ready = slave[i].b_ready ; - assign slave_monitor_dv[i].ar_id = slave[i].ar_id ; - assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ; - assign slave_monitor_dv[i].ar_len = slave[i].ar_len ; - assign slave_monitor_dv[i].ar_size = slave[i].ar_size ; - assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ; - assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ; - assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ; - assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ; - assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ; - assign slave_monitor_dv[i].ar_region = slave[i].ar_region; - assign slave_monitor_dv[i].ar_user = slave[i].ar_user ; - assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ; - assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ; - assign slave_monitor_dv[i].r_id = slave[i].r_id ; - assign slave_monitor_dv[i].r_data = slave[i].r_data ; - assign slave_monitor_dv[i].r_resp = slave[i].r_resp ; - assign slave_monitor_dv[i].r_last = slave[i].r_last ; - assign slave_monitor_dv[i].r_user = slave[i].r_user ; - assign slave_monitor_dv[i].r_valid = slave[i].r_valid ; - assign slave_monitor_dv[i].r_ready = slave[i].r_ready ; - end -endmodule +endmodule : tb_axi_xbar diff --git a/test/tb_axi_xbar_pkg.sv b/test/tb_axi_xbar_pkg.sv index d46a09515..26dd08856 100644 --- a/test/tb_axi_xbar_pkg.sv +++ b/test/tb_axi_xbar_pkg.sv @@ -19,81 +19,81 @@ package tb_axi_xbar_pkg; class axi_xbar_monitor #( - parameter int unsigned AxiAddrWidth, - parameter int unsigned AxiDataWidth, - parameter int unsigned AxiIdWidthMasters, - parameter int unsigned AxiIdWidthSlaves, - parameter int unsigned AxiUserWidth, - parameter int unsigned NoMasters, - parameter int unsigned NoSlaves, - parameter int unsigned NoAddrRules, + parameter int unsigned AddrWidth, + parameter int unsigned DataWidth, + parameter int unsigned SlvPortIdWidth, + parameter int unsigned MstPortIdWidth, + parameter int unsigned UserWidth, + parameter int unsigned NumSlvPorts, + parameter int unsigned NumMstPorts, + parameter int unsigned NumAddrRules, parameter type rule_t, - parameter rule_t [NoAddrRules-1:0] AddrMap, + parameter rule_t [NumAddrRules-1:0] AddrMap, // Stimuli application and test time - parameter time TimeTest + parameter time TestTime ); - typedef logic [AxiIdWidthMasters-1:0] mst_axi_id_t; - typedef logic [AxiIdWidthSlaves-1:0] slv_axi_id_t; - typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [SlvPortIdWidth-1:0] slv_port_axi_id_t; + typedef logic [MstPortIdWidth-1:0] mst_port_axi_id_t; + typedef logic [AddrWidth-1:0] axi_addr_t; - typedef logic [$clog2(NoMasters)-1:0] idx_mst_t; - typedef int unsigned idx_slv_t; // from rule_t + typedef logic [$clog2(NumSlvPorts)-1:0] idx_mst_t; // Index of conected master + typedef int unsigned idx_slv_t; // Connected salve index from rule_t typedef struct packed { - mst_axi_id_t mst_axi_id; - logic last; + slv_port_axi_id_t mst_axi_id; + logic last; } master_exp_t; typedef struct packed { - slv_axi_id_t slv_axi_id; - axi_addr_t slv_axi_addr; - axi_pkg::len_t slv_axi_len; + mst_port_axi_id_t slv_axi_id; + axi_addr_t slv_axi_addr; + axi_pkg::len_t slv_axi_len; } exp_ax_t; typedef struct packed { - slv_axi_id_t slv_axi_id; - logic last; + mst_port_axi_id_t slv_axi_id; + logic last; } slave_exp_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( master_exp_t ), - .ID_WIDTH ( AxiIdWidthMasters ) + .data_t ( master_exp_t ), + .ID_WIDTH ( SlvPortIdWidth ) ) master_exp_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( exp_ax_t ), - .ID_WIDTH ( AxiIdWidthSlaves ) + .data_t ( exp_ax_t ), + .ID_WIDTH ( MstPortIdWidth ) ) ax_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( slave_exp_t ), - .ID_WIDTH ( AxiIdWidthSlaves ) + .data_t ( slave_exp_t ), + .ID_WIDTH ( MstPortIdWidth ) ) slave_exp_queue_t; //----------------------------------------- // Monitoring virtual interfaces //----------------------------------------- virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) masters_axi [NoMasters-1:0]; + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( SlvPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) slv_ports[NumSlvPorts]; virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) slaves_axi [NoSlaves-1:0]; + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( MstPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) mst_ports[NumMstPorts]; //----------------------------------------- // Queues and FIFOs to hold the expected ids //----------------------------------------- // Write transactions - ax_queue_t exp_aw_queue [NoSlaves-1:0]; - slave_exp_t exp_w_fifo [NoSlaves-1:0][$]; - slave_exp_t act_w_fifo [NoSlaves-1:0][$]; - master_exp_queue_t exp_b_queue [NoMasters-1:0]; + ax_queue_t exp_aw_queue [NumMstPorts-1:0]; + slave_exp_t exp_w_fifo [NumMstPorts-1:0][$]; + slave_exp_t act_w_fifo [NumMstPorts-1:0][$]; + master_exp_queue_t exp_b_queue [NumSlvPorts-1:0]; // Read transactions - ax_queue_t exp_ar_queue [NoSlaves-1:0]; - master_exp_queue_t exp_r_queue [NoMasters-1:0]; + ax_queue_t exp_ar_queue [NumMstPorts-1:0]; + master_exp_queue_t exp_r_queue [NumSlvPorts-1:0]; //----------------------------------------- // Bookkeeping @@ -108,29 +108,29 @@ package tb_axi_xbar_pkg; //----------------------------------------- function new( virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) axi_masters_vif [NoMasters-1:0], + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( SlvPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) slv_ports_vif[NumSlvPorts], virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) axi_slaves_vif [NoSlaves-1:0] + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( MstPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) mst_ports_vif[NumMstPorts] ); begin - this.masters_axi = axi_masters_vif; - this.slaves_axi = axi_slaves_vif; + this.slv_ports = slv_ports_vif; + this.mst_ports = mst_ports_vif; this.tests_expected = 0; this.tests_conducted = 0; this.tests_failed = 0; - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin this.exp_b_queue[i] = new; this.exp_r_queue[i] = new; end - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin this.exp_aw_queue[i] = new; this.exp_ar_queue[i] = new; end @@ -140,12 +140,12 @@ package tb_axi_xbar_pkg; // when start the testing task cycle_start; - #TimeTest; + #TestTime; endtask // when is cycle finished task cycle_end; - @(posedge masters_axi[0].clk_i); + @(posedge slv_ports[0].clk_i); endtask // This task monitors a slave ports of the crossbar. Every time an AW beat is seen @@ -155,50 +155,50 @@ package tb_axi_xbar_pkg; task automatic monitor_mst_aw(input int unsigned i); idx_slv_t to_slave_idx; exp_ax_t exp_aw; - slv_axi_id_t exp_aw_id; + mst_port_axi_id_t exp_aw_id; bit decerr; master_exp_t exp_b; - if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin + if (slv_ports[i].aw_valid && slv_ports[i].aw_ready) begin // check if it should go to a decerror decerr = 1'b1; - for (int unsigned j = 0; j < NoAddrRules; j++) begin - if ((masters_axi[i].aw_addr >= AddrMap[j].start_addr) && - (masters_axi[i].aw_addr < AddrMap[j].end_addr)) begin + for (int unsigned j = 0; j < NumAddrRules; j++) begin + if ((slv_ports[i].aw_addr >= AddrMap[j].start_addr) && + (slv_ports[i].aw_addr < AddrMap[j].end_addr)) begin to_slave_idx = idx_slv_t'(AddrMap[j].idx); decerr = 1'b0; end end // send the exp aw beat down into the queue of the slave when no decerror if (!decerr) begin - exp_aw_id = {idx_mst_t'(i), masters_axi[i].aw_id}; + exp_aw_id = {idx_mst_t'(i), slv_ports[i].aw_id}; // $display("Test exp aw_id: %b",exp_aw_id); exp_aw = '{slv_axi_id: exp_aw_id, - slv_axi_addr: masters_axi[i].aw_addr, - slv_axi_len: masters_axi[i].aw_len }; + slv_axi_addr: slv_ports[i].aw_addr, + slv_axi_len: slv_ports[i].aw_len }; this.exp_aw_queue[to_slave_idx].push(exp_aw_id, exp_aw); incr_expected_tests(3); $display("%0tns > Master %0d: AW to Slave %0d: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $time, i, to_slave_idx, slv_ports[i].aw_id); end else begin $display("%0tns > Master %0d: AW to Decerror: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $time, i, to_slave_idx, slv_ports[i].aw_id); end // populate the expected b queue anyway - exp_b = '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1}; - this.exp_b_queue[i].push(masters_axi[i].aw_id, exp_b); + exp_b = '{mst_axi_id: slv_ports[i].aw_id, last: 1'b1}; + this.exp_b_queue[i].push(slv_ports[i].aw_id, exp_b); incr_expected_tests(1); $display(" Expect B response."); // inject expected r beats on this id, if it is an atop - if(masters_axi[i].aw_atop[5]) begin + if(slv_ports[i].aw_atop[5]) begin // push the required r beats into the right fifo (reuse the exp_b variable) - $display(" Expect R response, len: %0d.", masters_axi[i].aw_len); - for (int unsigned j = 0; j <= masters_axi[i].aw_len; j++) begin - exp_b = (j == masters_axi[i].aw_len) ? - '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1} : - '{mst_axi_id: masters_axi[i].aw_id, last: 1'b0}; - this.exp_r_queue[i].push(masters_axi[i].aw_id, exp_b); + $display(" Expect R response, len: %0d.", slv_ports[i].aw_len); + for (int unsigned j = 0; j <= slv_ports[i].aw_len; j++) begin + exp_b = (j == slv_ports[i].aw_len) ? + '{mst_axi_id: slv_ports[i].aw_id, last: 1'b1} : + '{mst_axi_id: slv_ports[i].aw_id, last: 1'b0}; + this.exp_r_queue[i].push(slv_ports[i].aw_id, exp_b); incr_expected_tests(1); end end @@ -212,34 +212,34 @@ package tb_axi_xbar_pkg; exp_ax_t exp_aw; slave_exp_t exp_slv_w; // $display("%0t > Was triggered: aw_valid %b, aw_ready: %b", - // $time(), slaves_axi[i].aw_valid, slaves_axi[i].aw_ready); - if (slaves_axi[i].aw_valid && slaves_axi[i].aw_ready) begin + // $time(), mst_ports[i].aw_valid, mst_ports[i].aw_ready); + if (mst_ports[i].aw_valid && mst_ports[i].aw_ready) begin // test if the aw beat was expected - exp_aw = this.exp_aw_queue[i].pop_id(slaves_axi[i].aw_id); + exp_aw = this.exp_aw_queue[i].pop_id(mst_ports[i].aw_id); $display("%0tns > Slave %0d: AW Axi ID: %b", - $time, i, slaves_axi[i].aw_id); - if (exp_aw.slv_axi_id != slaves_axi[i].aw_id) begin + $time, i, mst_ports[i].aw_id); + if (exp_aw.slv_axi_id != mst_ports[i].aw_id) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b", i, slaves_axi[i].aw_id); + $error("Slave %0d: Unexpected AW with ID: %b", i, mst_ports[i].aw_id); end - if (exp_aw.slv_axi_addr != slaves_axi[i].aw_addr) begin + if (exp_aw.slv_axi_addr != mst_ports[i].aw_addr) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", - i, slaves_axi[i].aw_id, slaves_axi[i].aw_addr, exp_aw.slv_axi_addr); + $error("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", + i, mst_ports[i].aw_id, mst_ports[i].aw_addr, exp_aw.slv_axi_addr); end - if (exp_aw.slv_axi_len != slaves_axi[i].aw_len) begin + if (exp_aw.slv_axi_len != mst_ports[i].aw_len) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", - i, slaves_axi[i].aw_id, slaves_axi[i].aw_len, exp_aw.slv_axi_len); + $error("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", + i, mst_ports[i].aw_id, mst_ports[i].aw_len, exp_aw.slv_axi_len); end incr_conducted_tests(3); // push the required w beats into the right fifo - incr_expected_tests(slaves_axi[i].aw_len + 1); - for (int unsigned j = 0; j <= slaves_axi[i].aw_len; j++) begin - exp_slv_w = (j == slaves_axi[i].aw_len) ? - '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b1} : - '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b0}; + incr_expected_tests(mst_ports[i].aw_len + 1); + for (int unsigned j = 0; j <= mst_ports[i].aw_len; j++) begin + exp_slv_w = (j == mst_ports[i].aw_len) ? + '{slv_axi_id: mst_ports[i].aw_id, last: 1'b1} : + '{slv_axi_id: mst_ports[i].aw_id, last: 1'b0}; this.exp_w_fifo[i].push_back(exp_slv_w); end end @@ -248,9 +248,9 @@ package tb_axi_xbar_pkg; // This task just pushes every W beat that gets sent on a master port in its respective fifo. task automatic monitor_slv_w(input int unsigned i); slave_exp_t act_slv_w; - if (slaves_axi[i].w_valid && slaves_axi[i].w_ready) begin - // $display("%0t > W beat on Slave %0d, last flag: %b", $time, i, slaves_axi[i].w_last); - act_slv_w = '{last: slaves_axi[i].w_last , default:'0}; + if (mst_ports[i].w_valid && mst_ports[i].w_ready) begin + // $display("%0t > W beat on Slave %0d, last flag: %b", $time, i, mst_ports[i].w_last); + act_slv_w = '{last: mst_ports[i].w_last , default:'0}; this.act_w_fifo[i].push_back(act_slv_w); end endtask : monitor_slv_w @@ -268,7 +268,7 @@ package tb_axi_xbar_pkg; incr_conducted_tests(1); if(exp_w.last != act_w.last) begin incr_failed_tests(1); - $warning("Slave %d: unexpected W beat last flag %b, expected: %b.", + $error("Slave %d: unexpected W beat last flag %b, expected: %b.", i, act_w.last, exp_w.last); end end @@ -277,20 +277,20 @@ package tb_axi_xbar_pkg; // This task checks if a B response is allowed on a slave port of the crossbar. task automatic monitor_mst_b(input int unsigned i); master_exp_t exp_b; - mst_axi_id_t axi_b_id; - if (masters_axi[i].b_valid && masters_axi[i].b_ready) begin + slv_port_axi_id_t axi_b_id; + if (slv_ports[i].b_valid && slv_ports[i].b_ready) begin incr_conducted_tests(1); - axi_b_id = masters_axi[i].b_id; + axi_b_id = slv_ports[i].b_id; $display("%0tns > Master %0d: Got last B with id: %b", $time, i, axi_b_id); if (this.exp_b_queue[i].empty()) begin incr_failed_tests(1); - $warning("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); + $error("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); end else begin exp_b = this.exp_b_queue[i].pop_id(axi_b_id); if (axi_b_id != exp_b.mst_axi_id) begin incr_failed_tests(1); - $warning("Master: %d got unexpected B with ID: %b", i, axi_b_id); + $error("Master: %d got unexpected B with ID: %b", i, axi_b_id); end end end @@ -301,25 +301,25 @@ package tb_axi_xbar_pkg; // Emphasis on the last flag. We will detect reordering, if the last flags do not match, // as each `random` burst tend to have a different length. task automatic monitor_mst_ar(input int unsigned i); - mst_axi_id_t mst_axi_id; + slv_port_axi_id_t mst_axi_id; axi_addr_t mst_axi_addr; axi_pkg::len_t mst_axi_len; idx_slv_t exp_slv_idx; - slv_axi_id_t exp_slv_axi_id; + mst_port_axi_id_t exp_slv_axi_id; exp_ax_t exp_slv_ar; master_exp_t exp_mst_r; logic exp_decerr; - if (masters_axi[i].ar_valid && masters_axi[i].ar_ready) begin + if (slv_ports[i].ar_valid && slv_ports[i].ar_ready) begin exp_decerr = 1'b1; - mst_axi_id = masters_axi[i].ar_id; - mst_axi_addr = masters_axi[i].ar_addr; - mst_axi_len = masters_axi[i].ar_len; + mst_axi_id = slv_ports[i].ar_id; + mst_axi_addr = slv_ports[i].ar_addr; + mst_axi_len = slv_ports[i].ar_len; exp_slv_axi_id = {idx_mst_t'(i), mst_axi_id}; exp_slv_idx = '0; - for (int unsigned j = 0; j < NoAddrRules; j++) begin + for (int unsigned j = 0; j < NumAddrRules; j++) begin if ((mst_axi_addr >= AddrMap[j].start_addr) && (mst_axi_addr < AddrMap[j].end_addr)) begin exp_slv_idx = AddrMap[j].idx; exp_decerr = 1'b0; @@ -340,7 +340,7 @@ package tb_axi_xbar_pkg; incr_expected_tests(1); end // push the required r beats into the right fifo - $display(" Expect R response, len: %0d.", masters_axi[i].ar_len); + $display(" Expect R response, len: %0d.", slv_ports[i].ar_len); for (int unsigned j = 0; j <= mst_axi_len; j++) begin exp_mst_r = (j == mst_axi_len) ? '{mst_axi_id: mst_axi_id, last: 1'b1} : '{mst_axi_id: mst_axi_id, last: 1'b0}; @@ -354,10 +354,10 @@ package tb_axi_xbar_pkg; // expected. task automatic monitor_slv_ar(input int unsigned i); exp_ax_t exp_slv_ar; - slv_axi_id_t slv_axi_id; - if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin + mst_port_axi_id_t slv_axi_id; + if (mst_ports[i].ar_valid && mst_ports[i].ar_ready) begin incr_conducted_tests(1); - slv_axi_id = slaves_axi[i].ar_id; + slv_axi_id = mst_ports[i].ar_id; if (this.exp_ar_queue[i].empty()) begin incr_failed_tests(1); end else begin @@ -366,7 +366,7 @@ package tb_axi_xbar_pkg; $display("%0tns > Slave %0d: AR Axi ID: %b", $time, i, slv_axi_id); if (exp_slv_ar.slv_axi_id != slv_axi_id) begin incr_failed_tests(1); - $warning("Slave %d: Unexpected AR with ID: %b", i, slv_axi_id); + $error("Slave %d: Unexpected AR with ID: %b", i, slv_axi_id); end end end @@ -376,28 +376,28 @@ package tb_axi_xbar_pkg; // which are determined by the sequence of previously sent AR vectors. task automatic monitor_mst_r(input int unsigned i); master_exp_t exp_mst_r; - mst_axi_id_t mst_axi_r_id; + slv_port_axi_id_t mst_axi_r_id; logic mst_axi_r_last; - if (masters_axi[i].r_valid && masters_axi[i].r_ready) begin + if (slv_ports[i].r_valid && slv_ports[i].r_ready) begin incr_conducted_tests(1); - mst_axi_r_id = masters_axi[i].r_id; - mst_axi_r_last = masters_axi[i].r_last; + mst_axi_r_id = slv_ports[i].r_id; + mst_axi_r_last = slv_ports[i].r_last; if (mst_axi_r_last) begin $display("%0tns > Master %0d: Got last R with id: %b", $time, i, mst_axi_r_id); end if (this.exp_r_queue[i].empty()) begin incr_failed_tests(1); - $warning("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); + $error("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); end else begin exp_mst_r = this.exp_r_queue[i].pop_id(mst_axi_r_id); if (mst_axi_r_id != exp_mst_r.mst_axi_id) begin incr_failed_tests(1); - $warning("Master: %d got unexpected R with ID: %b", i, mst_axi_r_id); + $error("Master: %d got unexpected R with ID: %b", i, mst_axi_r_id); end if (mst_axi_r_last != exp_mst_r.last) begin incr_failed_tests(1); - $warning("Master: %d got unexpected R with ID: %b and last flag: %b", + $error("Master: %d got unexpected R with ID: %b and last flag: %b", i, mst_axi_r_id, mst_axi_r_last); end end @@ -436,48 +436,48 @@ package tb_axi_xbar_pkg; // execute all processes that put something into the queues PushMon: fork proc_mst_aw: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_aw(i); end end proc_mst_ar: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_ar(i); end end join : PushMon // this one pops and pushes something proc_slv_aw: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin monitor_slv_aw(i); end end proc_slv_w: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin monitor_slv_w(i); end end // These only pop somethong from the queses PopMon: fork proc_mst_b: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_b(i); end end proc_slv_ar: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin monitor_slv_ar(i); end end proc_mst_r: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_r(i); end end join : PopMon // check the slave W fifos last proc_check_slv_w: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin check_slv_w(i); end end