From ca5250a4351985aba26b5286feba0c06e24f06ef Mon Sep 17 00:00:00 2001 From: Andreas Kurth Date: Fri, 15 Jan 2021 11:32:10 +0100 Subject: [PATCH] axi_test: Rename `rand` classes to follow `axi_` prefix convention --- CHANGELOG.md | 6 ++++++ README.md | 8 ++++---- src/axi_test.sv | 8 ++++---- test/tb_axi_addr_test.sv | 26 +++++++++++++------------- test/tb_axi_atop_filter.sv | 4 ++-- test/tb_axi_cdc.sv | 4 ++-- test/tb_axi_dw_downsizer.sv | 4 ++-- test/tb_axi_dw_upsizer.sv | 4 ++-- test/tb_axi_isolate.sv | 26 +++++++++++++------------- test/tb_axi_lite_mailbox.sv | 2 +- test/tb_axi_lite_regs.sv | 2 +- test/tb_axi_lite_to_apb.sv | 10 +++++----- test/tb_axi_lite_xbar.sv | 4 ++-- test/tb_axi_modify_address.sv | 4 ++-- test/tb_axi_serializer.sv | 26 +++++++++++++------------- test/tb_axi_to_axi_lite.sv | 10 +++++----- test/tb_axi_xbar.sv | 22 +++++++++++----------- 17 files changed, 88 insertions(+), 82 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e663b5a81..088053d96 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - Add infinite, simulation-only memory `axi_sim_mem`. ### Changed +- Rename the following classes in `axi_test` to follow the convention that all user-facing objects + in this repository start with `axi_`: + - `rand_axi_lite_master` to `axi_lite_rand_master`, + - `rand_axi_lite_slave` to `axi_lite_rand_slave`, + - `rand_axi_master` to `axi_rand_master`, and + - `rand_axi_slave` to `axi_rand_slave`. ### Fixed diff --git a/README.md b/README.md index 52a24a801..96d33fccf 100644 --- a/README.md +++ b/README.md @@ -61,12 +61,12 @@ In addition to the modules above, which are available in synthesis and simulatio | [`axi_chan_logger`](src/axi_test.sv) | Logs the transactions of an AXI4(+ATOPs) port to files. | | [`axi_driver`](src/axi_test.sv) | Low-level driver for AXI4(+ATOPs) that can send and receive individual beats on any channel. | | [`axi_lite_driver`](src/axi_test.sv) | Low-level driver for AXI4-Lite that can send and receive individual beats on any channel. | +| [`axi_lite_rand_master`](src/axi_test.sv) | AXI4-Lite master component that issues random transactions within user-defined constraints. | +| [`axi_lite_rand_slave`](src/axi_test.sv) | AXI4-Lite slave component that responds to transactions with constrainable random delays and data. | +| [`axi_rand_master`](src/axi_test.sv) | AXI4(+ATOPs) master component that issues random transactions within user-defined constraints. | +| [`axi_rand_slave`](src/axi_test.sv) | AXI4(+ATOPs) slave component that responds to transactions with constrainable random delays and data. | | [`axi_scoreboard`](src/axi_test.sv) | Scoreboard that models a memory that only gets changed by the monitored AXI4(+ATOPs) port. | | [`axi_sim_mem`](src/axi_sim_mem.sv) | Infinite memory with AXI4 slave port. | -| [`rand_axi_lite_master`](src/axi_test.sv) | AXI4-Lite master component that issues random transactions within user-defined constraints. | -| [`rand_axi_lite_slave`](src/axi_test.sv) | AXI4-Lite slave component that responds to transactions with constrainable random delays and data. | -| [`rand_axi_master`](src/axi_test.sv) | AXI4(+ATOPs) master component that issues random transactions within user-defined constraints. | -| [`rand_axi_slave`](src/axi_test.sv) | AXI4(+ATOPs) slave component that responds to transactions with constrainable random delays and data. | diff --git a/src/axi_test.sv b/src/axi_test.sv index 0da9e1ac7..04ddefcf8 100644 --- a/src/axi_test.sv +++ b/src/axi_test.sv @@ -591,7 +591,7 @@ package axi_test; endclass - class rand_axi_master #( + class axi_rand_master #( // AXI interface parameters parameter int AW = 32, parameter int DW = 32, @@ -1162,7 +1162,7 @@ package axi_test; endclass - class rand_axi_slave #( + class axi_rand_slave #( // AXI interface parameters parameter int AW = 32, parameter int DW = 32, @@ -1316,7 +1316,7 @@ package axi_test; endclass // AXI4-Lite random master and slave - class rand_axi_lite_master #( + class axi_lite_rand_master #( // AXI interface parameters parameter int unsigned AW = 0, parameter int unsigned DW = 0, @@ -1485,7 +1485,7 @@ package axi_test; endtask : read endclass - class rand_axi_lite_slave #( + class axi_lite_rand_slave #( // AXI interface parameters parameter int unsigned AW = 0, parameter int unsigned DW = 0, diff --git a/test/tb_axi_addr_test.sv b/test/tb_axi_addr_test.sv index 39851962e..8d61f86bd 100644 --- a/test/tb_axi_addr_test.sv +++ b/test/tb_axi_addr_test.sv @@ -51,7 +51,7 @@ module tb_axi_addr_test #( localparam time ApplTime = 2ns; localparam time TestTime = 8ns; - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -64,8 +64,8 @@ module tb_axi_addr_test #( .AXI_BURST_FIXED ( 1'b1 ), .AXI_BURST_INCR ( 1'b1 ), .AXI_BURST_WRAP ( 1'b1 ) - ) rand_axi_master_t; - typedef axi_test::rand_axi_slave #( + ) axi_rand_master_t; + typedef axi_test::axi_rand_slave #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -74,7 +74,7 @@ module tb_axi_addr_test #( // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) rand_axi_slave_t; + ) axi_rand_slave_t; // ------------- // DUT signals // ------------- @@ -109,24 +109,24 @@ module tb_axi_addr_test #( ); initial begin : proc_axi_master - automatic rand_axi_master_t rand_axi_master = new(master_dv); + automatic axi_rand_master_t axi_rand_master = new(master_dv); end_of_sim <= 1'b0; - rand_axi_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE); - rand_axi_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE); - rand_axi_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE); - rand_axi_master.reset(); + axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_master.add_memory_region(16'h0000, 16'hFFFF, axi_pkg::WBACK_RWALLOCATE); + axi_rand_master.reset(); @(posedge rst_n); - rand_axi_master.run(0, NumTests); + axi_rand_master.run(0, NumTests); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); end initial begin : proc_axi_slave - automatic rand_axi_slave_t rand_axi_slave = new(slave_dv); - rand_axi_slave.reset(); + automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); + axi_rand_slave.reset(); @(posedge rst_n); - rand_axi_slave.run(); + axi_rand_slave.run(); end initial begin : proc_sim_progress diff --git a/test/tb_axi_atop_filter.sv b/test/tb_axi_atop_filter.sv index 2cc317f17..47dc0c152 100644 --- a/test/tb_axi_atop_filter.sv +++ b/test/tb_axi_atop_filter.sv @@ -115,7 +115,7 @@ module tb_axi_atop_filter #( // AXI Master logic mst_done = 1'b0; - axi_test::rand_axi_master #( + axi_test::axi_rand_master #( .AW(AXI_ADDR_WIDTH), .DW(AXI_DATA_WIDTH), .IW(AXI_ID_WIDTH), .UW(AXI_USER_WIDTH), .TA(TA), .TT(TT), .MAX_READ_TXNS (AXI_MAX_READ_TXNS), @@ -142,7 +142,7 @@ module tb_axi_atop_filter #( end // AXI Slave - axi_test::rand_axi_slave #( + axi_test::axi_rand_slave #( .AW(AXI_ADDR_WIDTH), .DW(AXI_DATA_WIDTH), .IW(AXI_ID_WIDTH), .UW(AXI_USER_WIDTH), .TA(TA), .TT(TT), .AX_MIN_WAIT_CYCLES (RESP_MIN_WAIT_CYCLES), diff --git a/test/tb_axi_cdc.sv b/test/tb_axi_cdc.sv index 418fb7401..94dd9bde8 100644 --- a/test/tb_axi_cdc.sv +++ b/test/tb_axi_cdc.sv @@ -131,7 +131,7 @@ module tb_axi_cdc #( .dst (downstream) ); - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( .AW (AXI_AW), .DW (AXI_DW), .IW (AXI_IW), @@ -155,7 +155,7 @@ module tb_axi_cdc #( axi_master.run(N_RD_TXNS, N_WR_TXNS); end - typedef axi_test::rand_axi_slave #( + typedef axi_test::axi_rand_slave #( .AW (AXI_AW), .DW (AXI_DW), .IW (AXI_IW), diff --git a/test/tb_axi_dw_downsizer.sv b/test/tb_axi_dw_downsizer.sv index f34a86a92..f20478f8b 100644 --- a/test/tb_axi_dw_downsizer.sv +++ b/test/tb_axi_dw_downsizer.sv @@ -78,7 +78,7 @@ module tb_axi_dw_downsizer #( `AXI_ASSIGN(master, master_dv) - axi_test::rand_axi_master #( + axi_test::axi_rand_master #( .AW (AxiAddrWidth ), .DW (AxiSlvPortDataWidth), .IW (AxiIdWidth ), @@ -109,7 +109,7 @@ module tb_axi_dw_downsizer #( .AXI_USER_WIDTH(AxiUserWidth ) ) slave (); - axi_test::rand_axi_slave #( + axi_test::axi_rand_slave #( .AW(AxiAddrWidth ), .DW(AxiMstPortDataWidth), .IW(AxiIdWidth ), diff --git a/test/tb_axi_dw_upsizer.sv b/test/tb_axi_dw_upsizer.sv index e10c31d05..54fc926d1 100644 --- a/test/tb_axi_dw_upsizer.sv +++ b/test/tb_axi_dw_upsizer.sv @@ -75,7 +75,7 @@ module tb_axi_dw_upsizer #( `AXI_ASSIGN(master, master_dv) - axi_test::rand_axi_master #( + axi_test::axi_rand_master #( .AW (AxiAddrWidth ), .DW (AxiSlvPortDataWidth), .IW (AxiIdWidth ), @@ -105,7 +105,7 @@ module tb_axi_dw_upsizer #( .AXI_USER_WIDTH(AxiUserWidth ) ) slave (); - axi_test::rand_axi_slave #( + axi_test::axi_rand_slave #( .AW(AxiAddrWidth ), .DW(AxiMstPortDataWidth), .IW(AxiIdWidth ), diff --git a/test/tb_axi_isolate.sv b/test/tb_axi_isolate.sv index f2acf26d0..0d3d7ef93 100644 --- a/test/tb_axi_isolate.sv +++ b/test/tb_axi_isolate.sv @@ -36,7 +36,7 @@ module tb_axi_isolate #( localparam int unsigned PrintTnx = 1000; - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -49,8 +49,8 @@ module tb_axi_isolate #( .MAX_READ_TXNS ( MaxAR ), .MAX_WRITE_TXNS ( MaxAW ), .AXI_ATOPS ( EnAtop ) - ) rand_axi_master_t; - typedef axi_test::rand_axi_slave #( + ) axi_rand_master_t; + typedef axi_test::axi_rand_slave #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -59,7 +59,7 @@ module tb_axi_isolate #( // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) rand_axi_slave_t; + ) axi_rand_slave_t; // ------------- // DUT signals @@ -129,24 +129,24 @@ module tb_axi_isolate #( ); initial begin : proc_axi_master - automatic rand_axi_master_t rand_axi_master = new(master_dv); + automatic axi_rand_master_t axi_rand_master = new(master_dv); end_of_sim <= 1'b0; - rand_axi_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); - rand_axi_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); - rand_axi_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); - rand_axi_master.reset(); + axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); + axi_rand_master.reset(); @(posedge rst_n); - rand_axi_master.run(NoReads, NoWrites); + axi_rand_master.run(NoReads, NoWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); $stop(); end initial begin : proc_axi_slave - automatic rand_axi_slave_t rand_axi_slave = new(slave_dv); - rand_axi_slave.reset(); + automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); + axi_rand_slave.reset(); @(posedge rst_n); - rand_axi_slave.run(); + axi_rand_slave.run(); end initial begin : proc_sim_ctl diff --git a/test/tb_axi_lite_mailbox.sv b/test/tb_axi_lite_mailbox.sv index 906d69d86..45479e48c 100644 --- a/test/tb_axi_lite_mailbox.sv +++ b/test/tb_axi_lite_mailbox.sv @@ -60,7 +60,7 @@ module tb_axi_lite_mailbox; CTRL = addr_t'(9 * AxiDataWidth/8) } reg_addr_e; - typedef axi_test::rand_axi_lite_master #( + typedef axi_test::axi_lite_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), diff --git a/test/tb_axi_lite_regs.sv b/test/tb_axi_lite_regs.sv index 4c40308a4..52fc50260 100644 --- a/test/tb_axi_lite_regs.sv +++ b/test/tb_axi_lite_regs.sv @@ -49,7 +49,7 @@ module tb_axi_lite_regs #( localparam byte_t [RegNumBytes-1:0] RegRstVal = '0; - typedef axi_test::rand_axi_lite_master #( + typedef axi_test::axi_lite_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index a9b9885a5..d1df36266 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -78,7 +78,7 @@ module tb_axi_lite_to_apb; '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} }; - typedef axi_test::rand_axi_lite_master #( + typedef axi_test::axi_lite_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -97,7 +97,7 @@ module tb_axi_lite_to_apb; .W_MAX_WAIT_CYCLES ( 5 ), .RESP_MIN_WAIT_CYCLES ( 0 ), .RESP_MAX_WAIT_CYCLES ( 20 ) - ) rand_axi_lite_master_t; + ) axi_lite_rand_master_t; // ------------- // DUT signals @@ -135,11 +135,11 @@ module tb_axi_lite_to_apb; // ------------------------------- // Master controls simulation run time initial begin : proc_axi_master - static rand_axi_lite_master_t rand_axi_lite_master = new ( master_dv , "axi_lite_mst"); + static axi_lite_rand_master_t axi_lite_rand_master = new ( master_dv , "axi_lite_mst"); end_of_sim <= 1'b0; - rand_axi_lite_master.reset(); + axi_lite_rand_master.reset(); @(posedge rst_n); - rand_axi_lite_master.run(NoReads, NoWrites); + axi_lite_rand_master.run(NoReads, NoWrites); end_of_sim <= 1'b1; end diff --git a/test/tb_axi_lite_xbar.sv b/test/tb_axi_lite_xbar.sv index f88f9fcdd..c91603e95 100644 --- a/test/tb_axi_lite_xbar.sv +++ b/test/tb_axi_lite_xbar.sv @@ -72,7 +72,7 @@ module tb_axi_lite_xbar; '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} }; - typedef axi_test::rand_axi_lite_master #( + typedef axi_test::axi_lite_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -84,7 +84,7 @@ module tb_axi_lite_xbar; .MAX_READ_TXNS ( 10 ), .MAX_WRITE_TXNS ( 10 ) ) rand_lite_master_t; - typedef axi_test::rand_axi_lite_slave #( + typedef axi_test::axi_lite_rand_slave #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), diff --git a/test/tb_axi_modify_address.sv b/test/tb_axi_modify_address.sv index 37e4c4b99..16ee50101 100644 --- a/test/tb_axi_modify_address.sv +++ b/test/tb_axi_modify_address.sv @@ -111,7 +111,7 @@ module tb_axi_modify_address #( ); // Test harness master - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( .AW (AXI_SLV_PORT_ADDR_WIDTH), .DW (AXI_DATA_WIDTH), .IW (AXI_ID_WIDTH), @@ -137,7 +137,7 @@ module tb_axi_modify_address #( end // Test harness slave - typedef axi_test::rand_axi_slave #( + typedef axi_test::axi_rand_slave #( .AW (AXI_MST_PORT_ADDR_WIDTH), .DW (AXI_DATA_WIDTH), .IW (AXI_ID_WIDTH), diff --git a/test/tb_axi_serializer.sv b/test/tb_axi_serializer.sv index 700b17ccf..a06ff54e6 100644 --- a/test/tb_axi_serializer.sv +++ b/test/tb_axi_serializer.sv @@ -35,7 +35,7 @@ module tb_axi_serializer #( // Sim print config, how many transactions localparam int unsigned PrintTxn = 500; - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -48,8 +48,8 @@ module tb_axi_serializer #( .MAX_READ_TXNS ( MaxAR ), .MAX_WRITE_TXNS ( MaxAW ), .AXI_ATOPS ( EnAtop ) - ) rand_axi_master_t; - typedef axi_test::rand_axi_slave #( + ) axi_rand_master_t; + typedef axi_test::axi_rand_slave #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -58,7 +58,7 @@ module tb_axi_serializer #( // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) rand_axi_slave_t; + ) axi_rand_slave_t; // ------------- // DUT signals @@ -125,24 +125,24 @@ module tb_axi_serializer #( ); initial begin : proc_axi_master - automatic rand_axi_master_t rand_axi_master = new(master_dv); + automatic axi_rand_master_t axi_rand_master = new(master_dv); end_of_sim <= 1'b0; - rand_axi_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); - rand_axi_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); - rand_axi_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); - rand_axi_master.reset(); + axi_rand_master.add_memory_region(32'h0000_0000, 32'h1000_0000, axi_pkg::DEVICE_NONBUFFERABLE); + axi_rand_master.add_memory_region(32'h2000_0000, 32'h3000_0000, axi_pkg::WTHRU_NOALLOCATE); + axi_rand_master.add_memory_region(32'h4000_0000, 32'h5000_0000, axi_pkg::WBACK_RWALLOCATE); + axi_rand_master.reset(); @(posedge rst_n); - rand_axi_master.run(NoReads, NoWrites); + axi_rand_master.run(NoReads, NoWrites); end_of_sim <= 1'b1; repeat (100) @(posedge clk); $stop(); end initial begin : proc_axi_slave - automatic rand_axi_slave_t rand_axi_slave = new(slave_dv); - rand_axi_slave.reset(); + automatic axi_rand_slave_t axi_rand_slave = new(slave_dv); + axi_rand_slave.reset(); @(posedge rst_n); - rand_axi_slave.run(); + axi_rand_slave.run(); end // Checker diff --git a/test/tb_axi_to_axi_lite.sv b/test/tb_axi_to_axi_lite.sv index 113d9fdd1..cd20e4702 100644 --- a/test/tb_axi_to_axi_lite.sv +++ b/test/tb_axi_to_axi_lite.sv @@ -77,7 +77,7 @@ module tb_axi_to_axi_lite; .mst ( axi_lite ) ); - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( // AXI interface parameters .AW ( AW ), .DW ( DW ), @@ -90,11 +90,11 @@ module tb_axi_to_axi_lite; .MAX_READ_TXNS ( MAX_READ_TXNS ), .MAX_WRITE_TXNS ( MAX_WRITE_TXNS ), .AXI_ATOPS ( AXI_ATOPS ) - ) rand_axi_master_t; - typedef axi_test::rand_axi_lite_slave #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) rand_axi_lite_slv_t; + ) axi_rand_master_t; + typedef axi_test::axi_lite_rand_slave #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_rand_slv_t; - rand_axi_lite_slv_t axi_lite_drv = new(axi_lite_dv, "rand_axi_lite_slave"); - rand_axi_master_t axi_drv = new(axi_dv); + axi_lite_rand_slv_t axi_lite_drv = new(axi_lite_dv, "axi_lite_rand_slave"); + axi_rand_master_t axi_drv = new(axi_dv); initial begin #tCK; diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index 780880a6f..b5c034687 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -91,7 +91,7 @@ module tb_axi_xbar; '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} }; - typedef axi_test::rand_axi_master #( + typedef axi_test::axi_rand_master #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -104,8 +104,8 @@ module tb_axi_xbar; .MAX_READ_TXNS ( 20 ), .MAX_WRITE_TXNS ( 20 ), .AXI_ATOPS ( EnAtop ) - ) rand_axi_master_t; - typedef axi_test::rand_axi_slave #( + ) axi_rand_master_t; + typedef axi_test::axi_rand_slave #( // AXI interface parameters .AW ( AxiAddrWidth ), .DW ( AxiDataWidth ), @@ -114,7 +114,7 @@ module tb_axi_xbar; // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) rand_axi_slave_t; + ) axi_rand_slave_t; // ------------- // DUT signals @@ -187,25 +187,25 @@ module tb_axi_xbar; // ------------------------------- // Masters control simulation run time for (genvar i = 0; i < NoMasters; i++) begin : gen_rand_master - static rand_axi_master_t rand_axi_master = new ( master_dv[i] ); + static axi_rand_master_t axi_rand_master = new ( master_dv[i] ); initial begin end_of_sim[i] <= 1'b0; - rand_axi_master.add_memory_region(AddrMap[0].start_addr, + axi_rand_master.add_memory_region(AddrMap[0].start_addr, AddrMap[xbar_cfg.NoAddrRules-1].end_addr, axi_pkg::DEVICE_NONBUFFERABLE); - rand_axi_master.reset(); + axi_rand_master.reset(); @(posedge rst_n); - rand_axi_master.run(NoReads, NoWrites); + axi_rand_master.run(NoReads, NoWrites); end_of_sim[i] <= 1'b1; end end for (genvar i = 0; i < NoSlaves; i++) begin : gen_rand_slave - static rand_axi_slave_t rand_axi_slave = new( slave_dv[i] ); + static axi_rand_slave_t axi_rand_slave = new( slave_dv[i] ); initial begin - rand_axi_slave.reset(); + axi_rand_slave.reset(); @(posedge rst_n); - rand_axi_slave.run(); + axi_rand_slave.run(); end end