From bf900080be69151d54db9d9c6990c23a872397eb Mon Sep 17 00:00:00 2001
From: Michael Rogenmoser <michael@rogenmoser.us>
Date: Tue, 16 Jul 2024 18:32:33 +0200
Subject: [PATCH] axi_sim_mem: add basic and multiport interface variant

Ensures backward-compatability
---
 src/axi_sim_mem.sv | 81 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/src/axi_sim_mem.sv b/src/axi_sim_mem.sv
index bdc74715c..9bf164229 100644
--- a/src/axi_sim_mem.sv
+++ b/src/axi_sim_mem.sv
@@ -352,6 +352,87 @@ endmodule
 ///
 /// See the documentation of the main module for the definition of ports and parameters.
 module axi_sim_mem_intf #(
+  parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
+  parameter int unsigned AXI_DATA_WIDTH = 32'd0,
+  parameter int unsigned AXI_ID_WIDTH = 32'd0,
+  parameter int unsigned AXI_USER_WIDTH = 32'd0,
+  parameter bit WARN_UNINITIALIZED = 1'b0,
+  parameter UNINITIALIZED_DATA = "undefined",
+  parameter bit ClearErrOnAccess = 1'b0,
+  parameter time APPL_DELAY = 0ps,
+  parameter time ACQ_DELAY = 0ps
+) (
+  input  logic                      clk_i,
+  input  logic                      rst_ni,
+  AXI_BUS.Slave                     axi_slv,
+  output logic                      mon_w_valid_o,
+  output logic [AXI_ADDR_WIDTH-1:0] mon_w_addr_o,
+  output logic [AXI_DATA_WIDTH-1:0] mon_w_data_o,
+  output logic [AXI_ID_WIDTH-1:0]   mon_w_id_o,
+  output logic [AXI_USER_WIDTH-1:0] mon_w_user_o,
+  output axi_pkg::len_t             mon_w_beat_count_o,
+  output logic                      mon_w_last_o,
+  output logic                      mon_r_valid_o,
+  output logic [AXI_ADDR_WIDTH-1:0] mon_r_addr_o,
+  output logic [AXI_DATA_WIDTH-1:0] mon_r_data_o,
+  output logic [AXI_ID_WIDTH-1:0]   mon_r_id_o,
+  output logic [AXI_USER_WIDTH-1:0] mon_r_user_o,
+  output axi_pkg::len_t             mon_r_beat_count_o,
+  output logic                      mon_r_last_o
+);
+  
+  typedef logic [AXI_ADDR_WIDTH-1:0]   axi_addr_t;
+  typedef logic [AXI_DATA_WIDTH-1:0]   axi_data_t;
+  typedef logic [AXI_ID_WIDTH-1:0]     axi_id_t;
+  typedef logic [AXI_DATA_WIDTH/8-1:0] axi_strb_t;
+  typedef logic [AXI_USER_WIDTH-1:0]   axi_user_t;
+  `AXI_TYPEDEF_ALL(axi, axi_addr_t, axi_id_t, axi_data_t, axi_strb_t, axi_user_t)
+
+  axi_req_t  axi_req;
+  axi_resp_t axi_rsp;
+
+  `AXI_ASSIGN_TO_REQ(axi_req, axi_slv)
+  `AXI_ASSIGN_FROM_RESP(axi_slv, axi_rsp)
+
+  axi_sim_mem #(
+    .AddrWidth          (AXI_ADDR_WIDTH),
+    .DataWidth          (AXI_DATA_WIDTH),
+    .IdWidth            (AXI_ID_WIDTH),
+    .UserWidth          (AXI_USER_WIDTH),
+    .axi_req_t          (axi_req_t),
+    .axi_rsp_t          (axi_resp_t),
+    .WarnUninitialized  (WARN_UNINITIALIZED),
+    .UninitializedData  (UNINITIALIZED_DATA),
+    .ClearErrOnAccess   (ClearErrOnAccess),
+    .ApplDelay          (APPL_DELAY),
+    .AcqDelay           (ACQ_DELAY)
+  ) i_sim_mem (
+    .clk_i,
+    .rst_ni,
+    .axi_req_i (axi_req),
+    .axi_rsp_o (axi_rsp),
+    .mon_w_valid_o,
+    .mon_w_addr_o,
+    .mon_w_data_o,
+    .mon_w_id_o,
+    .mon_w_user_o,
+    .mon_w_beat_count_o,
+    .mon_w_last_o,
+    .mon_r_valid_o,
+    .mon_r_addr_o,
+    .mon_r_data_o,
+    .mon_r_id_o,
+    .mon_r_user_o,
+    .mon_r_beat_count_o,
+    .mon_r_last_o
+  );
+
+endmodule
+
+/// Mutliport interface variant of [`axi_sim_mem`](module.axi_sim_mem).
+///
+/// See the documentation of the main module for the definition of ports and parameters.
+module axi_sim_mem_multiport_intf #(
   parameter int unsigned AXI_ADDR_WIDTH = 32'd0,
   parameter int unsigned AXI_DATA_WIDTH = 32'd0,
   parameter int unsigned AXI_ID_WIDTH = 32'd0,