From 025f447b3afd1645c3ce877d21aa9d877161d8f4 Mon Sep 17 00:00:00 2001 From: hossein1387 Date: Mon, 1 Aug 2022 23:10:20 -0400 Subject: [PATCH 1/8] [fusesoc] Add fusesoc core file for synthesis in Xilinx FPGAs --- ara.core | 296 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 296 insertions(+) create mode 100644 ara.core diff --git a/ara.core b/ara.core new file mode 100644 index 000000000..3bec9e65d --- /dev/null +++ b/ara.core @@ -0,0 +1,296 @@ +CAPI=2: +name : ::ara:0 +description: Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core + +filesets: + rtl: + file_type: systemVerilogSource + files: + - hardware/deps/axi/src/axi_pkg.sv + - hardware/deps/axi/src/axi_intf.sv + - hardware/deps/axi/include/axi/assign.svh: {is_include_file: true, include_path: hardware/deps/axi/include} + - hardware/deps/axi/include/axi/typedef.svh: {is_include_file: true, include_path: hardware/deps/axi/include} + - hardware/deps/axi/src/axi_xbar.sv + - hardware/deps/axi/src/axi_atop_filter.sv + - hardware/deps/axi/src/axi_dw_converter.sv + - hardware/deps/axi/src/axi_to_axi_lite.sv + - hardware/deps/axi/src/axi_lite_regs.sv + - hardware/deps/axi/src/axi_burst_splitter.sv + - hardware/deps/axi/src/axi_cut.sv + - hardware/deps/axi/src/axi_mux.sv + - hardware/deps/axi/src/axi_demux.sv + - hardware/deps/axi/src/axi_err_slv.sv + - hardware/deps/axi/src/axi_dw_upsizer.sv + - hardware/deps/axi/src/axi_cdc.sv + - hardware/deps/axi/src/axi_cdc_dst.sv + - hardware/deps/axi/src/axi_cdc_src.sv + - hardware/deps/axi/src/axi_cut.sv + - hardware/deps/axi/src/axi_delayer.sv + - hardware/deps/axi/src/axi_dw_converter.sv + - hardware/deps/axi/src/axi_id_prepend.sv + - hardware/deps/axi/src/axi_isolate.sv + - hardware/deps/axi/src/axi_join.sv + - hardware/deps/axi/src/axi_lite_demux.sv + - hardware/deps/axi/src/axi_lite_join.sv + - hardware/deps/axi/src/axi_lite_mailbox.sv + - hardware/deps/axi/src/axi_lite_mux.sv + - hardware/deps/axi/src/axi_lite_to_apb.sv + - hardware/deps/axi/src/axi_lite_to_axi.sv + - hardware/deps/axi/src/axi_lite_xbar.sv + - hardware/deps/axi/src/axi_modify_address.sv + - hardware/deps/axi/src/axi_multicut.sv + - hardware/deps/axi/src/axi_serializer.sv + - hardware/deps/axi/src/axi_sim_mem.sv + - hardware/deps/axi/src/axi_dw_downsizer.sv + + - hardware/deps/cva6/include/riscv_pkg.sv + - hardware/deps/cva6/include/instr_tracer_pkg.sv + + - hardware/deps/cva6/src/riscv-dbg/src/dm_pkg.sv + - hardware/deps/cva6/src/fpu/src/fpnew_pkg.sv + - hardware/deps/cva6/include/ariane_pkg.sv + - hardware/deps/cva6/include/std_cache_pkg.sv + - hardware/deps/cva6/include/wt_cache_pkg.sv + - hardware/deps/cva6/src/register_interface/src/reg_intf.sv + - hardware/deps/cva6/src/register_interface/src/reg_intf_pkg.sv + - hardware/deps/cva6/include/ariane_axi_pkg.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv + - hardware/deps/cva6/src/ariane.sv + - hardware/deps/cva6/src/serdiv.sv + - hardware/deps/cva6/src/ariane_regfile_ff.sv + - hardware/deps/cva6/src/amo_buffer.sv + - hardware/deps/cva6/src/id_stage.sv + - hardware/deps/cva6/src/branch_unit.sv + - hardware/deps/cva6/src/instr_realign.sv + - hardware/deps/cva6/src/load_store_unit.sv + - hardware/deps/cva6/src/controller.sv + - hardware/deps/cva6/src/issue_stage.sv + - hardware/deps/cva6/src/re_name.sv + - hardware/deps/cva6/src/csr_buffer.sv + - hardware/deps/cva6/src/tlb.sv + - hardware/deps/cva6/src/decoder.sv + - hardware/deps/cva6/src/scoreboard.sv + - hardware/deps/cva6/src/perf_counters.sv + - hardware/deps/cva6/src/store_unit.sv + - hardware/deps/cva6/src/axi_adapter.sv + - hardware/deps/cva6/src/fpu_wrap.sv + - hardware/deps/cva6/src/csr_regfile.sv + - hardware/deps/cva6/src/commit_stage.sv + - hardware/deps/cva6/src/alu.sv + - hardware/deps/cva6/src/multiplier.sv + - hardware/deps/cva6/src/store_buffer.sv + - hardware/deps/cva6/src/compressed_decoder.sv + - hardware/deps/cva6/src/axi_shim.sv + - hardware/deps/cva6/src/ex_stage.sv + - hardware/deps/cva6/src/mmu.sv + - hardware/deps/cva6/src/ptw.sv + - hardware/deps/cva6/src/mult.sv + - hardware/deps/cva6/src/load_unit.sv + - hardware/deps/cva6/src/issue_read_operands.sv + - hardware/deps/cva6/src/acc_dispatcher.sv + - hardware/deps/cva6/src/pmp/src/pmp_entry.sv + - hardware/deps/cva6/src/pmp/src/pmp.sv + - hardware/deps/cva6/src/fpu/src/fpnew_fma.sv + - hardware/deps/cva6/src/fpu/src/fpnew_opgroup_fmt_slice.sv + - hardware/deps/cva6/src/fpu/src/fpnew_divsqrt_multi.sv + - hardware/deps/cva6/src/fpu/src/fpnew_fma_multi.sv + - hardware/deps/cva6/src/fpu/src/fpnew_opgroup_multifmt_slice.sv + - hardware/deps/cva6/src/fpu/src/fpnew_classifier.sv + - hardware/deps/cva6/src/fpu/src/fpnew_noncomp.sv + - hardware/deps/cva6/src/fpu/src/fpnew_cast_multi.sv + - hardware/deps/cva6/src/fpu/src/fpnew_opgroup_block.sv + - hardware/deps/cva6/src/fpu/src/fpnew_rounding.sv + - hardware/deps/cva6/src/fpu/src/fpnew_top.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv + - hardware/deps/cva6/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv + - hardware/deps/cva6/src/frontend/frontend.sv + - hardware/deps/cva6/src/frontend/instr_scan.sv + - hardware/deps/cva6/src/frontend/instr_queue.sv + - hardware/deps/cva6/src/frontend/bht.sv + - hardware/deps/cva6/src/frontend/btb.sv + - hardware/deps/cva6/src/frontend/ras.sv + - hardware/deps/cva6/src/cache_subsystem/tag_cmp.sv + - hardware/deps/cva6/src/cache_subsystem/cache_ctrl.sv + - hardware/deps/cva6/src/cache_subsystem/amo_alu.sv + - hardware/deps/cva6/src/cache_subsystem/wt_axi_adapter.sv + - hardware/deps/cva6/src/cache_subsystem/wt_dcache_ctrl.sv + - hardware/deps/cva6/src/cache_subsystem/wt_cache_subsystem.sv + - hardware/deps/cva6/src/cache_subsystem/wt_dcache_missunit.sv + - hardware/deps/cva6/src/cache_subsystem/cva6_icache.sv + - hardware/deps/cva6/src/cache_subsystem/wt_dcache_wbuffer.sv + - hardware/deps/cva6/src/cache_subsystem/wt_l15_adapter.sv + - hardware/deps/cva6/src/cache_subsystem/wt_dcache_mem.sv + - hardware/deps/cva6/src/cache_subsystem/cva6_icache_axi_wrapper.sv + - hardware/deps/cva6/src/cache_subsystem/std_cache_subsystem.sv + - hardware/deps/cva6/src/cache_subsystem/wt_dcache.sv + - hardware/deps/cva6/src/cache_subsystem/std_nbdcache.sv + - hardware/deps/cva6/src/cache_subsystem/miss_handler.sv + - hardware/deps/cva6/src/clint/axi_lite_interface.sv + - hardware/deps/cva6/src/clint/clint.sv + - hardware/deps/cva6/fpga/src/axi2apb/src/axi2apb_wrap.sv + - hardware/deps/cva6/fpga/src/axi2apb/src/axi2apb.sv + - hardware/deps/cva6/fpga/src/axi2apb/src/axi2apb_64_32.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_w_buffer.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_b_buffer.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_slice_wrap.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_slice.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_single_slice.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_ar_buffer.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_r_buffer.sv + - hardware/deps/cva6/fpga/src/axi_slice/src/axi_aw_buffer.sv + - hardware/deps/cva6/fpga/src/apb_timer/apb_timer.sv + - hardware/deps/cva6/fpga/src/apb_timer/timer.sv + - hardware/deps/cva6/src/axi_node/src/axi_regs_top.sv + - hardware/deps/cva6/src/axi_node/src/axi_BR_allocator.sv + - hardware/deps/cva6/src/axi_node/src/axi_BW_allocator.sv + - hardware/deps/cva6/src/axi_node/src/axi_address_decoder_BR.sv + - hardware/deps/cva6/src/axi_node/src/axi_DW_allocator.sv + - hardware/deps/cva6/src/axi_node/src/axi_address_decoder_BW.sv + - hardware/deps/cva6/src/axi_node/src/axi_address_decoder_DW.sv + - hardware/deps/cva6/src/axi_node/src/axi_node_arbiter.sv + - hardware/deps/cva6/src/axi_node/src/axi_response_block.sv + - hardware/deps/cva6/src/axi_node/src/axi_request_block.sv + - hardware/deps/cva6/src/axi_node/src/axi_AR_allocator.sv + - hardware/deps/cva6/src/axi_node/src/axi_AW_allocator.sv + - hardware/deps/cva6/src/axi_node/src/axi_address_decoder_AR.sv + - hardware/deps/cva6/src/axi_node/src/axi_address_decoder_AW.sv + - hardware/deps/cva6/src/axi_node/src/apb_regs_top.sv + - hardware/deps/cva6/src/axi_node/src/axi_node_intf_wrap.sv + - hardware/deps/cva6/src/axi_node/src/axi_node.sv + - hardware/deps/cva6/src/axi_node/src/axi_node_wrap_with_slices.sv + - hardware/deps/cva6/src/axi_node/src/axi_multiplexer.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_amos.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_atomics.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_res_tbl.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv + - hardware/deps/cva6/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv + - hardware/deps/cva6/src/axi_mem_if/src/axi2mem.sv + - hardware/deps/cva6/src/rv_plic/rtl/rv_plic_target.sv + - hardware/deps/cva6/src/rv_plic/rtl/rv_plic_gateway.sv + - hardware/deps/cva6/src/rv_plic/rtl/plic_regmap.sv + - hardware/deps/cva6/src/rv_plic/rtl/plic_top.sv + - hardware/deps/cva6/src/riscv-dbg/src/dmi_cdc.sv + - hardware/deps/cva6/src/riscv-dbg/src/dmi_jtag.sv + - hardware/deps/cva6/src/riscv-dbg/src/dmi_jtag_tap.sv + - hardware/deps/cva6/src/riscv-dbg/src/dm_csrs.sv + - hardware/deps/cva6/src/riscv-dbg/src/dm_mem.sv + - hardware/deps/cva6/src/riscv-dbg/src/dm_sba.sv + - hardware/deps/cva6/src/riscv-dbg/src/dm_top.sv + - hardware/deps/cva6/src/riscv-dbg/debug_rom/debug_rom.sv + - hardware/deps/cva6/src/register_interface/src/apb_to_reg.sv + - hardware/deps/cva6/src/common_cells/src/deprecated/generic_fifo.sv + - hardware/deps/cva6/src/common_cells/src/deprecated/pulp_sync.sv + - hardware/deps/cva6/src/common_cells/src/deprecated/find_first_one.sv + - hardware/deps/cva6/src/common_cells/src/rstgen_bypass.sv + - hardware/deps/cva6/src/common_cells/src/rstgen.sv + - hardware/deps/cva6/src/common_cells/src/stream_mux.sv + - hardware/deps/cva6/src/common_cells/src/stream_demux.sv + - hardware/deps/cva6/src/common_cells/src/stream_arbiter.sv + - hardware/deps/cva6/src/common_cells/src/stream_arbiter_flushable.sv + - hardware/deps/cva6/src/util/axi_master_connect.sv + - hardware/deps/cva6/src/util/axi_slave_connect.sv + - hardware/deps/cva6/src/util/axi_master_connect_rev.sv + - hardware/deps/cva6/src/util/axi_slave_connect_rev.sv + - hardware/deps/cva6/src/util/instr_tracer_if.sv + - hardware/deps/cva6/src/fpga-support/rtl/SyncSpRamBeNx64.sv + - hardware/deps/cva6/src/common_cells/src/popcount.sv + - hardware/deps/cva6/src/common_cells/src/unread.sv + - hardware/deps/cva6/src/common_cells/src/cdc_2phase.sv + - hardware/deps/cva6/src/common_cells/src/spill_register.sv + - hardware/deps/cva6/src/common_cells/src/edge_detect.sv + - hardware/deps/cva6/src/common_cells/src/fifo_v3.sv + - hardware/deps/cva6/src/common_cells/src/deprecated/fifo_v2.sv + - hardware/deps/cva6/src/common_cells/src/deprecated/fifo_v1.sv + - hardware/deps/cva6/src/common_cells/src/lzc.sv + - hardware/deps/cva6/src/common_cells/src/rr_arb_tree.sv + - hardware/deps/cva6/src/common_cells/src/deprecated/rrarbiter.sv + - hardware/deps/cva6/src/common_cells/src/stream_delay.sv + - hardware/deps/cva6/src/common_cells/src/lfsr.sv + - hardware/deps/cva6/src/common_cells/src/lfsr_8bit.sv + - hardware/deps/cva6/src/common_cells/src/lfsr_16bit.sv + - hardware/deps/cva6/src/common_cells/src/counter.sv + - hardware/deps/cva6/src/common_cells/src/shift_reg.sv + - hardware/deps/cva6/src/common_cells/src/exp_backoff.sv + - hardware/deps/cva6/src/tech_cells_generic/src/cluster_clock_inverter.sv + - hardware/deps/cva6/src/tech_cells_generic/src/pulp_clock_mux2.sv + - hardware/deps/cva6/src/util/sram.sv + - hardware/deps/cva6/src/util/instr_tracer.sv + - hardware/deps/cva6/src/util/ex_trace_item.svh: {is_include_file: true} + - hardware/deps/cva6/src/util/instr_trace_item.svh: {is_include_file: true} + + - hardware/include/ara/ara.svh: {is_include_file: true, include_path: hardware/include} + - hardware/include/rvv_pkg.sv + - hardware/include/ara_pkg.sv + - hardware/src/axi_to_mem.sv + - hardware/src/ctrl_registers.sv + - hardware/src/cva6_accel_first_pass_decoder.sv + - hardware/src/ara_dispatcher.sv + - hardware/src/ara_sequencer.sv + - hardware/src/axi_inval_filter.sv + - hardware/src/lane/lane_sequencer.sv + - hardware/src/lane/operand_queue.sv + - hardware/src/lane/operand_requester.sv + - hardware/src/lane/simd_alu.sv + - hardware/src/lane/simd_div.sv + - hardware/src/lane/simd_mul.sv + - hardware/src/lane/vector_regfile.sv + - hardware/src/masku/masku.sv + - hardware/src/sldu/sldu.sv + - hardware/src/vlsu/addrgen.sv + - hardware/src/vlsu/vldu.sv + - hardware/src/vlsu/vstu.sv + - hardware/src/lane/operand_queues_stage.sv + - hardware/src/lane/valu.sv + - hardware/src/lane/vmfpu.sv + - hardware/src/vlsu/vlsu.sv + - hardware/src/lane/vector_fus_stage.sv + - hardware/src/lane/lane.sv + - hardware/src/ara.sv + - hardware/src/ara_system.sv + - hardware/src/ara_soc.sv + depend: + - pulp-platform.org::common_cells + + behav_sram: + file_type : systemVerilogSource + files: + - hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv + xilinx_sram: + file_type : systemVerilogSource + files: + - hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv + + svtb: + file_type: systemVerilogSource + files: + - hardware/tb/ara_testharness.sv + - hardware/tb/ara_tb.sv + - hardware/deps/cva6/tb/common/mock_uart.sv + + verilator_tb: + files: + - hardware/tb/ara_testharness.sv + - hardware/tb/ara_tb_verilator.sv +targets: + xsim: + default_tool: xsim + filesets: [behav_sram, rtl, svtb] + description: Simulate the design + tools: + xsim: + xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, --timescale, 1ns/1ps, --define, NR_LANES=4, --define, RVV_ARIANE=1, --define, TARGET_ARA_TEST, --define, TARGET_ASIC, --define, TARGET_CVA6_TEST, --define, TARGET_RTL, --define, TARGET_SIMULATION, --define, TARGET_VSIM, --define, VLEN=4096, --define, WT_DCACHE=1] + parameters: [PRELOAD] + toplevel: [ara_tb] +parameters: + PRELOAD: + datatype : file + default : apps/bin/helloworld_2 + paramtype : plusarg + From 98923e1a0054455d61e3844ac8887db9d03d0e30 Mon Sep 17 00:00:00 2001 From: hossein1387 Date: Tue, 16 Aug 2022 00:31:25 -0400 Subject: [PATCH 2/8] [hardware] Add building blocks for FPGA implementation of Ara --- .gitmodules | 3 + ara.core | 40 ++++++++++++- fpga/constraints/ara.xdc | 1 + fpga/scripts/run.tcl | 4 ++ fpga/scripts/xpm_rams.tcl | 1 + fpga/src/clk_gen.sv | 44 ++++++++++++++ fpga/src/xcvu9p.svh | 23 ++++++++ fpga/src/xilinx_ara_soc.sv | 117 +++++++++++++++++++++++++++++++++++++ hardware/deps/apb_uart | 1 + 9 files changed, 233 insertions(+), 1 deletion(-) create mode 100644 fpga/constraints/ara.xdc create mode 100644 fpga/scripts/run.tcl create mode 100644 fpga/scripts/xpm_rams.tcl create mode 100644 fpga/src/clk_gen.sv create mode 100644 fpga/src/xcvu9p.svh create mode 100644 fpga/src/xilinx_ara_soc.sv create mode 160000 hardware/deps/apb_uart diff --git a/.gitmodules b/.gitmodules index f7d26db14..8ac9a38f4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -32,3 +32,6 @@ path = toolchain/riscv-llvm url = https://github.com/llvm/llvm-project.git ignore = dirty +[submodule "hardware/deps/apb_uart"] + path = hardware/deps/apb_uart + url = https://github.com/pulp-platform/apb_uart.git diff --git a/ara.core b/ara.core index 3bec9e65d..fbde59769 100644 --- a/ara.core +++ b/ara.core @@ -6,6 +6,7 @@ filesets: rtl: file_type: systemVerilogSource files: + - fpga/src/xcvu9p.svh - hardware/deps/axi/src/axi_pkg.sv - hardware/deps/axi/src/axi_intf.sv - hardware/deps/axi/include/axi/assign.svh: {is_include_file: true, include_path: hardware/deps/axi/include} @@ -224,6 +225,20 @@ filesets: - hardware/deps/cva6/src/util/instr_tracer.sv - hardware/deps/cva6/src/util/ex_trace_item.svh: {is_include_file: true} - hardware/deps/cva6/src/util/instr_trace_item.svh: {is_include_file: true} + + - hardware/deps/apb_uart/src/slib_clock_div.sv + - hardware/deps/apb_uart/src/slib_counter.sv + - hardware/deps/apb_uart/src/slib_edge_detect.sv + - hardware/deps/apb_uart/src/slib_fifo.sv + - hardware/deps/apb_uart/src/slib_input_filter.sv + - hardware/deps/apb_uart/src/slib_input_sync.sv + - hardware/deps/apb_uart/src/slib_mv_filter.sv + - hardware/deps/apb_uart/src/uart_baudgen.sv + - hardware/deps/apb_uart/src/uart_interrupt.sv + - hardware/deps/apb_uart/src/uart_receiver.sv + - hardware/deps/apb_uart/src/uart_transmitter.sv + - hardware/deps/apb_uart/src/apb_uart.sv + - hardware/deps/apb_uart/src/apb_uart_wrap.sv - hardware/include/ara/ara.svh: {is_include_file: true, include_path: hardware/include} - hardware/include/rvv_pkg.sv @@ -265,7 +280,16 @@ filesets: xilinx_sram: file_type : systemVerilogSource files: - - hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv + - fpga/scripts/xpm_rams.tcl: {file_type: tclSource} + - hardware/deps/tech_cells_generic/src/fpga/tc_sram_xilinx.sv: {file_type : systemVerilogSource} + xilinx_synth: + files: + - fpga/scripts/run.tcl: {file_type: tclSource} + + xcvu9p: + files: + - fpga/constraints/ara.xdc: {file_type: xdc} + - fpga/src/xilinx_ara_soc.sv: {file_type : systemVerilogSource} svtb: file_type: systemVerilogSource @@ -275,9 +299,11 @@ filesets: - hardware/deps/cva6/tb/common/mock_uart.sv verilator_tb: + file_type: systemVerilogSource files: - hardware/tb/ara_testharness.sv - hardware/tb/ara_tb_verilator.sv + targets: xsim: default_tool: xsim @@ -288,6 +314,18 @@ targets: xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, --timescale, 1ns/1ps, --define, NR_LANES=4, --define, RVV_ARIANE=1, --define, TARGET_ARA_TEST, --define, TARGET_ASIC, --define, TARGET_CVA6_TEST, --define, TARGET_RTL, --define, TARGET_SIMULATION, --define, TARGET_VSIM, --define, VLEN=4096, --define, WT_DCACHE=1] parameters: [PRELOAD] toplevel: [ara_tb] + synth: + description: Synthesize the design for an FPGA board + filesets: + - xilinx_sram + - rtl + - xilinx_synth + - xcvu9p + default_tool: vivado + tools: + vivado: + part: xcvu9p-flgb2104-2-e + toplevel: [xilinx_ara_soc] parameters: PRELOAD: datatype : file diff --git a/fpga/constraints/ara.xdc b/fpga/constraints/ara.xdc new file mode 100644 index 000000000..ede7f7b77 --- /dev/null +++ b/fpga/constraints/ara.xdc @@ -0,0 +1 @@ +create_clock -period 10.000 -name clk_i [get_ports clk_i] \ No newline at end of file diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl new file mode 100644 index 000000000..72f3da81a --- /dev/null +++ b/fpga/scripts/run.tcl @@ -0,0 +1,4 @@ +# read_verilog -sv {../src/ara_0/fpga/src/xcvu9p.svh } +# set file "../src/ara_0/fpga/src/xcvu9p.svh" + +set_property is_global_include true [get_files xcvu9p.svh] \ No newline at end of file diff --git a/fpga/scripts/xpm_rams.tcl b/fpga/scripts/xpm_rams.tcl new file mode 100644 index 000000000..8e069ad97 --- /dev/null +++ b/fpga/scripts/xpm_rams.tcl @@ -0,0 +1 @@ +set_property XPM_LIBRARIES XPM_MEMORY [current_project] diff --git a/fpga/src/clk_gen.sv b/fpga/src/clk_gen.sv new file mode 100644 index 000000000..41f3f3936 --- /dev/null +++ b/fpga/src/clk_gen.sv @@ -0,0 +1,44 @@ +`default_nettype none +module vcu9p_clock_gen + (input wire i_clk, + output wire o_clk, + output reg o_rst); + + wire clkfb; + wire locked; + reg locked_r; + + MMCME4_ADV + #(.DIVCLK_DIVIDE (5), + .CLKFBOUT_MULT_F (48.000), + .CLKOUT0_DIVIDE_F (75.0), + .CLKIN1_PERIOD (8.0), //125MHz + .STARTUP_WAIT ("FALSE")) + mmcm + (.CLKFBOUT (clkfb), + .CLKFBOUTB (), + .CLKOUT0 (o_clk), + .CLKOUT0B (), + .CLKOUT1 (), + .CLKOUT1B (), + .CLKOUT2 (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN1 (i_clk), + .CLKIN2 (1'b0), + .CLKINSEL (1'b1), + .LOCKED (locked), + .PWRDWN (1'b0), + .RST (1'b0), + .CLKFBIN (clkfb)); + + always @(posedge o_clk) begin + locked_r <= locked; + o_rst <= !locked_r; + end + +endmodule \ No newline at end of file diff --git a/fpga/src/xcvu9p.svh b/fpga/src/xcvu9p.svh new file mode 100644 index 000000000..3f67e97d1 --- /dev/null +++ b/fpga/src/xcvu9p.svh @@ -0,0 +1,23 @@ +// Description: Set global FPGA degines +// Author: MohammadHossein AskariHemmat m.h.askari.hemmat@gmail.com + +`define xcvu9p + +//============================================================================= +// CVA6 Configurations +//============================================================================= +`define ARIANE_DATA_WIDTH 64 +// Instantiate protocl checker +// `define PROTOCOL_CHECKER +// write-back cache +// `define WB_DCACHE +// write-through cache +`define WT_DCACHE 1 + +`define RVV_ARIANE 1 + +//============================================================================= +// Ara Configurations +//============================================================================= +`define NrLanes 4 +`define VLEN 4096 diff --git a/fpga/src/xilinx_ara_soc.sv b/fpga/src/xilinx_ara_soc.sv new file mode 100644 index 000000000..83153cb72 --- /dev/null +++ b/fpga/src/xilinx_ara_soc.sv @@ -0,0 +1,117 @@ +// Copyright 2022 ETH Zurich and University of Bologna and Polytechnique Montreal. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: MohammadHossein AskariHemmat +// Description: +// Ara's FPGA based SoC, containing: +// - ara_soc: +// - ara +// - L2 Cache +// - cva6/ariane +// - peripherals: +// - uart (wip) +// - jtag (wip) + +module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #( + // RVV Parameters + parameter int unsigned NrLanes = 4, // Number of parallel vector lanes. + // Support for floating-point data types + parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble, + // AXI Interface + parameter int unsigned AxiDataWidth = 32*NrLanes, + parameter int unsigned AxiAddrWidth = 64, + parameter int unsigned AxiUserWidth = 1, + parameter int unsigned AxiIdWidth = 5, + // Main memory + parameter int unsigned L2NumWords = 2**14, + // Dependant parameters. DO NOT CHANGE! + localparam type axi_data_t = logic [AxiDataWidth-1:0], + localparam type axi_strb_t = logic [AxiDataWidth/8-1:0], + localparam type axi_addr_t = logic [AxiAddrWidth-1:0], + localparam type axi_user_t = logic [AxiUserWidth-1:0], + localparam type axi_id_t = logic [AxiIdWidth-1:0] + ) ( + input logic clk_i, + input logic rst_ni, + output logic [63:0] exit_o, + // Scan chain + // UART + input logic rx_i , + output logic tx_o + ); + + + /************* + * Signals * + *************/ + + // UART + logic uart_penable; + logic uart_pwrite; + logic [31:0] uart_paddr; + logic uart_psel; + logic [31:0] uart_pwdata; + logic [31:0] uart_prdata; + logic uart_pready; + logic uart_pslverr; + + ////////////////////// + // Ara SoC // + ////////////////////// + + ara_soc #( + .NrLanes (NrLanes ), + .AxiAddrWidth(AxiAddrWidth ), + .AxiDataWidth(AxiDataWidth ), + .AxiIdWidth (AxiIdWidth ), + .AxiUserWidth(AxiUserWidth ) + ) i_ara_soc ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .exit_o (exit_o ), + .scan_enable_i (1'b0 ), + .scan_data_i (1'b0 ), + .scan_data_o (/* Unused */), + // UART + .uart_penable_o(uart_penable), + .uart_pwrite_o (uart_pwrite ), + .uart_paddr_o (uart_paddr ), + .uart_psel_o (uart_psel ), + .uart_pwdata_o (uart_pwdata ), + .uart_prdata_i (uart_prdata ), + .uart_pready_i (uart_pready ), + .uart_pslverr_i(uart_pslverr) + ); + ////////////////////// + // Peripherals // + ////////////////////// + + ////////////////////// + // UART // + ////////////////////// + apb_uart i_apb_uart ( + .CLK ( clk_i ), + .RSTN ( rst_ni ), + .PSEL ( uart_psel ), + .PENABLE ( uart_penable ), + .PWRITE ( uart_pwrite ), + .PADDR ( uart_paddr[4:2] ), + .PWDATA ( uart_pwdata ), + .PRDATA ( uart_prdata ), + .PREADY ( uart_pready ), + .PSLVERR ( uart_pslverr ), + .INT ( ), // no interrupts + .OUT1N ( ), // keep open + .OUT2N ( ), // keep open + .RTSN ( ), // no flow control + .DTRN ( ), // no flow control + .CTSN ( 1'b0 ), + .DSRN ( 1'b0 ), + .DCDN ( 1'b0 ), + .RIN ( 1'b0 ), + .SIN ( rx_i ), + .SOUT ( tx_o ) +); + +endmodule : xilinx_ara_soc diff --git a/hardware/deps/apb_uart b/hardware/deps/apb_uart new file mode 160000 index 000000000..b6145341d --- /dev/null +++ b/hardware/deps/apb_uart @@ -0,0 +1 @@ +Subproject commit b6145341df79137ac584c83e9c081f80a7a40440 From 40643e290731487d599b1b8dcb58cb4fdb204d00 Mon Sep 17 00:00:00 2001 From: hossein1387 Date: Tue, 16 Aug 2022 00:57:50 -0400 Subject: [PATCH 3/8] [hardware] Set ara's cache size from top level --- fpga/src/xilinx_ara_soc.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fpga/src/xilinx_ara_soc.sv b/fpga/src/xilinx_ara_soc.sv index 83153cb72..302f70575 100644 --- a/fpga/src/xilinx_ara_soc.sv +++ b/fpga/src/xilinx_ara_soc.sv @@ -65,7 +65,8 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #( .AxiAddrWidth(AxiAddrWidth ), .AxiDataWidth(AxiDataWidth ), .AxiIdWidth (AxiIdWidth ), - .AxiUserWidth(AxiUserWidth ) + .AxiUserWidth(AxiUserWidth ), + .L2NumWords (L2NumWords ) ) i_ara_soc ( .clk_i (clk_i ), .rst_ni (rst_ni ), From 0b673e6f7ddc2993b7064f91c155570958b652c0 Mon Sep 17 00:00:00 2001 From: hossein1387 Date: Mon, 19 Sep 2022 20:23:45 -0400 Subject: [PATCH 4/8] [fpga] :art: Remove trailing white spaces --- ara.core | 8 ++------ fpga/src/xilinx_ara_soc.sv | 18 +++++++++--------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/ara.core b/ara.core index fbde59769..d48e532e2 100644 --- a/ara.core +++ b/ara.core @@ -43,10 +43,8 @@ filesets: - hardware/deps/axi/src/axi_serializer.sv - hardware/deps/axi/src/axi_sim_mem.sv - hardware/deps/axi/src/axi_dw_downsizer.sv - - hardware/deps/cva6/include/riscv_pkg.sv - hardware/deps/cva6/include/instr_tracer_pkg.sv - - hardware/deps/cva6/src/riscv-dbg/src/dm_pkg.sv - hardware/deps/cva6/src/fpu/src/fpnew_pkg.sv - hardware/deps/cva6/include/ariane_pkg.sv @@ -225,7 +223,6 @@ filesets: - hardware/deps/cva6/src/util/instr_tracer.sv - hardware/deps/cva6/src/util/ex_trace_item.svh: {is_include_file: true} - hardware/deps/cva6/src/util/instr_trace_item.svh: {is_include_file: true} - - hardware/deps/apb_uart/src/slib_clock_div.sv - hardware/deps/apb_uart/src/slib_counter.sv - hardware/deps/apb_uart/src/slib_edge_detect.sv @@ -306,10 +303,10 @@ filesets: targets: xsim: - default_tool: xsim + default_tool: xsim filesets: [behav_sram, rtl, svtb] description: Simulate the design - tools: + tools: xsim: xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, --timescale, 1ns/1ps, --define, NR_LANES=4, --define, RVV_ARIANE=1, --define, TARGET_ARA_TEST, --define, TARGET_ASIC, --define, TARGET_CVA6_TEST, --define, TARGET_RTL, --define, TARGET_SIMULATION, --define, TARGET_VSIM, --define, VLEN=4096, --define, WT_DCACHE=1] parameters: [PRELOAD] @@ -331,4 +328,3 @@ parameters: datatype : file default : apps/bin/helloworld_2 paramtype : plusarg - diff --git a/fpga/src/xilinx_ara_soc.sv b/fpga/src/xilinx_ara_soc.sv index 302f70575..a0394cc99 100644 --- a/fpga/src/xilinx_ara_soc.sv +++ b/fpga/src/xilinx_ara_soc.sv @@ -14,8 +14,8 @@ // - jtag (wip) module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #( - // RVV Parameters - parameter int unsigned NrLanes = 4, // Number of parallel vector lanes. + // Number of parallel vector lanes. + parameter int unsigned NrLanes = 4, // Support for floating-point data types parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble, // AXI Interface @@ -37,8 +37,8 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #( output logic [63:0] exit_o, // Scan chain // UART - input logic rx_i , - output logic tx_o + input logic rx_i, + output logic tx_o ); @@ -102,11 +102,11 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #( .PRDATA ( uart_prdata ), .PREADY ( uart_pready ), .PSLVERR ( uart_pslverr ), - .INT ( ), // no interrupts - .OUT1N ( ), // keep open - .OUT2N ( ), // keep open - .RTSN ( ), // no flow control - .DTRN ( ), // no flow control + .INT ( ), + .OUT1N ( ), + .OUT2N ( ), + .RTSN ( ), + .DTRN ( ), .CTSN ( 1'b0 ), .DSRN ( 1'b0 ), .DCDN ( 1'b0 ), From 4ba9831191cfc79aee466edb79d5dd31c7be3f8b Mon Sep 17 00:00:00 2001 From: Elisabeth Humblet Date: Mon, 27 Feb 2023 09:28:05 -0500 Subject: [PATCH 5/8] update gitignore --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 06de2157d..d6dfc6519 100644 --- a/.gitignore +++ b/.gitignore @@ -34,3 +34,5 @@ install pyenv_ara/ docs/build/ docs/source/_templates/ +*.jou +fusesoc.conf From 0b1e3fdc19e63ce207bf72618aa0dd725ae65e1e Mon Sep 17 00:00:00 2001 From: Elisabeth Humblet Date: Tue, 28 Feb 2023 17:47:29 -0500 Subject: [PATCH 6/8] [fusesoc] :ok_hand update Ara lane files --- ara.core | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ara.core b/ara.core index d48e532e2..452d790a8 100644 --- a/ara.core +++ b/ara.core @@ -261,6 +261,8 @@ filesets: - hardware/src/lane/operand_queues_stage.sv - hardware/src/lane/valu.sv - hardware/src/lane/vmfpu.sv + - hardware/src/lane/fixed_p_rounding.sv + - hardware/src/lane/power_gating_generic.sv - hardware/src/vlsu/vlsu.sv - hardware/src/lane/vector_fus_stage.sv - hardware/src/lane/lane.sv From f2351e6b5fc63a79b213807725e7b09cf0193bf2 Mon Sep 17 00:00:00 2001 From: Elisabeth Humblet Date: Mon, 27 Mar 2023 10:54:16 -0400 Subject: [PATCH 7/8] [fpga] :ok_hand: Add Alveo U280 board and change config --- ara.core | 26 ++++++++++++++++++++++---- fpga/constraints/ara.xdc | 2 +- fpga/scripts/run.tcl | 3 ++- fpga/src/xcu280.svh | 23 +++++++++++++++++++++++ fpga/src/xilinx_ara_soc.sv | 2 +- 5 files changed, 49 insertions(+), 7 deletions(-) create mode 100644 fpga/src/xcu280.svh diff --git a/ara.core b/ara.core index 452d790a8..ce7f7bddd 100644 --- a/ara.core +++ b/ara.core @@ -7,6 +7,7 @@ filesets: file_type: systemVerilogSource files: - fpga/src/xcvu9p.svh + - fpga/src/xcu280.svh - hardware/deps/axi/src/axi_pkg.sv - hardware/deps/axi/src/axi_intf.sv - hardware/deps/axi/include/axi/assign.svh: {is_include_file: true, include_path: hardware/deps/axi/include} @@ -288,7 +289,12 @@ filesets: xcvu9p: files: - fpga/constraints/ara.xdc: {file_type: xdc} - - fpga/src/xilinx_ara_soc.sv: {file_type : systemVerilogSource} + - fpga/src/xilinx_ara_soc.sv: {file_type: systemVerilogSource} + + xcu280: + files: + - fpga/constraints/ara.xdc: {file_type: xdc} + - fpga/src/xilinx_ara_soc.sv: {file_type: systemVerilogSource} svtb: file_type: systemVerilogSource @@ -313,18 +319,30 @@ targets: xelab_options: [--debug, typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, --timescale, 1ns/1ps, --define, NR_LANES=4, --define, RVV_ARIANE=1, --define, TARGET_ARA_TEST, --define, TARGET_ASIC, --define, TARGET_CVA6_TEST, --define, TARGET_RTL, --define, TARGET_SIMULATION, --define, TARGET_VSIM, --define, VLEN=4096, --define, WT_DCACHE=1] parameters: [PRELOAD] toplevel: [ara_tb] - synth: + synth: &synth description: Synthesize the design for an FPGA board filesets: - xilinx_sram - rtl - xilinx_synth - - xcvu9p default_tool: vivado + toplevel: [xilinx_ara_soc] + synth-xcvu9p: + <<: *synth + description: Synthesize the design for an FPGA board + filesets_append: + - xcvu9p tools: vivado: part: xcvu9p-flgb2104-2-e - toplevel: [xilinx_ara_soc] + synth-xcu280: + <<: *synth + description: Synthesize the design for an FPGA board + filesets_append: + - xcu280 + tools: + vivado: + part: xcu280-fsvh2892-2l-e parameters: PRELOAD: datatype : file diff --git a/fpga/constraints/ara.xdc b/fpga/constraints/ara.xdc index ede7f7b77..64c2a9473 100644 --- a/fpga/constraints/ara.xdc +++ b/fpga/constraints/ara.xdc @@ -1 +1 @@ -create_clock -period 10.000 -name clk_i [get_ports clk_i] \ No newline at end of file +create_clock -period 13.334 -name clk_i [get_ports clk_i] diff --git a/fpga/scripts/run.tcl b/fpga/scripts/run.tcl index 72f3da81a..92e2fc836 100644 --- a/fpga/scripts/run.tcl +++ b/fpga/scripts/run.tcl @@ -1,4 +1,5 @@ # read_verilog -sv {../src/ara_0/fpga/src/xcvu9p.svh } # set file "../src/ara_0/fpga/src/xcvu9p.svh" -set_property is_global_include true [get_files xcvu9p.svh] \ No newline at end of file +set_property is_global_include true [get_files xcvu9p.svh] +set_property is_global_include true [get_files xcu280.svh] diff --git a/fpga/src/xcu280.svh b/fpga/src/xcu280.svh new file mode 100644 index 000000000..df3e35b01 --- /dev/null +++ b/fpga/src/xcu280.svh @@ -0,0 +1,23 @@ +// Description: Set global FPGA degines +// Author: Elisabeth Humblet elisabeth.humblet@polymtl.ca + +`define xcu280 + +//============================================================================= +// CVA6 Configurations +//============================================================================= +`define ARIANE_DATA_WIDTH 64 +// Instantiate protocl checker +// `define PROTOCOL_CHECKER +// write-back cache +// `define WB_DCACHE +// write-through cache +`define WT_DCACHE 1 + +`define RVV_ARIANE 1 + +//============================================================================= +// Ara Configurations +//============================================================================= +`define NrLanes 4 +`define VLEN 4096 diff --git a/fpga/src/xilinx_ara_soc.sv b/fpga/src/xilinx_ara_soc.sv index a0394cc99..002476a15 100644 --- a/fpga/src/xilinx_ara_soc.sv +++ b/fpga/src/xilinx_ara_soc.sv @@ -24,7 +24,7 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #( parameter int unsigned AxiUserWidth = 1, parameter int unsigned AxiIdWidth = 5, // Main memory - parameter int unsigned L2NumWords = 2**14, + parameter int unsigned L2NumWords = 2**15, // Dependant parameters. DO NOT CHANGE! localparam type axi_data_t = logic [AxiDataWidth-1:0], localparam type axi_strb_t = logic [AxiDataWidth/8-1:0], From bd04a8f354c0d0a1e18e814cdfdc833a66bc752a Mon Sep 17 00:00:00 2001 From: Elisabeth Humblet Date: Tue, 9 May 2023 15:51:17 -0400 Subject: [PATCH 8/8] [fpga] Add Alveo U280 constraints --- .gitignore | 2 + ara.core | 2 + fpga/constraints/xcu280.xdc | 81 +++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 fpga/constraints/xcu280.xdc diff --git a/.gitignore b/.gitignore index d6dfc6519..1a84e2faf 100644 --- a/.gitignore +++ b/.gitignore @@ -36,3 +36,5 @@ docs/build/ docs/source/_templates/ *.jou fusesoc.conf +.Xil/ +*.str diff --git a/ara.core b/ara.core index ce7f7bddd..bb0c279c8 100644 --- a/ara.core +++ b/ara.core @@ -294,6 +294,7 @@ filesets: xcu280: files: - fpga/constraints/ara.xdc: {file_type: xdc} + - fpga/constraints/xcu280.xdc: {file_type: xdc} - fpga/src/xilinx_ara_soc.sv: {file_type: systemVerilogSource} svtb: @@ -343,6 +344,7 @@ targets: tools: vivado: part: xcu280-fsvh2892-2l-e + parameters: PRELOAD: datatype : file diff --git a/fpga/constraints/xcu280.xdc b/fpga/constraints/xcu280.xdc new file mode 100644 index 000000000..d0e82f0ad --- /dev/null +++ b/fpga/constraints/xcu280.xdc @@ -0,0 +1,81 @@ + +## Ara SOC +set_property -dict {PACKAGE_PIN BE41 IOSTANDARD LVCMOS18} [get_ports exit_o[63]] +set_property -dict {PACKAGE_PIN BD41 IOSTANDARD LVCMOS18} [get_ports exit_o[62]] +set_property -dict {PACKAGE_PIN BF46 IOSTANDARD LVCMOS18} [get_ports exit_o[61]] +set_property -dict {PACKAGE_PIN BF45 IOSTANDARD LVCMOS18} [get_ports exit_o[60]] +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD LVCMOS18} [get_ports exit_o[59]] +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD LVCMOS18} [get_ports exit_o[58]] +set_property -dict {PACKAGE_PIN BE46 IOSTANDARD LVCMOS18} [get_ports exit_o[57]] +set_property -dict {PACKAGE_PIN BE45 IOSTANDARD LVCMOS18} [get_ports exit_o[56]] +set_property -dict {PACKAGE_PIN BD42 IOSTANDARD LVCMOS18} [get_ports exit_o[55]] +set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS18} [get_ports exit_o[54]] +set_property -dict {PACKAGE_PIN BE44 IOSTANDARD LVCMOS18} [get_ports exit_o[53]] +set_property -dict {PACKAGE_PIN BE43 IOSTANDARD LVCMOS18} [get_ports exit_o[52]] +set_property -dict {PACKAGE_PIN BL50 IOSTANDARD LVCMOS18} [get_ports exit_o[51]] +set_property -dict {PACKAGE_PIN BL48 IOSTANDARD LVCMOS18} [get_ports exit_o[50]] +set_property -dict {PACKAGE_PIN BF53 IOSTANDARD LVCMOS18} [get_ports exit_o[49]] +set_property -dict {PACKAGE_PIN BG47 IOSTANDARD LVCMOS18} [get_ports exit_o[48]] +set_property -dict {PACKAGE_PIN BP49 IOSTANDARD LVCMOS18} [get_ports exit_o[47]] +set_property -dict {PACKAGE_PIN BP48 IOSTANDARD LVCMOS18} [get_ports exit_o[46]] +set_property -dict {PACKAGE_PIN BN51 IOSTANDARD LVCMOS18} [get_ports exit_o[45]] +set_property -dict {PACKAGE_PIN BN50 IOSTANDARD LVCMOS18} [get_ports exit_o[44]] +set_property -dict {PACKAGE_PIN BN49 IOSTANDARD LVCMOS18} [get_ports exit_o[43]] +set_property -dict {PACKAGE_PIN BM48 IOSTANDARD LVCMOS18} [get_ports exit_o[42]] +set_property -dict {PACKAGE_PIN BM50 IOSTANDARD LVCMOS18} [get_ports exit_o[41]] +set_property -dict {PACKAGE_PIN BM49 IOSTANDARD LVCMOS18} [get_ports exit_o[40]] +set_property -dict {PACKAGE_PIN BM52 IOSTANDARD LVCMOS18} [get_ports exit_o[39]] +set_property -dict {PACKAGE_PIN BL51 IOSTANDARD LVCMOS18} [get_ports exit_o[38]] +set_property -dict {PACKAGE_PIN BL53 IOSTANDARD LVCMOS18} [get_ports exit_o[37]] +set_property -dict {PACKAGE_PIN BL52 IOSTANDARD LVCMOS18} [get_ports exit_o[36]] +set_property -dict {PACKAGE_PIN BK49 IOSTANDARD LVCMOS18} [get_ports exit_o[35]] +set_property -dict {PACKAGE_PIN BK48 IOSTANDARD LVCMOS18} [get_ports exit_o[34]] +set_property -dict {PACKAGE_PIN BK51 IOSTANDARD LVCMOS18} [get_ports exit_o[33]] +set_property -dict {PACKAGE_PIN BK50 IOSTANDARD LVCMOS18} [get_ports exit_o[32]] +set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD LVCMOS18} [get_ports exit_o[31]] +set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD LVCMOS18} [get_ports exit_o[30]] +set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD LVCMOS18} [get_ports exit_o[29]] +set_property -dict {PACKAGE_PIN BH47 IOSTANDARD LVCMOS18} [get_ports exit_o[28]] +set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD LVCMOS18} [get_ports exit_o[27]] +set_property -dict {PACKAGE_PIN BH51 IOSTANDARD LVCMOS18} [get_ports exit_o[26]] +set_property -dict {PACKAGE_PIN BH50 IOSTANDARD LVCMOS18} [get_ports exit_o[25]] +set_property -dict {PACKAGE_PIN BH49 IOSTANDARD LVCMOS18} [get_ports exit_o[24]] +set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD LVCMOS18} [get_ports exit_o[23]] +set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD LVCMOS18} [get_ports exit_o[22]] +set_property -dict {PACKAGE_PIN BH52 IOSTANDARD LVCMOS18} [get_ports exit_o[21]] +set_property -dict {PACKAGE_PIN BG52 IOSTANDARD LVCMOS18} [get_ports exit_o[20]] +set_property -dict {PACKAGE_PIN BK54 IOSTANDARD LVCMOS18} [get_ports exit_o[19]] +set_property -dict {PACKAGE_PIN BK53 IOSTANDARD LVCMOS18} [get_ports exit_o[18]] +set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD LVCMOS18} [get_ports exit_o[17]] +set_property -dict {PACKAGE_PIN BH54 IOSTANDARD LVCMOS18} [get_ports exit_o[16]] +set_property -dict {PACKAGE_PIN BG54 IOSTANDARD LVCMOS18} [get_ports exit_o[15]] +set_property -dict {PACKAGE_PIN BG53 IOSTANDARD LVCMOS18} [get_ports exit_o[14]] +set_property -dict {PACKAGE_PIN BE54 IOSTANDARD LVCMOS18} [get_ports exit_o[13]] +set_property -dict {PACKAGE_PIN BE53 IOSTANDARD LVCMOS18} [get_ports exit_o[12]] +set_property -dict {PACKAGE_PIN BG49 IOSTANDARD LVCMOS18} [get_ports exit_o[11]] +set_property -dict {PACKAGE_PIN BG48 IOSTANDARD LVCMOS18} [get_ports exit_o[10]] +set_property -dict {PACKAGE_PIN BG50 IOSTANDARD LVCMOS18} [get_ports exit_o[9]] +set_property -dict {PACKAGE_PIN BF50 IOSTANDARD LVCMOS18} [get_ports exit_o[8]] +set_property -dict {PACKAGE_PIN BF52 IOSTANDARD LVCMOS18} [get_ports exit_o[7]] +set_property -dict {PACKAGE_PIN BF51 IOSTANDARD LVCMOS18} [get_ports exit_o[6]] +set_property -dict {PACKAGE_PIN BF48 IOSTANDARD LVCMOS18} [get_ports exit_o[5]] +set_property -dict {PACKAGE_PIN BF47 IOSTANDARD LVCMOS18} [get_ports exit_o[4]] +set_property -dict {PACKAGE_PIN BE50 IOSTANDARD LVCMOS18} [get_ports exit_o[3]] +set_property -dict {PACKAGE_PIN BE49 IOSTANDARD LVCMOS18} [get_ports exit_o[2]] +set_property -dict {PACKAGE_PIN BE51 IOSTANDARD LVCMOS18} [get_ports exit_o[1]] +set_property -dict {PACKAGE_PIN BD51 IOSTANDARD LVCMOS18} [get_ports exit_o[0]] + +## CLK +set_property -dict {PACKAGE_PIN BJ24 IOSTANDARD LVCMOS18} [get_ports clk_i] + +## RESET +set_property -dict {PACKAGE_PIN BH26 IOSTANDARD LVCMOS18} [get_ports rst_ni] + +## UART +set_property -dict {PACKAGE_PIN BF21 IOSTANDARD LVCMOS18} [get_ports rx_i] +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS18} [get_ports tx_o] + +#set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports tx_o] +#set_property -dict {PACKAGE_PIN B33 IOSTANDARD LVCMOS18} [get_ports rx_i] + +