From fe570ff520b5ac7087c6e505957c26a12c8f306e Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Wed, 30 Oct 2024 18:32:33 +0100 Subject: [PATCH] [hardware] Remove vl-mask for mask tail elements Mask-producing insn can avoid worrying of tail elements --- hardware/src/masku/masku.sv | 6 ++---- hardware/src/masku/masku_operands.sv | 4 ---- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/hardware/src/masku/masku.sv b/hardware/src/masku/masku.sv index 3d87a95f5..0cd0fa9e2 100644 --- a/hardware/src/masku/masku.sv +++ b/hardware/src/masku/masku.sv @@ -109,7 +109,6 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( pe_req_t vinsn_issue; logic [NrLanes*ELEN-1:0] bit_enable_mask; - logic [NrLanes*ELEN-1:0] bit_enable_shuffle; logic [NrLanes*ELEN-1:0] alu_result_compressed; // Performs all shuffling and deshuffling of mask operands (including masks for mask instructions) @@ -149,7 +148,6 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( .masku_operand_m_seq_valid_o ( ), .masku_operand_m_seq_ready_i ( ), .bit_enable_mask_o ( bit_enable_mask ), - .shuffled_vl_bit_mask_o ( bit_enable_shuffle ), .alu_result_compressed_o ( alu_result_compressed ) ); @@ -453,8 +451,8 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( // Evaluate the instruction unique case (vinsn_issue.op) inside - [VMANDNOT:VMXNOR]: alu_result = (masku_operand_alu) | (~bit_enable_shuffle); - [VMFEQ:VMSGTU], [VMSGT:VMSBC]: alu_result = (alu_result_compressed & bit_enable_mask) | (~bit_enable_shuffle); + [VMANDNOT:VMXNOR]: alu_result = masku_operand_alu; + [VMFEQ:VMSGTU], [VMSGT:VMSBC]: alu_result = alu_result_compressed & bit_enable_mask; [VMSBF:VMSIF] : begin if (&masku_operand_vs2_seq_valid && (&masku_operand_m_valid || vinsn_issue.vm)) begin for (int i = 0; i < NrLanes * DataWidth; i++) begin diff --git a/hardware/src/masku/masku_operands.sv b/hardware/src/masku/masku_operands.sv index 93ba59a90..503f5b207 100644 --- a/hardware/src/masku/masku_operands.sv +++ b/hardware/src/masku/masku_operands.sv @@ -54,7 +54,6 @@ module masku_operands import ara_pkg::*; import rvv_pkg::*; #( output logic [ NrLanes-1:0] masku_operand_m_seq_valid_o, input logic [ NrLanes-1:0] masku_operand_m_seq_ready_i, output logic [NrLanes*ELEN-1:0] bit_enable_mask_o, // Bit mask for mask unit instructions (shuffled like mask register) - output logic [NrLanes*ELEN-1:0] shuffled_vl_bit_mask_o, // vl mask for mask unit instructions (first vl bits are 1, others 0) (shuffled like mask register) output logic [NrLanes*ELEN-1:0] alu_result_compressed_o // ALU/FPU results compressed (from sew to 1-bit) (shuffled, in mask format) ); @@ -181,9 +180,6 @@ module masku_operands import ara_pkg::*; import rvv_pkg::*; #( end end - assign shuffled_vl_bit_mask_o = shuffled_vl_bit_mask; - - // ------------------------------------------- // Compress ALU/FPU results into a mask vector // -------------------------------------------