From f2c62ee55e71aba9ebc1d16893d006ff6a037366 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 15 Nov 2024 17:32:53 +0100 Subject: [PATCH] [hardware] :bug: Fix legality check in dispatcher --- hardware/src/ara_dispatcher.sv | 75 +++++++++++++++------------------- 1 file changed, 34 insertions(+), 41 deletions(-) diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv index bc028aa31..fe883e534 100644 --- a/hardware/src/ara_dispatcher.sv +++ b/hardware/src/ara_dispatcher.sv @@ -224,7 +224,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( logic load_zero_vl, store_zero_vl; // Do not checks vregs validity against current LMUL logic skip_lmul_checks; - logic skip_vs1_lmul_checks; // Are we decoding? logic is_decoding; // Is this an in-lane operation? @@ -333,7 +332,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( store_zero_vl = 1'b0; skip_lmul_checks = 1'b0; - skip_vs1_lmul_checks = 1'b0; null_vslideup = 1'b0; @@ -1522,7 +1520,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( 6'b010010: begin // VXUNARY0 // These instructions do not use vs1 ara_req.use_vs1 = 1'b0; - skip_vs1_lmul_checks = 1'b1; // They are always encoded as ADDs with zero. ara_req.op = ara_pkg::VADD; ara_req.use_scalar_op = 1'b1; @@ -1750,21 +1747,21 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // destination register. if (!skip_lmul_checks) begin unique case (ara_req.emul) - LMUL_2: if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4: if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8: if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2: if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_4: if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_8: if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vd; default:; endcase unique case (lmul_vs2) - LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2; default:; endcase unique case (lmul_vs1) - LMUL_2: if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4: if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8: if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2: if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs1; + LMUL_4: if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs1; + LMUL_8: if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs1; default:; endcase end @@ -1992,15 +1989,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // destination register. if (!skip_lmul_checks) begin unique case (ara_req.emul) - LMUL_2: if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4: if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8: if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2: if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_4: if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_8: if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vd; default:; endcase unique case (lmul_vs2) - LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2; default:; endcase end @@ -2146,7 +2143,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( 6'b010010: begin // VFUNARY0 // These instructions do not use vs1 ara_req.use_vs1 = 1'b0; - skip_vs1_lmul_checks = 1'b1; case (insn.varith_type.rs1) 5'b00000: ara_req.op = VFCVTXUF; @@ -2253,7 +2249,6 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( 6'b010011: begin // VFUNARY1 // These instructions do not use vs1 ara_req.use_vs1 = 1'b0; - skip_vs1_lmul_checks = 1'b1; unique case (insn.varith_type.rs1) 5'b00000: ara_req.op = ara_pkg::VFSQRT; @@ -2411,28 +2406,26 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // destination register. if (!skip_lmul_checks) begin unique case (ara_req.emul) - LMUL_2 : if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4 : if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8 : if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2 : if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_4 : if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_8 : if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vd; LMUL_RSVD: illegal_insn = 1'b1; default:; endcase unique case (lmul_vs2) - LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_RSVD: illegal_insn = 1'b1; + default:; + endcase + unique case (lmul_vs1) + LMUL_2 : if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs1; + LMUL_4 : if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs1; + LMUL_8 : if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs1; LMUL_RSVD: illegal_insn = 1'b1; default:; endcase - if (!skip_vs1_lmul_checks) begin - unique case (lmul_vs1) - LMUL_2 : if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4 : if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8 : if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn = 1'b1; - LMUL_RSVD: illegal_insn = 1'b1; - default:; - endcase - end end // Ara can support 16-bit float, 32-bit float, 64-bit float. @@ -2705,16 +2698,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // destination register. if (!skip_lmul_checks) begin unique case (ara_req.emul) - LMUL_2 : if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4 : if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8 : if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2 : if ((insn.varith_type.rd & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_4 : if ((insn.varith_type.rd & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vd; + LMUL_8 : if ((insn.varith_type.rd & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vd; LMUL_RSVD: illegal_insn = 1'b1; default:; endcase unique case (lmul_vs2) - LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = 1'b1; - LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = 1'b1; - LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = 1'b1; + LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2; + LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2; LMUL_RSVD: illegal_insn = 1'b1; default:; endcase