From e04b9324d624ea654df874e46f1ba160053e0342 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 16 Sep 2024 13:56:51 +0200 Subject: [PATCH] [hardware] Clean up pre-decoder --- hardware/src/ara_pre_decoder.sv | 66 ++++++++++++++++----------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/hardware/src/ara_pre_decoder.sv b/hardware/src/ara_pre_decoder.sv index 4d6c8223d..9a0f25d0b 100644 --- a/hardware/src/ara_pre_decoder.sv +++ b/hardware/src/ara_pre_decoder.sv @@ -5,7 +5,7 @@ // Author: Matheus Cavalcante // Frederic zur Bonsen // Description: -// Ara's predecoder to detect legallity: this module needs to be slimmed and has unused functionality. +// Ara's predecoder to detect legality: this module needs to be slimmed and has unused functionality. module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( parameter int unsigned NrLanes = 0, @@ -464,7 +464,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vtype_d = vtype_xlen(riscv::xlen_t'(core_v_xif_req_i.register_rs[1][7:0])); csr_stall_o = 1'b1; end else begin - insn_error = 1'b1; + illegal_insn = 1'b1; end // Check whether the updated vtype makes sense @@ -2030,8 +2030,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( end default: begin // Trigger an error - ara_req_valid_d = 1'b0; - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -2559,8 +2558,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( is_rs2 = insn.vmem_type.mop == 2'b10; // Strided operation end default: begin // Invalid. Element is too wide, or encoding is non-existant. - ara_req_valid_d = 1'b0; - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase @@ -2766,8 +2764,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( is_rs2 = insn.vmem_type.mop == 2'b10; // Strided operation end default: begin // Invalid. Element is too wide, or encoding is non-existant. - ara_req_valid_d = 1'b0; - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase @@ -2907,7 +2904,8 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( case (riscv::csr_addr_t'(core_v_xif_req_i.issue_req_instr.itype.imm)) // Only vstart can be written with CSR instructions. riscv::CSR_VSTART: begin - vstart_d = core_v_xif_req_i.register_rs[0]; + vstart_d = core_v_xif_req_i.register_rs[0]; + csr_stall_o = 1'b1; end riscv::CSR_VXRM: begin vxrm_d = vxrm_t'(core_v_xif_req_i.register_rs[0][1:0]); @@ -2916,7 +2914,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vxsat_d = vxsat_e'(core_v_xif_req_i.register_rs[0][0]); end default: begin - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -2927,24 +2925,25 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( // Decode the CSR. case (riscv::csr_addr_t'(core_v_xif_req_i.issue_req_instr.itype.imm)) riscv::CSR_VSTART: begin - vstart_d = vstart_q | vlen_t'(core_v_xif_req_i.register_rs[0]); + vstart_d = vstart_q | vlen_t'(core_v_xif_req_i.register_rs[0]); + csr_stall_o = 1'b1; end riscv::CSR_VTYPE: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VL: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VLENB: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VXRM: begin @@ -2954,7 +2953,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vxsat_d = vxsat_q | vxsat_e'(core_v_xif_req_i.register_rs[0][0]); end default: begin - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -2965,31 +2964,32 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( // Decode the CSR. case (riscv::csr_addr_t'(core_v_xif_req_i.issue_req_instr.itype.imm)) riscv::CSR_VSTART: begin - vstart_d = vstart_q & ~vlen_t'(core_v_xif_req_i.register_rs[0]); + vstart_d = vstart_q & ~vlen_t'(core_v_xif_req_i.register_rs[0]); + csr_stall_o = 1'b1; end riscv::CSR_VTYPE: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VL: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VLENB: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VXSAT: begin vxsat_d = vxsat_q & ~vxsat_e'(core_v_xif_req_i.register_rs[0][0]); end default: begin - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -3011,7 +3011,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vxsat_d = core_v_xif_req_i.issue_req_instr.itype.rs1[15]; end default: begin - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -3027,19 +3027,19 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( riscv::CSR_VTYPE: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VL: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VLENB: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VXSAT: begin @@ -3047,7 +3047,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vxsat_d = vxsat_q | vxsat_e'(core_v_xif_req_i.issue_req_instr.itype.rs1[15]); end default: begin - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -3063,19 +3063,19 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( riscv::CSR_VTYPE: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VL: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VLENB: begin // Only reads are allowed if (!(core_v_xif_req_i.issue_req_instr.itype.rs1 == '0)) begin - insn_error = 1'b1; + illegal_insn = 1'b1; end end riscv::CSR_VXSAT: begin @@ -3083,13 +3083,13 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vxsat_d = vxsat_q & ~vxsat_e'(core_v_xif_req_i.issue_req_instr.itype.rs1[15]); end default: begin - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end default: begin // Trigger an illegal instruction - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -3108,7 +3108,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( default: begin // Trigger an illegal instruction - insn_error = 1'b1; + illegal_insn = 1'b1; end endcase end @@ -3185,7 +3185,7 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( endcase end - // csr sync + // Sync the speculative CSRs with the current value after a flush. if (sync_i) begin vstart_d = csr_sync_i.vstart; vl_d = csr_sync_i.vl; @@ -3194,4 +3194,4 @@ module ara_pre_decoder import ara_pkg::*; import rvv_pkg::*; #( vxrm_d = csr_sync_i.vxrm; end end: p_decoder -endmodule : ara_pre_decoder \ No newline at end of file +endmodule : ara_pre_decoder