diff --git a/hardware/src/lane/clk_gating_generic.sv b/hardware/src/lane/clk_gating_generic.sv
deleted file mode 100644
index 644bbc4f3..000000000
--- a/hardware/src/lane/clk_gating_generic.sv
+++ /dev/null
@@ -1,18 +0,0 @@
-// Copyright 2023 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-//
-// Authors: Matteo Perotti <mperotti@iis.ee.ethz.ch>
-// Description:
-// Technology-agnostic replacement for a clock-gating cell
-
-module clk_gating_generic (
-  input  logic CLK,
-  input  logic TE,
-  input  logic E,
-  output logic Z
-);
-
-  assign Z = E & CLK;
-
-endmodule
diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv
index f193d3e47..c00844552 100644
--- a/hardware/src/lane/vmfpu.sv
+++ b/hardware/src/lane/vmfpu.sv
@@ -287,12 +287,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
   // Clock-gate for the multipliers
   logic clkgate_en_d, clkgate_en_q, clk_i_gated;
 
-`ifdef GF22
-  clk_gating_gf22
-`else
-  tc_clk_gating
-`endif
-  i_simd_mul_manual_clk_gate (
+  tc_clk_gating i_simd_mul_manual_clk_gate (
     .clk_i     (clk_i       ),
     .en_i      (clkgate_en_q),
     .test_en_i (1'b0        ),