diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv index e89658ef7..a6d4e3fc5 100644 --- a/hardware/src/ara_dispatcher.sv +++ b/hardware/src/ara_dispatcher.sv @@ -291,6 +291,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( null_vslideup = 1'b0; + vfmvfs_result = ara_resp_i.resp; + is_decoding = 1'b0; in_lane_op = 1'b0; @@ -645,18 +647,43 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( end 6'b011001: begin ara_req_d.op = ara_pkg::VMSNE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011010: begin ara_req_d.op = ara_pkg::VMSLTU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011011: begin ara_req_d.op = ara_pkg::VMSLT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011100: begin ara_req_d.op = ara_pkg::VMSLEU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011101: begin ara_req_d.op = ara_pkg::VMSLE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b010111: begin ara_req_d.op = ara_pkg::VMERGE; @@ -874,24 +901,59 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( end 6'b011001: begin ara_req_d.op = ara_pkg::VMSNE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011010: begin ara_req_d.op = ara_pkg::VMSLTU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011011: begin ara_req_d.op = ara_pkg::VMSLT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011100: begin ara_req_d.op = ara_pkg::VMSLEU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011101: begin ara_req_d.op = ara_pkg::VMSLE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011110: begin ara_req_d.op = ara_pkg::VMSGTU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011111: begin ara_req_d.op = ara_pkg::VMSGT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b010111: begin ara_req_d.op = ara_pkg::VMERGE; @@ -1049,18 +1111,43 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( end 6'b011001: begin ara_req_d.op = ara_pkg::VMSNE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011100: begin ara_req_d.op = ara_pkg::VMSLEU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011101: begin ara_req_d.op = ara_pkg::VMSLE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011110: begin ara_req_d.op = ara_pkg::VMSGTU; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b011111: begin ara_req_d.op = ara_pkg::VMSGT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; end 6'b010111: begin ara_req_d.op = ara_pkg::VMERGE; @@ -1975,10 +2062,38 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( ara_req_valid_d = 1'b0; end end - 6'b011000: ara_req_d.op = ara_pkg::VMFEQ; - 6'b011001: ara_req_d.op = ara_pkg::VMFLE; - 6'b011011: ara_req_d.op = ara_pkg::VMFLT; - 6'b011100: ara_req_d.op = ara_pkg::VMFNE; + 6'b011000: begin + ara_req_d.op = ara_pkg::VMFEQ; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011001: begin + ara_req_d.op = ara_pkg::VMFLE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011011: begin + ara_req_d.op = ara_pkg::VMFLT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011100: begin + ara_req_d.op = ara_pkg::VMFNE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end 6'b010010: begin // VFUNARY0 // These instructions do not use vs1 ara_req_d.use_vs1 = 1'b0; @@ -2270,20 +2385,20 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // Ara can support 16-bit float, 32-bit float, 64-bit float. // Ara cannot support instructions who operates on more than 64 bits. unique case (FPUSupport) - FPUSupportHalfSingleDouble: if (int'(ara_req_d.vtype.vsew) < int'(EW16) || - int'(ara_req_d.vtype.vsew) > int'(EW64) || int'(ara_req_d.eew_vs2) > int'(EW64)) + FPUSupportHalfSingleDouble: if (int'(csr_vtype_q.vsew) < int'(EW16) || + int'(csr_vtype_q.vsew) > int'(EW64) || int'(ara_req_d.eew_vs2) > int'(EW64)) illegal_insn = 1'b1; - FPUSupportHalfSingle: if (int'(ara_req_d.vtype.vsew) < int'(EW16) || - int'(ara_req_d.vtype.vsew) > int'(EW32) || int'(ara_req_d.eew_vs2) > int'(EW32)) + FPUSupportHalfSingle: if (int'(csr_vtype_q.vsew) < int'(EW16) || + int'(csr_vtype_q.vsew) > int'(EW32) || int'(ara_req_d.eew_vs2) > int'(EW32)) illegal_insn = 1'b1; - FPUSupportSingleDouble: if (int'(ara_req_d.vtype.vsew) < int'(EW32) || - int'(ara_req_d.vtype.vsew) > int'(EW64) || int'(ara_req_d.eew_vs2) > int'(EW64)) + FPUSupportSingleDouble: if (int'(csr_vtype_q.vsew) < int'(EW32) || + int'(csr_vtype_q.vsew) > int'(EW64) || int'(ara_req_d.eew_vs2) > int'(EW64)) illegal_insn = 1'b1; - FPUSupportHalf: if (int'(ara_req_d.vtype.vsew) != int'(EW16) || int'(ara_req_d.eew_vs2) > int'(EW16)) + FPUSupportHalf: if (int'(csr_vtype_q.vsew) != int'(EW16) || int'(ara_req_d.eew_vs2) > int'(EW16)) illegal_insn = 1'b1; - FPUSupportSingle: if (int'(ara_req_d.vtype.vsew) != int'(EW32) || int'(ara_req_d.eew_vs2) > int'(EW32)) + FPUSupportSingle: if (int'(csr_vtype_q.vsew) != int'(EW32) || int'(ara_req_d.eew_vs2) > int'(EW32)) illegal_insn = 1'b1; - FPUSupportDouble: if (int'(ara_req_d.vtype.vsew) != int'(EW64) || int'(ara_req_d.eew_vs2) > int'(EW64)) + FPUSupportDouble: if (int'(csr_vtype_q.vsew) != int'(EW64) || int'(ara_req_d.eew_vs2) > int'(EW64)) illegal_insn = 1'b1; default: illegal_insn = 1'b1; // Unsupported configuration endcase @@ -2351,12 +2466,54 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( skip_lmul_checks = 1'b1; end 6'b010111: ara_req_d.op = ara_pkg::VMERGE; - 6'b011000: ara_req_d.op = ara_pkg::VMFEQ; - 6'b011001: ara_req_d.op = ara_pkg::VMFLE; - 6'b011011: ara_req_d.op = ara_pkg::VMFLT; - 6'b011100: ara_req_d.op = ara_pkg::VMFNE; - 6'b011101: ara_req_d.op = ara_pkg::VMFGT; - 6'b011111: ara_req_d.op = ara_pkg::VMFGE; + 6'b011000: begin + ara_req_d.op = ara_pkg::VMFEQ; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011001: begin + ara_req_d.op = ara_pkg::VMFLE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011011: begin + ara_req_d.op = ara_pkg::VMFLT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011100: begin + ara_req_d.op = ara_pkg::VMFNE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011101: begin + ara_req_d.op = ara_pkg::VMFGT; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end + 6'b011111: begin + ara_req_d.op = ara_pkg::VMFGE; + ara_req_d.use_vd_op = 1'b1; + ara_req_d.eew_vs1 = csr_vtype_q.vsew; + ara_req_d.eew_vs2 = csr_vtype_q.vsew; + ara_req_d.eew_vd_op = eew_q[ara_req_d.vd]; + ara_req_d.vtype.vsew = eew_q[ara_req_d.vd]; + end 6'b100100: ara_req_d.op = ara_pkg::VFMUL; 6'b100000: ara_req_d.op = ara_pkg::VFDIV; 6'b100001: ara_req_d.op = ara_pkg::VFRDIV; @@ -2513,16 +2670,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( // Ara can support 16-bit float, 32-bit float, 64-bit float. // Ara cannot support instructions who operates on more than 64 bits. unique case (FPUSupport) - FPUSupportHalfSingleDouble: if (int'(ara_req_d.vtype.vsew) < int'(EW16) || - int'(ara_req_d.vtype.vsew) > int'(EW64)) illegal_insn = 1'b1; - FPUSupportHalfSingle: if (int'(ara_req_d.vtype.vsew) < int'(EW16) || - int'(ara_req_d.vtype.vsew) > int'(EW32)) illegal_insn = 1'b1; - FPUSupportSingleDouble: if (int'(ara_req_d.vtype.vsew) < int'(EW32) || - int'(ara_req_d.vtype.vsew) > int'(EW64)) illegal_insn = 1'b1; - FPUSupportHalf: if (int'(ara_req_d.vtype.vsew) != int'(EW16)) illegal_insn = 1'b1; - FPUSupportSingle: if (int'(ara_req_d.vtype.vsew) != int'(EW32)) + FPUSupportHalfSingleDouble: if (int'(csr_vtype_q.vsew) < int'(EW16) || + int'(csr_vtype_q.vsew) > int'(EW64)) illegal_insn = 1'b1; + FPUSupportHalfSingle: if (int'(csr_vtype_q.vsew) < int'(EW16) || + int'(csr_vtype_q.vsew) > int'(EW32)) illegal_insn = 1'b1; + FPUSupportSingleDouble: if (int'(csr_vtype_q.vsew) < int'(EW32) || + int'(csr_vtype_q.vsew) > int'(EW64)) illegal_insn = 1'b1; + FPUSupportHalf: if (int'(csr_vtype_q.vsew) != int'(EW16)) illegal_insn = 1'b1; + FPUSupportSingle: if (int'(csr_vtype_q.vsew) != int'(EW32)) illegal_insn = 1'b1; - FPUSupportDouble: if (int'(ara_req_d.vtype.vsew) != int'(EW64)) + FPUSupportDouble: if (int'(csr_vtype_q.vsew) != int'(EW64)) illegal_insn = 1'b1; default: illegal_insn = 1'b1; // Unsupported configuration endcase diff --git a/hardware/src/lane/lane_sequencer.sv b/hardware/src/lane/lane_sequencer.sv index 55581bc77..6a3dd2b52 100644 --- a/hardware/src/lane/lane_sequencer.sv +++ b/hardware/src/lane/lane_sequencer.sv @@ -760,7 +760,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg:: // extra operand regardless of whether it is valid in this lane or not. if ((operand_request[MaskB].vl * NrLanes) != pe_req.vl) operand_request[MaskB].vl += 1; - end else begin // Mask logical, VMSBF, VMSIF, VMSOF, VCPOP, VFIRST + end else begin // Mask logical, comparisons, VMSBF, VMSIF, VMSOF // Mask layout operand_request[MaskB].eew = EW64; operand_request[MaskB].vl = (pe_req.vl / NrLanes / ELEN); diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv index fdf10363a..3f7a80590 100644 --- a/hardware/src/lane/vmfpu.sv +++ b/hardware/src/lane/vmfpu.sv @@ -1245,21 +1245,18 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; (vinsn_processing_q.op == VMFNE) ? ~vfpu_processed_result[16*b] : vfpu_processed_result[16*b]; - for (int b = 0; b < 4; b++) vfpu_processed_result[16*b+1] = vfpu_mask[2*b]; end EW32: begin for (int b = 0; b < 2; b++) vfpu_processed_result[32*b] = (vinsn_processing_q.op == VMFNE) ? ~vfpu_processed_result[32*b] : vfpu_processed_result[32*b]; - for (int b = 0; b < 2; b++) vfpu_processed_result[32*b+1] = vfpu_mask[4*b]; end EW64: begin for (int b = 0; b < 1; b++) vfpu_processed_result[b] = (vinsn_processing_q.op == VMFNE) ? ~vfpu_processed_result[b] : vfpu_processed_result[b]; - for (int b = 0; b < 1; b++) vfpu_processed_result[b+1] = vfpu_mask[8*b]; end endcase end @@ -2180,7 +2177,15 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; if (!vinsn_queue_full && vfu_operation_valid_i && (vfu_operation_i.vfu == VFU_MFpu || vfu_operation_i.op inside {[VMFEQ:VMFGE]})) begin - vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt] = vfu_operation_i; + vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt] = vfu_operation_i; + // Masks are handled in the MASKU directly for comparisons + vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt].vm = vfu_operation_i.op inside {[VMFEQ:VMFGE]} + ? 1'b1 + : vfu_operation_i.vm; + // During comparisons, vd_op is for the masku, not for the VMFPU + vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt].use_vd_op = vfu_operation_i.op inside {[VMFEQ:VMFGE]} + ? 1'b0 + : vfu_operation_i.use_vd_op; // Initialize counters if (vinsn_queue_d.issue_cnt == '0 && !prevent_commit) begin diff --git a/hardware/src/masku/masku.sv b/hardware/src/masku/masku.sv index a2b129852..7fd4b27cd 100644 --- a/hardware/src/masku/masku.sv +++ b/hardware/src/masku/masku.sv @@ -698,13 +698,9 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( // Simplify layout handling alu_result = alu_result_vm_shuf; - // Prepare result queue mask; VIOTA,VID use the BE instead - for (int lane = 0; lane < NrLanes; lane++) - result_queue_mask_seq[lane] = vinsn_issue.op inside {[VIOTA:VID]} ? '0 : masku_operand_m_seq[lane*DataWidth +: DataWidth] | {DataWidth{vinsn_issue.vm}}; - - // Shuffle the background information with vtype.vsew encoding - for (int lane = 0; lane < NrLanes; lane++) - background_data_init_seq[lane*DataWidth +: DataWidth] = masku_operand_vd_seq[lane*DataWidth +: DataWidth] | result_queue_mask_seq[lane]; + // Prepare the background data with vtype.vsew encoding + result_queue_mask_seq = vinsn_issue.op inside {[VIOTA:VID]} ? '0 : masku_operand_m_seq | {NrLanes*DataWidth{vinsn_issue.vm}}; + background_data_init_seq = masku_operand_vd_seq | result_queue_mask_seq; for (int b = 0; b < (NrLanes*StrbWidth); b++) begin automatic int shuffle_byte = shuffle_index(b, NrLanes, vinsn_issue.vtype.vsew); background_data_init_shuf[8*shuffle_byte +: 8] = background_data_init_seq[8*b +: 8]; @@ -953,7 +949,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( for (int unsigned lane = 0; lane < NrLanes; lane++) begin result_queue_background_data[lane] = (out_valid_cnt_q != '0) ? result_queue_q[result_queue_write_pnt_q][lane].wdata - : vinsn_issue.op inside {[VIOTA:VID]} ? '1 : background_data_init_shuf; + : vinsn_issue.op inside {[VIOTA:VID]} ? '1 : background_data_init_shuf[lane*DataWidth +: DataWidth]; end for (int unsigned lane = 0; lane < NrLanes; lane++) begin // The alu_result has all the bits at 1 except for the portion of bits to write.