From d66d7628aded9b280672b7b5ac8ecd0d212a388d Mon Sep 17 00:00:00 2001 From: Matteo Perotti <mperotti@iis.ee.ethz.ch> Date: Thu, 19 Sep 2024 14:27:30 +0200 Subject: [PATCH] [hardware] Parametrize OS support (disabled by default) --- hardware/src/ara.sv | 49 +++++++++++++++++++++++++++++++------- hardware/src/ara_soc.sv | 2 ++ hardware/src/ara_system.sv | 3 ++- 3 files changed, 44 insertions(+), 10 deletions(-) diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv index 92f1861bc..92d6cd1c6 100644 --- a/hardware/src/ara.sv +++ b/hardware/src/ara.sv @@ -10,6 +10,7 @@ module ara import ara_pkg::*; #( // RVV Parameters parameter int unsigned NrLanes = 0, // Number of parallel vector lanes. parameter int unsigned VLEN = 0, // VLEN [bit] + parameter int unsigned OSSupport = 0, // Support for floating-point data types parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble, // External support for vfrec7, vfrsqrt7 @@ -487,6 +488,36 @@ module ara import ara_pkg::*; #( logic vldu_mask_ready; logic vstu_mask_ready; + // Optional OS support + logic acc_mmu_misaligned_ex, acc_mmu_req, acc_mmu_is_store, acc_mmu_dtlb_hit, acc_mmu_valid, acc_mmu_en; + logic [riscv::VLEN-1:0] acc_mmu_vaddr; + logic [riscv::PLEN-1:0] acc_mmu_paddr; + logic [riscv::PPNW-1:0] acc_mmu_dtlb_ppn; + ariane_pkg::exception_t acc_mmu_exception; + if (OSSupport) begin + assign acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex = acc_mmu_misaligned_ex; + assign acc_resp_o.acc_mmu_req.acc_mmu_req = acc_mmu_req; + assign acc_resp_o.acc_mmu_req.acc_mmu_vaddr = acc_mmu_vaddr; + assign acc_resp_o.acc_mmu_req.acc_mmu_is_store = acc_mmu_is_store; + assign acc_mmu_en = acc_req_i.acc_mmu_en; + assign acc_mmu_dtlb_hit = acc_req_i.acc_mmu_resp.acc_mmu_dtlb_hit; + assign acc_mmu_dtlb_ppn = acc_req_i.acc_mmu_resp.acc_mmu_dtlb_ppn; + assign acc_mmu_valid = acc_req_i.acc_mmu_resp.acc_mmu_valid; + assign acc_mmu_paddr = acc_req_i.acc_mmu_resp.acc_mmu_paddr; + assign acc_mmu_exception = acc_req_i.acc_mmu_resp.acc_mmu_exception; + end else begin + assign acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex = '0; + assign acc_resp_o.acc_mmu_req.acc_mmu_req = '0; + assign acc_resp_o.acc_mmu_req.acc_mmu_vaddr = '0; + assign acc_resp_o.acc_mmu_req.acc_mmu_is_store = '0; + assign acc_mmu_en = '0; + assign acc_mmu_dtlb_hit = '0; + assign acc_mmu_dtlb_ppn = '0; + assign acc_mmu_valid = '0; + assign acc_mmu_paddr = '0; + assign acc_mmu_exception = '0; + end + vlsu #( .NrLanes (NrLanes ), .VLEN (VLEN ), @@ -541,15 +572,15 @@ module ara import ara_pkg::*; #( // CSR input .en_ld_st_translation_i (acc_req_i.acc_mmu_en ), // Interface with CVA6's sv39 MMU - .mmu_misaligned_ex_o (acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex ), - .mmu_req_o (acc_resp_o.acc_mmu_req.acc_mmu_req ), - .mmu_vaddr_o (acc_resp_o.acc_mmu_req.acc_mmu_vaddr ), - .mmu_is_store_o (acc_resp_o.acc_mmu_req.acc_mmu_is_store ), - .mmu_dtlb_hit_i (acc_req_i.acc_mmu_resp.acc_mmu_dtlb_hit ), - .mmu_dtlb_ppn_i (acc_req_i.acc_mmu_resp.acc_mmu_dtlb_ppn ), - .mmu_valid_i (acc_req_i.acc_mmu_resp.acc_mmu_valid ), - .mmu_paddr_i (acc_req_i.acc_mmu_resp.acc_mmu_paddr ), - .mmu_exception_i (acc_req_i.acc_mmu_resp.acc_mmu_exception ), + .mmu_misaligned_ex_o (acc_mmu_misaligned_ex ), + .mmu_req_o (acc_mmu_req ), + .mmu_vaddr_o (acc_mmu_vaddr ), + .mmu_is_store_o (acc_mmu_is_store ), + .mmu_dtlb_hit_i (acc_mmu_dtlb_hit ), + .mmu_dtlb_ppn_i (acc_mmu_dtlb_ppn ), + .mmu_valid_i (acc_mmu_valid ), + .mmu_paddr_i (acc_mmu_paddr ), + .mmu_exception_i (acc_mmu_exception ), // Load unit .ldu_result_req_o (ldu_result_req ), .ldu_result_addr_o (ldu_result_addr ), diff --git a/hardware/src/ara_soc.sv b/hardware/src/ara_soc.sv index c9c9d4a04..45d4de78d 100644 --- a/hardware/src/ara_soc.sv +++ b/hardware/src/ara_soc.sv @@ -10,6 +10,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( // RVV Parameters parameter int unsigned NrLanes = 0, // Number of parallel vector lanes. parameter int unsigned VLEN = 0, // VLEN [bit] + parameter int unsigned OSSupport = 0, // Support for OS // Support for floating-point data types parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble, // External support for vfrec7, vfrsqrt7 @@ -514,6 +515,7 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #( ara_system #( .NrLanes (NrLanes ), .VLEN (VLEN ), + .OSSupport (OSSupport ), .FPUSupport (FPUSupport ), .FPExtSupport (FPExtSupport ), .FixPtSupport (FixPtSupport ), diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index df32066bb..c74de9d4e 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -10,7 +10,7 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( // RVV Parameters parameter int unsigned NrLanes = 0, // Number of parallel vector lanes. parameter int unsigned VLEN = 0, // VLEN [bit] - // Support for floating-point data types + parameter int unsigned OSSupport = 0, // Support for floating-point data types parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble, // External support for vfrec7, vfrsqrt7 parameter fpext_support_e FPExtSupport = FPExtSupportEnable, @@ -210,6 +210,7 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( ara #( .NrLanes (NrLanes ), .VLEN (VLEN ), + .OSSupport (OSSupport ), .FPUSupport (FPUSupport ), .FPExtSupport(FPExtSupport ), .FixPtSupport(FixPtSupport ),