From 9a849b256e7bfa5a39458cd77d6eac27ecbf6fe2 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Thu, 7 Sep 2023 16:31:49 +0200 Subject: [PATCH] [hardware] Clean-up unused clk-gating cell --- Bender.yml | 1 - hardware/src/lane/clk_gating_generic.sv | 18 ------------------ hardware/src/lane/vmfpu.sv | 7 +------ 3 files changed, 1 insertion(+), 25 deletions(-) delete mode 100644 hardware/src/lane/clk_gating_generic.sv diff --git a/Bender.yml b/Bender.yml index d114499d2..051313258 100644 --- a/Bender.yml +++ b/Bender.yml @@ -42,7 +42,6 @@ sources: - hardware/src/lane/simd_mul.sv - hardware/src/lane/vector_regfile.sv - hardware/src/lane/power_gating_generic.sv - - hardware/src/lane/clk_gating_generic.sv - hardware/src/masku/masku.sv - hardware/src/sldu/p2_stride_gen.sv - hardware/src/sldu/sldu_op_dp.sv diff --git a/hardware/src/lane/clk_gating_generic.sv b/hardware/src/lane/clk_gating_generic.sv deleted file mode 100644 index 644bbc4f3..000000000 --- a/hardware/src/lane/clk_gating_generic.sv +++ /dev/null @@ -1,18 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 -// -// Authors: Matteo Perotti -// Description: -// Technology-agnostic replacement for a clock-gating cell - -module clk_gating_generic ( - input logic CLK, - input logic TE, - input logic E, - output logic Z -); - - assign Z = E & CLK; - -endmodule diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv index f193d3e47..c00844552 100644 --- a/hardware/src/lane/vmfpu.sv +++ b/hardware/src/lane/vmfpu.sv @@ -287,12 +287,7 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*; // Clock-gate for the multipliers logic clkgate_en_d, clkgate_en_q, clk_i_gated; -`ifdef GF22 - clk_gating_gf22 -`else - tc_clk_gating -`endif - i_simd_mul_manual_clk_gate ( + tc_clk_gating i_simd_mul_manual_clk_gate ( .clk_i (clk_i ), .en_i (clkgate_en_q), .test_en_i (1'b0 ),