From 93976c26a5d1400b4b0cafcb604beff6a659d5a8 Mon Sep 17 00:00:00 2001
From: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Date: Fri, 1 Dec 2023 10:36:52 +0100
Subject: [PATCH] [README] Update readme

---
 README.md | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 96719e765..4412208b7 100644
--- a/README.md
+++ b/README.md
@@ -97,13 +97,38 @@ make riscv_tests
 
 ## RTL Simulation
 
-To simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation:
+### Hardware dependencies
+
+The Ara repository depends on external IPs and uses Bender to handle the IP dependencies.
+To install Bender and initialize all the hardware IPs, run the following commands:
+
+```bash
+# Go to the hardware folder
+cd hardware
+# Install Bender and checkout all the IPs
+make update
+```
+
+### Patches (only once!)
+
+Note: this step is required only once, and needs to be repeated ONLY if the IP hardware dependencies are deleted and checked out again.
+
+Some of the IPs need to be patched to work with Verilator.
 
 ```bash
 # Go to the hardware folder
 cd hardware
 # Apply the patches (only need to run this once)
 make apply-patches
+```
+
+### Simulation
+
+To simulate the Ara system with ModelSim, go to the `hardware` folder, which contains all the SystemVerilog files. Use the following command to run your simulation:
+
+```bash
+# Go to the hardware folder
+cd hardware
 # Only compile the hardware without running the simulation.
 make compile
 # Run the simulation with the *hello_world* binary loaded