diff --git a/hardware/src/lane/valu.sv b/hardware/src/lane/valu.sv
index 7f2be6614..d3ce82bee 100644
--- a/hardware/src/lane/valu.sv
+++ b/hardware/src/lane/valu.sv
@@ -180,13 +180,11 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
 
   assign mask_operand_gnt = mask_operand_ready && result_queue_q[result_queue_read_pnt_q].mask && result_queue_valid_q[result_queue_read_pnt_q];
 
-  stream_register #(
+  spill_register #(
     .T(elen_t)
   ) i_mask_operand_register (
     .clk_i     (clk_i                                                                                        ),
     .rst_ni    (rst_ni                                                                                       ),
-    .clr_i     (1'b0                                                                                         ),
-    .testmode_i(1'b0                                                                                         ),
     .data_o    (mask_operand_o                                                                               ),
     .valid_o   (mask_operand_valid_o                                                                         ),
     .ready_i   (mask_operand_ready_i                                                                         ),
diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv
index 4822ce7b7..fdf10363a 100644
--- a/hardware/src/lane/vmfpu.sv
+++ b/hardware/src/lane/vmfpu.sv
@@ -245,13 +245,11 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
 
   assign mask_operand_gnt = mask_operand_ready && result_queue_q[result_queue_read_pnt_q].mask && result_queue_valid_q[result_queue_read_pnt_q];
 
-  stream_register #(
+  spill_register #(
     .T(elen_t)
   ) i_mask_operand_register (
     .clk_i     (clk_i                                                                                        ),
     .rst_ni    (rst_ni                                                                                       ),
-    .clr_i     (1'b0                                                                                         ),
-    .testmode_i(1'b0                                                                                         ),
     .data_o    (mask_operand_o                                                                               ),
     .valid_o   (mask_operand_valid_o                                                                         ),
     .ready_i   (mask_operand_ready_i                                                                         ),
diff --git a/hardware/src/sldu/sldu.sv b/hardware/src/sldu/sldu.sv
index 423ee092a..66527b442 100644
--- a/hardware/src/sldu/sldu.sv
+++ b/hardware/src/sldu/sldu.sv
@@ -239,13 +239,11 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
   logic  [NrLanes-1:0] mask_ready_q;
 
   for (genvar l = 0; l < NrLanes; l++) begin
-    stream_register #(
+    spill_register #(
       .T(strb_t)
     ) i_mask_operand_register (
       .clk_i     (clk_i           ),
       .rst_ni    (rst_ni          ),
-      .clr_i     (1'b0            ),
-      .testmode_i(1'b0            ),
       .data_o    (mask_q[l]       ),
       .valid_o   (mask_valid_q[l] ),
       .ready_i   (mask_ready_d    ),