From 82f7f5d4eb91db75453a1595dd5bcc31bbab1256 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 16 Sep 2024 11:46:47 +0200 Subject: [PATCH] [hardware] XIF - cleanup --- hardware/src/ara_ring_buffer.sv | 4 +- hardware/src/ara_xif_handler.sv | 71 ++++++++++++++++++--------------- 2 files changed, 41 insertions(+), 34 deletions(-) diff --git a/hardware/src/ara_ring_buffer.sv b/hardware/src/ara_ring_buffer.sv index 315540472..a08e25c9e 100644 --- a/hardware/src/ara_ring_buffer.sv +++ b/hardware/src/ara_ring_buffer.sv @@ -110,8 +110,8 @@ module ara_ring_buffer #( commit_d = id_mem_q[commit_id_i] + 1'b1; end - // Read - if (valid_o && !empty_o && ready_i) begin + // Read - valid_o implies a non-empty buffer + if (valid_o && ready_i) begin // Pop the head by one head_d = head_q + 1'b1; // Decrease usage diff --git a/hardware/src/ara_xif_handler.sv b/hardware/src/ara_xif_handler.sv index 1ab034b07..3ecdbf1bc 100644 --- a/hardware/src/ara_xif_handler.sv +++ b/hardware/src/ara_xif_handler.sv @@ -48,9 +48,25 @@ module ara_xif_handler #( logic csr_stall_d, csr_stall_q; logic [ID_WIDTH-1:0] csr_instr_id_d, csr_instr_id_q; - // Second dispatcher to handle pre decoding - x_resp_t core_v_xif_resp_decoder2; - x_req_t core_v_xif_req_decoder2; + // Effective commit or kill on the XIF commit intf + logic commit_ok, commit_kill; + assign commit_ok = core_v_xif_req_i.commit_valid & !core_v_xif_req_i.commit_commit_kill; + assign commit_kill = core_v_xif_req_i.commit_valid & core_v_xif_req_i.commit_commit_kill; + + // No errors at decode time for this RVV vector insn + logic xif_issue_decode_error; + assign xif_issue_decode_ok = core_v_xif_resp_decoder2.issue_resp_accept; + + // Push a new instruction from the XIF issue intf into the speculative XIF buffer + logic new_instr, pop_next_instr; + assign new_instr_valid = core_v_xif_req_i.issue_valid & core_v_xif_resp_o.issue_ready & xif_issue_decode_ok & ~csr_stall_q; + + // XIF issue buffer full + logic buffer_full; + + // XIF issue decoder to pre-decode and check for errors + x_resp_t core_v_xif_resp_decoder2; + x_req_t core_v_xif_req_decoder2; ara_pre_decoder #( .NrLanes(NrLanes), .x_req_t (x_req_t), @@ -59,28 +75,21 @@ module ara_xif_handler #( .x_issue_resp_t(x_issue_resp_t), .x_acc_resp_t(x_acc_resp_t), .csr_sync_t (csr_sync_t) - ) i_pre_decoder ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), + ) i_xif_issue_pre_decoder ( + .clk_i (clk_i ), + .rst_ni (rst_ni), // Interface with the sequencer .ara_req_ready_i (core_v_xif_req_decoder2.issue_valid), - .ara_idle_i (ara_idle ), + .ara_idle_i (ara_idle ), // XIF - .core_v_xif_req_i (core_v_xif_req_decoder2), + .core_v_xif_req_i (core_v_xif_req_decoder2 ), .core_v_xif_resp_o (core_v_xif_resp_decoder2), // CSR sync - .sync_i (core_v_xif_req_i.commit_valid && core_v_xif_req_i.commit_commit_kill), - .csr_sync_i (csr_sync_i ), - .csr_stall_o (csr_stall ) + .sync_i (commit_kill), + .csr_sync_i (csr_sync_i ), + .csr_stall_o (csr_stall ) ); - logic new_instr; - logic load_next_instr; - logic buffer_full; - - assign new_instr = core_v_xif_req_i.issue_valid && core_v_xif_resp_o.issue_ready && core_v_xif_resp_o.issue_resp_accept && !csr_block; - assign load_next_instr = instruction_ready_i && instruction_valid_o; - // Issued instruction instr_pack_t instr_to_buffer; @@ -95,24 +104,24 @@ module ara_xif_handler #( assign instr_to_buffer.is_writeback = core_v_xif_resp_o.issue_resp_writeback; // to keep track of the returned instructions - logic [ID_WIDTH-1:0] result_id; + logic [ID_WIDTH-1:0] result_id; ara_ring_buffer #( .ID_WIDTH(ID_WIDTH), .DEPTH(4), .readregflags_t(readregflags_t), .dtype(instr_pack_t) - ) i_ring_buffer ( + ) i_xif_buffer ( .clk_i (clk_i ), .rst_ni (rst_ni ), .full_o (buffer_full ), - .empty_o ( ), + .empty_o (/* unused */ ), .push_i (new_instr ), - .commit_i (core_v_xif_req_i.commit_valid && !core_v_xif_req_i.commit_commit_kill), + .commit_i (commit_ok ), .register_valid_i (core_v_xif_req_i.register_valid ), - .flush_i (core_v_xif_req_i.commit_valid && core_v_xif_req_i.commit_commit_kill), - .ready_i (load_next_instr ), - .valid_o (instruction_valid_o ), + .flush_i (commit_kill ), + .ready_i (instruction_ready_i ), + .valid_o (instruction_valid_o ), .commit_id_i (core_v_xif_req_i.commit_id ), .reg_id_i (core_v_xif_req_i.register_id ), .id_i (instr_to_buffer.id ), @@ -121,7 +130,7 @@ module ara_xif_handler #( .rs2_i (core_v_xif_req_i.register_rs[1] ), .rs_valid_i (core_v_xif_req_i.register_rs_valid ), .frm_i (core_v_xif_req_i.frm ), - .data_o (instruction_o ) + .data_o (instruction_o ) ); always_comb begin @@ -129,7 +138,6 @@ module ara_xif_handler #( core_v_xif_req_decoder2 = core_v_xif_req_i; core_v_xif_resp_o = core_v_xif_resp_i; core_v_xif_resp_o.issue_ready = 1'b0; - csr_block = 1'b0; csr_stall_d = csr_stall_q; csr_instr_id_d = csr_instr_id_q; @@ -155,10 +163,10 @@ module ara_xif_handler #( core_v_xif_req_decoder2.result_ready = core_v_xif_req_i.issue_valid; core_v_xif_req_decoder2.issue_valid = core_v_xif_req_i.issue_valid && !buffer_full; - // issue response - if (core_v_xif_req_i.issue_valid && !buffer_full && !(core_v_xif_req_i.commit_valid && core_v_xif_req_i.commit_commit_kill)) + // Issue ready if buffer has space and we are not flushing it + if (core_v_xif_req_i.issue_valid && !buffer_full && !commit_kill) begin core_v_xif_resp_o.issue_ready = 1'b1; - core_v_xif_resp_o.issue_resp_accept = core_v_xif_resp_decoder2.issue_resp_accept; + end core_v_xif_resp_o.issue_resp_writeback = core_v_xif_resp_decoder2.issue_resp_writeback; core_v_xif_resp_o.issue_resp_register_read = core_v_xif_resp_decoder2.issue_resp_register_read; core_v_xif_resp_o.issue_resp_is_vfp = core_v_xif_resp_decoder2.issue_resp_is_vfp; @@ -171,7 +179,6 @@ module ara_xif_handler #( // If we are waiting for a vsetvl to complete we need to mask the outpu of the pre decoder if (csr_stall_q) begin - csr_block = 1'b1; core_v_xif_resp_o.issue_ready = 1'b0; // If the registers for the stalling instruction are passed we can resolve the stall of the pre decoder if (core_v_xif_req_i.register_id == csr_instr_id_q && core_v_xif_req_i.register_valid) begin @@ -187,7 +194,7 @@ module ara_xif_handler #( end end - if (core_v_xif_req_i.commit_valid && core_v_xif_req_i.commit_commit_kill) begin + if (commit_kill) begin csr_stall_d = 1'b0; end