diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv index 001545d10..10b444d8c 100644 --- a/hardware/include/ara_pkg.sv +++ b/hardware/include/ara_pkg.sv @@ -963,10 +963,24 @@ package ara_pkg; logic is_exception; } addrgen_axi_req_t; + ////////////////////////// + // VRGATHER / VCOMPRESS // + ////////////////////////// - //////////////////////// - // VFREC7 & VFRSQRT7 // - /////////////////////// + // Indices are 16-bit at most because of RISC-V V VLEN limitation at 64Kibit + typedef logic [$clog2(rvv_pkg::RISCV_MAX_VLEN)-1:0] max_vlen_t; + + // During VRGATHER/VCOMPRESS, the MASKU asks for operands to the lanes + typedef struct packed { + max_vlen_t idx; + rvv_pkg::vew_e eew; + logic [4:0] vs; + logic is_last_req; + } vrgat_req_t; + + //////////////////////// + // VFREC7 & VFRSQRT7 // + /////////////////////// localparam int unsigned LUT_BITS = 7; diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv index db14bee26..b68c16751 100644 --- a/hardware/src/ara.sv +++ b/hardware/src/ara.sv @@ -333,7 +333,7 @@ module ara import ara_pkg::*; #( logic [NrLanes-1:0] masku_result_final_gnt; logic [NrLanes-1:0] masku_vrgat_req_valid; logic [NrLanes-1:0] masku_vrgat_req_ready; - vaddr_t masku_vrgat_addr; + vrgat_req_t masku_vrgat_req; for (genvar lane = 0; lane < NrLanes; lane++) begin: gen_lanes lane #( @@ -407,7 +407,7 @@ module ara import ara_pkg::*; #( .masku_result_final_gnt_o (masku_result_final_gnt[lane] ), .masku_vrgat_req_valid_i (masku_vrgat_req_valid[lane] ), .masku_vrgat_req_ready_o (masku_vrgat_req_ready[lane] ), - .masku_vrgat_addr_i (masku_vrgat_addr ), + .masku_vrgat_req_i (masku_vrgat_req ), .mask_i (mask[lane] ), .mask_valid_i (mask_valid[lane] & mask_valid_lane ), .mask_ready_o (lane_mask_ready[lane] ) @@ -602,7 +602,7 @@ module ara import ara_pkg::*; #( .masku_result_final_gnt_i(masku_result_final_gnt ), .masku_vrgat_req_valid_o (masku_vrgat_req_valid ), .masku_vrgat_req_ready_i (masku_vrgat_req_ready ), - .masku_vrgat_addr_o (masku_vrgat_addr ), + .masku_vrgat_req_o (masku_vrgat_req ), // Interface with the VFUs .mask_o (mask ), .mask_valid_o (mask_valid ), diff --git a/hardware/src/lane/lane.sv b/hardware/src/lane/lane.sv index 2653109a9..e453e2c61 100644 --- a/hardware/src/lane/lane.sv +++ b/hardware/src/lane/lane.sv @@ -99,7 +99,7 @@ module lane import ara_pkg::*; import rvv_pkg::*; #( output logic masku_result_final_gnt_o, input logic masku_vrgat_req_valid_i, output logic masku_vrgat_req_ready_o, - input vaddr_t masku_vrgat_addr_i, + input vrgat_req_t masku_vrgat_req_i, // Interface between the Mask unit and the VFUs input strb_t mask_i, input logic mask_valid_i, @@ -252,7 +252,11 @@ module lane import ara_pkg::*; import rvv_pkg::*; #( .alu_ready_i (alu_ready ), .alu_vinsn_done_i (alu_vinsn_done ), .mfpu_ready_i (mfpu_ready ), - .mfpu_vinsn_done_i (mfpu_vinsn_done ) + .mfpu_vinsn_done_i (mfpu_vinsn_done ), + // From the MASKU - for VRGATHER/VCOMPRESS + .masku_vrgat_req_valid_i(masku_vrgat_req_valid_i ), + .masku_vrgat_req_ready_o(masku_vrgat_req_ready_o ), + .masku_vrgat_req_i (masku_vrgat_req_i ) ); ///////////////////////// @@ -340,9 +344,6 @@ module lane import ara_pkg::*; import rvv_pkg::*; #( .masku_result_be_i (masku_result_be_i ), .masku_result_gnt_o (masku_result_gnt_o ), .masku_result_final_gnt_o (masku_result_final_gnt_o), - .masku_vrgat_req_valid_i (masku_vrgat_req_valid_i ), - .masku_vrgat_req_ready_o (masku_vrgat_req_ready_o ), - .masku_vrgat_addr_i (masku_vrgat_addr_i ), // Slide Unit .sldu_result_req_i (sldu_result_req_i ), .sldu_result_id_i (sldu_result_id_i ), diff --git a/hardware/src/lane/lane_sequencer.sv b/hardware/src/lane/lane_sequencer.sv index ac8559db4..d7824a219 100644 --- a/hardware/src/lane/lane_sequencer.sv +++ b/hardware/src/lane/lane_sequencer.sv @@ -41,8 +41,8 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg:: // Masku interface for vrgather/vcompress input logic masku_vrgat_req_valid_i, output logic masku_vrgat_req_ready_o, - input vaddr_t masku_vrgat_addr_i - );, + input vrgat_req_t masku_vrgat_req_i + ); //////////////////////////// // Register the request // @@ -164,20 +164,20 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg:: typedef enum logic {IDLE, REQUESTING} vrgat_state_e; vrgat_state_e vrgat_state_d, vrgat_state_q; - vaddr_t masku_vrgat_addr_q; + vrgat_req_t masku_vrgat_req_q; logic masku_vrgat_req_ready_d, masku_vrgat_req_valid_q; spill_register #( - .T ( vaddr_t ) - ) i_spill_register_vrgat_addr ( + .T ( vrgat_req_t ) + ) i_spill_register_vrgat_req ( .clk_i, .rst_ni, .valid_i (masku_vrgat_req_valid_i), .ready_o (masku_vrgat_req_ready_o), - .data_i (masku_vrgat_addr_i), + .data_i (masku_vrgat_req_i), .valid_o (masku_vrgat_req_valid_q), .ready_i (masku_vrgat_req_ready_d), - .data_o (masku_vrgat_addr_q) + .data_o (masku_vrgat_req_q) ); always_comb begin @@ -192,8 +192,10 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg:: end end REQUESTING: begin - // If the MASKU is over with VRGATHER/VCOMPRESS, return tu idle - if (masku_vrgat_end_q) begin + // Pop if the operand requester is ready to accept a request + masku_vrgat_req_ready_d = masku_vrgat_req_valid_q && !(operand_request_valid_o[MaskB]); + // If the MASKU is over with VRGATHER/VCOMPRESS, return to idle + if (masku_vrgat_req_ready_d && masku_vrgat_req_q.is_last_req) begin vrgat_state_d = IDLE; end end @@ -859,6 +861,21 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg:: default:; endcase end + + // VRGATHER and VCOMPRESS access the opreq with ad-hoc requests + if (vrgat_state_q == REQUESTING) begin + // Here, we are sure the MaskB operand_request is free + operand_request[MaskB] = '{ + vs : masku_vrgat_req_q.vs, + eew : masku_vrgat_req_q.eew, + scale_vl : 1'b0, + vl : 1, + vstart : masku_vrgat_req_q.idx, + hazard : '0, + default : '0 + }; + operand_request_push[MaskB] = masku_vrgat_req_valid_q && !(operand_request_valid_o[MaskB]); + end end: sequencer always_ff @(posedge clk_i or negedge rst_ni) begin: p_sequencer_ff diff --git a/hardware/src/lane/operand_requester.sv b/hardware/src/lane/operand_requester.sv index 6a8ebd05a..de2cc4f82 100644 --- a/hardware/src/lane/operand_requester.sv +++ b/hardware/src/lane/operand_requester.sv @@ -62,7 +62,6 @@ module operand_requester import ara_pkg::*; import rvv_pkg::*; #( input strb_t masku_result_be_i, output logic masku_result_gnt_o, output logic masku_result_final_gnt_o, - output logic masku_result_final_gnt_o, // Slide unit input logic sldu_result_req_i, input vid_t sldu_result_id_i, diff --git a/hardware/src/masku/masku.sv b/hardware/src/masku/masku.sv index 68a7dabf1..b12675768 100644 --- a/hardware/src/masku/masku.sv +++ b/hardware/src/masku/masku.sv @@ -45,7 +45,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( input logic [NrLanes-1:0] masku_result_final_gnt_i, output logic [NrLanes-1:0] masku_vrgat_req_valid_o, input logic [NrLanes-1:0] masku_vrgat_req_ready_i, - output vaddr_t masku_vrgat_addr_o, + output vrgat_req_t masku_vrgat_req_o, output logic masku_vrgat_end_o, // Interface with the VFUs output strb_t [NrLanes-1:0] mask_o, @@ -507,9 +507,6 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( //// VRGATHER / VCOMPRESS //// /////////////////////////////// - // Indices are 16-bit at most because of RISC-V V VLEN limitation at 64Kibit - typedef logic [$clog2(RISCV_MAX_VLEN)-1:0] max_vlen_t; - // How deep are the VRGATHER/VCOMPRESS address/index FIFOs? localparam int unsigned VrgatFifoDepth = 3; @@ -524,43 +521,55 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( logic vcompress_bit; // FIFO-related signals - logic vrgat_addr_fifo_empty, vrgat_addr_fifo_full, vrgat_addr_fifo_push, vrgat_addr_fifo_pop; + logic vrgat_req_fifo_empty, vrgat_req_fifo_full, vrgat_req_fifo_push, vrgat_req_fifo_pop; logic vrgat_idx_fifo_empty, vrgat_idx_fifo_full, vrgat_idx_fifo_push, vrgat_idx_fifo_pop; - max_vlen_t vrgat_idx_d, vrgat_idx_q; - vaddr_t vrgat_addr_d, vrgat_addr_q; + max_vlen_t vrgat_req_idx_d, vrgat_req_idx_q; + vrgat_req_t vrgat_req_d, vrgat_req_q; + + vew_e vrgat_req_eew_d; + logic [4:0] vrgat_req_vs_d; + logic vrgat_req_is_last_req_d; + + assign vrgat_req_eew_d = vinsn_issue.op == VRGATHEREI16 ? EW16 : vinsn_issue.vtype.vsew; + assign vrgat_req_vs_d = vinsn_issue.vs1; // Build the address from the index - assign vrgat_addr_d = vaddr(vinsn_issue.vs2, NrLanes, VLEN) + vrgat_idx_d; + assign vrgat_req_d = { + vrgat_req_idx_d, + vrgat_req_eew_d, + vrgat_req_vs_d, + vrgat_req_is_last_req_d + }; // Broadcast the address request to all the lanes - assign masku_vrgat_addr_o = vrgat_addr_q; + assign masku_vrgat_req_o = vrgat_req_q; // A mask for the valid to keep up only the unshaked ones and hide the others - logic [NrLanes-1:0] vrgat_addr_valid_mask_d, vrgat_addr_valid_mask_q; + logic [NrLanes-1:0] vrgat_req_valid_mask_d, vrgat_req_valid_mask_q; // Synchronize the handshake between MASKU and lanes since we are making a single request // to all the lanes, which can also answer individually always_comb begin // Don't do anything by default - vrgat_addr_fifo_pop = 1'b0; + vrgat_req_fifo_pop = 1'b0; // Don't hide the valids by defaults - vrgat_addr_valid_mask_d = vrgat_addr_valid_mask_q; + vrgat_req_valid_mask_d = vrgat_req_valid_mask_q; for (int lane = 0; lane < NrLanes; lane++) begin // Valid address request if the address fifo is not empty and if the valid is not masked - masku_vrgat_req_valid_o[lane] = ~vrgat_addr_fifo_empty & ~vrgat_addr_valid_mask_q[lane]; + masku_vrgat_req_valid_o[lane] = ~vrgat_req_fifo_empty & ~vrgat_req_valid_mask_q[lane]; // Mask the next valid on this lane if the lane is handshaking - vrgat_addr_valid_mask_d[lane] = masku_vrgat_req_ready_i[lane]; + vrgat_req_valid_mask_d[lane] = masku_vrgat_req_ready_i[lane]; end // Don't mask if all the lanes have handshaked - if (&masku_vrgat_req_ready_i) vrgat_addr_valid_mask_d = '0; + if (&masku_vrgat_req_ready_i) vrgat_req_valid_mask_d = '0; // Pop the current address if all the lanes have handshaked it - if (&(masku_vrgat_req_ready_i | vrgat_addr_valid_mask_q)) vrgat_addr_fifo_pop = 1'b1; + if (&(masku_vrgat_req_ready_i | vrgat_req_valid_mask_q)) vrgat_req_fifo_pop = 1'b1; end // Overflow after 16-bits @@ -581,28 +590,28 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( .full_o (vrgat_idx_fifo_full ), .empty_o (vrgat_idx_fifo_empty ), .usage_o (/* unused */ ), - .data_i ({vrgat_idx_oor_d, vrgat_idx_d}), + .data_i ({vrgat_idx_oor_d, vrgat_req_idx_d}), .push_i (vrgat_idx_fifo_push ), - .data_o ({vrgat_idx_oor_q, vrgat_idx_q}), + .data_o ({vrgat_idx_oor_q, vrgat_req_idx_q}), .pop_i (vrgat_idx_fifo_pop ) ); // Send the address request to the lanes fifo_v3 #( - .dtype(vaddr_t ), + .dtype(vrgat_req_t ), .DEPTH(VrgatFifoDepth) - ) i_fifo_vrgat_addr ( + ) i_fifo_vrgat_req ( .clk_i, .rst_ni, .flush_i (1'b0), .testmode_i(1'b0), - .full_o (vrgat_addr_fifo_full ), - .empty_o (vrgat_addr_fifo_empty), + .full_o (vrgat_req_fifo_full ), + .empty_o (vrgat_req_fifo_empty), .usage_o (/* unused */ ), - .data_i (vrgat_addr_d ), - .push_i (vrgat_addr_fifo_push ), - .data_o (vrgat_addr_q ), - .pop_i (vrgat_addr_fifo_pop ) + .data_i (vrgat_req_d ), + .push_i (vrgat_req_fifo_push ), + .data_o (vrgat_req_q ), + .pop_i (vrgat_req_fifo_pop ) ); //////////////////////////// @@ -801,22 +810,22 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( // Extract the correct elements vrgat_res = '1; // Default assignment - vrgat_buf = masku_operand_vd_seq[vrgat_idx_q[idx_width(NrLanes*ELENB/8)-1:0] * 64 +: 64]; // Default assignment + vrgat_buf = masku_operand_vd_seq[vrgat_req_idx_q[idx_width(NrLanes*ELENB/8)-1:0] * 64 +: 64]; // Default assignment unique case (vinsn_issue.vtype.vsew) EW8: begin - vrgat_buf[0 +: 8] = masku_operand_vd_seq[vrgat_idx_q[idx_width(NrLanes*ELENB/1)-1:0] * 8 +: 8]; + vrgat_buf[0 +: 8] = masku_operand_vd_seq[vrgat_req_idx_q[idx_width(NrLanes*ELENB/1)-1:0] * 8 +: 8]; vrgat_res[out_valid_cnt_q[idx_width(NrLanes*ELENB/1)-1:0] * 8 +: 8] = vrgat_idx_oor_q ? '0 : vrgat_buf[0 +: 8]; end EW16: begin - vrgat_buf[0 +: 16] = masku_operand_vd_seq[vrgat_idx_q[idx_width(NrLanes*ELENB/2)-1:0] * 16 +: 16]; + vrgat_buf[0 +: 16] = masku_operand_vd_seq[vrgat_req_idx_q[idx_width(NrLanes*ELENB/2)-1:0] * 16 +: 16]; vrgat_res[out_valid_cnt_q[idx_width(NrLanes*ELENB/2)-1:0] * 16 +: 16] = vrgat_idx_oor_q ? '0 : vrgat_buf[0 +: 16]; end EW32: begin - vrgat_buf[0 +: 32] = masku_operand_vd_seq[vrgat_idx_q[idx_width(NrLanes*ELENB/4)-1:0] * 32 +: 32]; + vrgat_buf[0 +: 32] = masku_operand_vd_seq[vrgat_req_idx_q[idx_width(NrLanes*ELENB/4)-1:0] * 32 +: 32]; vrgat_res[out_valid_cnt_q[idx_width(NrLanes*ELENB/4)-1:0] * 32 +: 32] = vrgat_idx_oor_q ? '0 : vrgat_buf[0 +: 32]; end default: begin // EW64 - vrgat_buf[0 +: 64] = masku_operand_vd_seq[vrgat_idx_q[idx_width(NrLanes*ELENB/8)-1:0] * 64 +: 64]; + vrgat_buf[0 +: 64] = masku_operand_vd_seq[vrgat_req_idx_q[idx_width(NrLanes*ELENB/8)-1:0] * 64 +: 64]; vrgat_res[out_valid_cnt_q[idx_width(NrLanes*ELENB/8)-1:0] * 64 +: 64] = vrgat_idx_oor_q ? '0 : vrgat_buf[0 +: 64]; end endcase @@ -1091,9 +1100,9 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( vrgat_cnt_d = vrgat_cnt_q; - vrgat_idx_d = '0; + vrgat_req_idx_d = '0; vrgat_idx_fifo_push = 1'b0; - vrgat_addr_fifo_push = 1'b0; + vrgat_req_fifo_push = 1'b0; // Track if an index overflow occurred past the 16 sampled bits vrgat_idx_overflow = 1'b0; @@ -1103,6 +1112,8 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( vcompress_bit = 1'b0; + vrgat_req_is_last_req_d = 1'b0; + // Control counters in the pre-issue phase if (vinsn_issue_valid) begin unique case (vinsn_issue.op) @@ -1110,14 +1121,14 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( // Select the current enable bit vcompress_bit = masku_operand_alu_seq[in_m_ready_cnt_q[idx_width(NrLanes*DataWidth)-1:0]]; // Select the current index - vrgat_idx_d = vrgat_cnt_q; - if (masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_addr_fifo_full) begin + vrgat_req_idx_d = vrgat_cnt_q; + if (masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_req_fifo_full) begin // Check vrgat_m_seq_bit: we can use this since VRGATHER and VCOMPRESS are mutually exclusive // and the masku_operand_m is used in different ways if (vcompress_bit) begin // Push this index and address if the fifos are free and if the mask bit is set vrgat_idx_fifo_push = 1'b1; - vrgat_addr_fifo_push = 1'b1; + vrgat_req_fifo_push = 1'b1; end end end @@ -1141,40 +1152,40 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( if (vinsn_issue.op == VRGATHER) begin unique case (vinsn_issue.vtype.vsew) EW8: begin - vrgat_idx_d = {8'b0, masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/8)-1:0] * 8 +: 8]}; + vrgat_req_idx_d = {8'b0, masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/8)-1:0] * 8 +: 8]}; end EW16: begin - vrgat_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/16)-1:0] * 16 +: 16]; + vrgat_req_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/16)-1:0] * 16 +: 16]; end EW32: begin - vrgat_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/32)-1:0] * 32 +: 16]; + vrgat_req_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/32)-1:0] * 32 +: 16]; vrgat_idx_overflow = |masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/32)-1:0] * 32 + 16 +: 32 - 16]; end default: begin // EW64 - vrgat_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/64)-1:0] * 64 +: 16]; + vrgat_req_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/64)-1:0] * 64 +: 16]; vrgat_idx_overflow = |masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/64)-1:0] * 64 + 16 +: 64 - 16]; end endcase end else begin // VRGATHEREI16: treat the index as a 16-bit number - vrgat_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/16)-1:0] * 16 +: 16]; + vrgat_req_idx_d = masku_operand_alu_seq[in_ready_cnt_q[idx_width(NrLanes*DataWidth/16)-1:0] * 16 +: 16]; end // VRGATHER.v[x|i] splats one scalar into Vd. The scalar is not truncated if (vinsn_issue.use_scalar_op) begin - vrgat_idx_d = vinsn_issue.scalar_op[15:0]; + vrgat_req_idx_d = vinsn_issue.scalar_op[15:0]; vrgat_idx_overflow = |vinsn_issue.scalar_op[16 +: ELEN - 16]; end - vrgat_idx_oor_d = (vrgat_idx_d >= vlmax) | vrgat_idx_overflow; + vrgat_idx_oor_d = (vrgat_req_idx_d >= vlmax) | vrgat_idx_overflow; // Proceed if the FIFOs are not full - if (masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_addr_fifo_full) begin + if (masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_req_fifo_full) begin // Push the index no matter what vrgat_idx_fifo_push = 1'b1; // Request to the lanes only if the index is within range if (!vrgat_idx_oor_d) begin - vrgat_addr_fifo_push = 1'b1; + vrgat_req_fifo_push = 1'b1; end end end @@ -1183,13 +1194,14 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( end // Handle the counters - if (vinsn_issue.op inside {[VRGATHER:VCOMPRESS]} && masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_addr_fifo_full) begin + if (vinsn_issue.op inside {[VRGATHER:VCOMPRESS]} && masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_req_fifo_full) begin // Count up if we could process the current mask bit vrgat_cnt_d = vrgat_cnt_q + 1; // End of the pre-issue phase if ((vrgat_cnt_q[idx_width(NrLanes*DataWidth)-1:0] == in_ready_threshold_q) || (vrgat_cnt_q == vinsn_issue.vl)) begin masku_operand_alu_ready = '1; + vrgat_req_is_last_req_d = 1'b1; if (vrgat_cnt_q == vinsn_issue.vl) vrgat_cnt_d = '0; end end @@ -1606,7 +1618,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( found_one_q <= '0; be_viota_seq_q <= '1; // Default: write be_vrgat_seq_q <= '1; // Default: write - vrgat_addr_valid_mask_q <= '0; + vrgat_req_valid_mask_q <= '0; vrgat_cnt_q <= '0; end else begin vinsn_running_q <= vinsn_running_d; @@ -1628,7 +1640,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #( found_one_q <= found_one_d; be_viota_seq_q <= be_viota_seq_d; be_vrgat_seq_q <= be_vrgat_seq_d; - vrgat_addr_valid_mask_q <= vrgat_addr_valid_mask_d; + vrgat_req_valid_mask_q <= vrgat_req_valid_mask_d; vrgat_cnt_q <= vrgat_cnt_d; end end