From 80af4d170966312fbcbe99fcd2ada2111d9f5980 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Tue, 18 Jun 2024 18:17:06 +0200 Subject: [PATCH] [hardware] Fix rebase errors --- hardware/include/ara_pkg.sv | 4 ++++ hardware/src/ara.sv | 29 +++++++++++++---------------- hardware/src/ara_dispatcher.sv | 4 ++-- hardware/src/ara_system.sv | 12 ++++++------ hardware/src/vlsu/addrgen.sv | 2 +- hardware/src/vlsu/vlsu.sv | 2 +- hardware/tb/ara_testharness.sv | 8 ++++---- 7 files changed, 31 insertions(+), 30 deletions(-) diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv index b8c01e118..77d248cf1 100644 --- a/hardware/include/ara_pkg.sv +++ b/hardware/include/ara_pkg.sv @@ -243,8 +243,12 @@ package ara_pkg; ///////////////////////////// // Use Ariane's accelerator interface. + typedef acc_pkg::cva6_to_acc_t cva6_to_acc_t; + typedef acc_pkg::acc_to_cva6_t acc_to_cva6_t; typedef acc_pkg::accelerator_req_t accelerator_req_t; typedef acc_pkg::accelerator_resp_t accelerator_resp_t; + typedef acc_pkg::acc_mmu_req_t acc_mmu_req_t; + typedef acc_pkg::acc_mmu_resp_t acc_mmu_resp_t; ///////////////////////// // Backend interface // diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv index 1680d23d4..9a969a326 100644 --- a/hardware/src/ara.sv +++ b/hardware/src/ara.sv @@ -38,12 +38,9 @@ module ara import ara_pkg::*; #( input logic scan_data_i, output logic scan_data_o, - // CSR input - input logic en_ld_st_translation_i, - // Interface with Ariane - input cva6_to_acc_t acc_req_i, - output acc_to_cva6_t acc_resp_o, + input cva6_to_acc_t acc_req_i, + output acc_to_cva6_t acc_resp_o, // AXI interface output axi_req_t axi_req_o, input axi_resp_t axi_resp_i @@ -94,8 +91,8 @@ module ara import ara_pkg::*; #( .clk_i (clk_i ), .rst_ni (rst_ni ), // Interface with Ariane - .acc_req_i (acc_req_i ), - .acc_resp_o (acc_resp_o ), + .acc_req_i (acc_req_i.acc_req ), + .acc_resp_o (acc_resp_o.acc_resp), // Interface with the sequencer .ara_req_o (ara_req ), .ara_req_valid_o (ara_req_valid ), @@ -364,15 +361,15 @@ module ara import ara_pkg::*; #( // CSR input .en_ld_st_translation_i (acc_req_i.acc_mmu_en ), // Interface with CVA6's sv39 MMU - .mmu_misaligned_ex_o (acc_resp_o.mmu_misaligned_ex_o ), - .mmu_req_o (acc_resp_o.mmu_req_o ), - .mmu_vaddr_o (acc_resp_o.mmu_vaddr_o ), - .mmu_is_store_o (acc_resp_o.mmu_is_store_o ), - .mmu_dtlb_hit_i (acc_req_i.mmu_dtlb_hit_i ), - .mmu_dtlb_ppn_i (acc_req_i.mmu_dtlb_ppn_i ), - .mmu_valid_i (acc_req_i.mmu_valid_i ), - .mmu_paddr_i (acc_req_i.mmu_paddr_i ), - .mmu_exception_i (acc_req_i.mmu_exception_i ), + .mmu_misaligned_ex_o (acc_resp_o.acc_mmu_req.acc_mmu_misaligned_ex ), + .mmu_req_o (acc_resp_o.acc_mmu_req.acc_mmu_req ), + .mmu_vaddr_o (acc_resp_o.acc_mmu_req.acc_mmu_vaddr ), + .mmu_is_store_o (acc_resp_o.acc_mmu_req.acc_mmu_is_store ), + .mmu_dtlb_hit_i (acc_req_i.acc_mmu_resp.acc_mmu_dtlb_hit ), + .mmu_dtlb_ppn_i (acc_req_i.acc_mmu_resp.acc_mmu_dtlb_ppn ), + .mmu_valid_i (acc_req_i.acc_mmu_resp.acc_mmu_valid ), + .mmu_paddr_i (acc_req_i.acc_mmu_resp.acc_mmu_paddr ), + .mmu_exception_i (acc_req_i.acc_mmu_resp.acc_mmu_exception ), // Load unit .ldu_result_req_o (ldu_result_req ), .ldu_result_addr_o (ldu_result_addr ), diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv index 964463e0d..93951cd9b 100644 --- a/hardware/src/ara_dispatcher.sv +++ b/hardware/src/ara_dispatcher.sv @@ -21,8 +21,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( input logic clk_i, input logic rst_ni, // Interfaces with Ariane - input cva6_to_acc_t acc_req_i, - output acc_to_cva6_t acc_resp_o, + input accelerator_req_t acc_req_i, + output accelerator_resp_t acc_resp_o, // Interface with Ara's backend output ara_req_t ara_req_o, output logic ara_req_valid_o, diff --git a/hardware/src/ara_system.sv b/hardware/src/ara_system.sv index 64043626c..fae39e7c4 100644 --- a/hardware/src/ara_system.sv +++ b/hardware/src/ara_system.sv @@ -91,13 +91,13 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #( assign hart_id = {'0, hart_id_i}; // Pack invalidation interface into acc interface - accelerator_resp_t acc_resp_pack; + acc_to_cva6_t acc_resp_pack; always_comb begin : pack_inval - acc_resp_pack = acc_resp; - acc_resp_pack.inval_valid = inval_valid; - acc_resp_pack.inval_addr = inval_addr; - inval_ready = acc_req.inval_ready; - acc_cons_en = acc_req.acc_cons_en; + acc_resp_pack = acc_resp; + acc_resp_pack.acc_resp.inval_valid = inval_valid; + acc_resp_pack.acc_resp.inval_addr = inval_addr; + inval_ready = acc_req.acc_req.inval_ready; + acc_cons_en = acc_req.acc_req.acc_cons_en; end `ifdef IDEAL_DISPATCHER diff --git a/hardware/src/vlsu/addrgen.sv b/hardware/src/vlsu/addrgen.sv index d9307d0b5..4ab7c9a7f 100644 --- a/hardware/src/vlsu/addrgen.sv +++ b/hardware/src/vlsu/addrgen.sv @@ -30,7 +30,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #( input logic en_ld_st_translation_i, // Interface with CVA6's sv39 MMU // This is everything the MMU can provide, it might be overcomplete for Ara and some signals be useless - output ariane_pkg::exception_t mmu_misaligned_ex_o, + output logic mmu_misaligned_ex_o, output logic mmu_req_o, // request address translation output logic [riscv::VLEN-1:0] mmu_vaddr_o, // virtual address out output logic mmu_is_store_o, // the translation is requested by a store diff --git a/hardware/src/vlsu/vlsu.sv b/hardware/src/vlsu/vlsu.sv index 1826dbec2..c89027817 100644 --- a/hardware/src/vlsu/vlsu.sv +++ b/hardware/src/vlsu/vlsu.sv @@ -66,7 +66,7 @@ module vlsu import ara_pkg::*; import rvv_pkg::*; #( // Interface with CVA6's sv39 MMU // This is everything the MMU can provide, it might be overcomplete for Ara and some signals be useless - output ariane_pkg::exception_t mmu_misaligned_ex_o, + output logic mmu_misaligned_ex_o, output logic mmu_req_o, // request address translation output logic [riscv::VLEN-1:0] mmu_vaddr_o, // virtual address out output logic mmu_is_store_o, // the translation is requested by a store diff --git a/hardware/tb/ara_testharness.sv b/hardware/tb/ara_testharness.sv index b50d018b4..061e31c7b 100644 --- a/hardware/tb/ara_testharness.sv +++ b/hardware/tb/ara_testharness.sv @@ -153,7 +153,7 @@ module ara_testharness #( // If disabled if (!runtime_cnt_en_q) // Start only if the software allowed the enable and we detect the first V instruction - runtime_cnt_en_d = i_ara_soc.i_system.i_ara.acc_req_i.req_valid & cnt_en_mask; + runtime_cnt_en_d = i_ara_soc.i_system.i_ara.acc_req_i.acc_req.req_valid & cnt_en_mask; // If enabled if (runtime_cnt_en_q) // Stop counting only if the software disabled the counter and Ara returned idle @@ -177,14 +177,14 @@ module ara_testharness #( runtime_to_be_updated_d = runtime_to_be_updated_q; // Assert the update flag upon a new valid vector instruction - if (!runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.acc_req_i.req_valid) begin + if (!runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.acc_req_i.acc_req.req_valid) begin runtime_to_be_updated_d = 1'b1; end // Update the internal runtime and reset the update flag if (runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.ara_idle && - !i_ara_soc.i_system.i_ara.acc_req_i.req_valid) begin + !i_ara_soc.i_system.i_ara.acc_req_i.acc_req.req_valid) begin runtime_buf_d = runtime_cnt_q; runtime_to_be_updated_d = 1'b0; end @@ -240,7 +240,7 @@ module ara_testharness #( // Update the internal runtime and reset the update flag if (runtime_to_be_updated_q && i_ara_soc.i_system.i_ara.ara_idle && - !i_ara_soc.i_system.i_ara.acc_req_i.req_valid) begin + !i_ara_soc.i_system.i_ara.acc_req_i.acc_req.req_valid) begin dcache_stall_buf_d = dcache_stall_cnt_q; icache_stall_buf_d = icache_stall_cnt_q; sb_full_buf_d = sb_full_cnt_q;