diff --git a/hardware/include/ara/ara.svh b/hardware/include/ara/ara.svh index a2c7c6cbc..bdbaea34b 100644 --- a/hardware/include/ara/ara.svh +++ b/hardware/include/ara/ara.svh @@ -19,11 +19,7 @@ // Structs in ports of hierarchical modules are not supported in Verilator // --> Flatten them for Verilator `define STRUCT_PORT_BITS(bits) \ - `ifndef VERILATOR \ - struct_t \ - `else \ logic[bits-1:0] \ - `endif // Create a flattened vector of a struct. Make sure the first dimension is // the dimension into the vector of struct types and not the struct itself. diff --git a/hardware/src/lane/lane.sv b/hardware/src/lane/lane.sv index d3ac6c5f3..a27f2bc4d 100644 --- a/hardware/src/lane/lane.sv +++ b/hardware/src/lane/lane.sv @@ -213,6 +213,12 @@ module lane import ara_pkg::*; import rvv_pkg::*; #( logic mfpu_ready; logic [NrVInsn-1:0] mfpu_vinsn_done; + // Additional signals to please Verilator's hierarchical verilation + pe_req_t pe_req; + pe_resp_t pe_resp; + assign pe_req = pe_req_i; + assign pe_resp_o = pe_resp; + lane_sequencer #( .NrLanes (NrLanes ), .pe_req_t (pe_req_t ), @@ -224,11 +230,11 @@ module lane import ara_pkg::*; import rvv_pkg::*; #( .rst_ni (rst_ni ), .lane_id_i (lane_id_i ), // Interface with the main sequencer - .pe_req_i (pe_req_i ), + .pe_req_i (pe_req ), .pe_req_valid_i (pe_req_valid_i ), .pe_vinsn_running_i (pe_vinsn_running_i ), .pe_req_ready_o (pe_req_ready_o ), - .pe_resp_o (pe_resp_o ), + .pe_resp_o (pe_resp ), // Interface with the operand requesters .operand_request_o (operand_request ), .operand_request_valid_o(operand_request_valid),