diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index 149cc6858..98ebc882c 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -2722,11 +2722,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
             // Check for segment loads
             if (ara_req.nf != 3'b000) begin
-              // This is a segment load instruction
-              is_segment_mem_op = 1'b1;
-              // Wait for idle not to mess with load/store_complete_i
-              // since the segment sequencer filters these signals
-              if (!segment_micro_op_on) state_d = WAIT_IDLE;
+              if (ara_idle_i || segment_micro_op_on) begin
+                // This is a segment load instruction
+                is_segment_mem_op = 1'b1;
+              end else begin
+                // Wait for idle not to mess with pending load/store_complete_i
+                // since the segment sequencer filters these signals
+                ara_req_valid = 1'b0;
+                state_d = WAIT_IDLE;
+              end
               // Check that EMUL * NFIELDS <= 8
               if (!ara_req.emul[2]) begin
                 // emul >= 1
@@ -2945,11 +2949,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
             // Check for segment stores
             if (ara_req.nf != 3'b000) begin
-              // This is a segment store instruction
-              is_segment_mem_op = 1'b1;
-              // Wait for idle not to mess with load/store_complete_i
-              // since the segment sequencer filters these signals
-              if (!segment_micro_op_on) state_d = WAIT_IDLE;
+              if (ara_idle_i || segment_micro_op_on) begin
+                // This is a segment store instruction
+                is_segment_mem_op = 1'b1;
+              end else begin
+                // Wait for idle not to mess with load/store_complete_i
+                // since the segment sequencer filters these signals
+                ara_req_valid = 1'b0;
+                state_d = WAIT_IDLE;
+              end
               // Check that EMUL * NFIELDS <= 8
               if (!ara_req.emul[2]) begin
                 // emul >= 1