diff --git a/hardware/Makefile b/hardware/Makefile
index 6187f3169..5963a0ffb 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -188,6 +188,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
 # Verilate the design
 	$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \
   -GNrLanes=$(nr_lanes)                                                         \
+  -GVLEN=$(vlen)                                                                \
   -O3                                                                           \
   -Wno-fatal                                                                    \
   -Wno-PINCONNECTEMPTY                                                          \
diff --git a/hardware/tb/ara_tb_verilator.sv b/hardware/tb/ara_tb_verilator.sv
index 09befa5f4..81f70ad8b 100644
--- a/hardware/tb/ara_tb_verilator.sv
+++ b/hardware/tb/ara_tb_verilator.sv
@@ -7,7 +7,8 @@
 // Description: Top level testbench module for Verilator.
 
 module ara_tb_verilator #(
-    parameter int unsigned NrLanes = 0
+    parameter int unsigned NrLanes = 0,
+    parameter int unsigned VLEN    = 0
   )(
     input  logic        clk_i,
     input  logic        rst_ni,
@@ -27,6 +28,7 @@ module ara_tb_verilator #(
 
   ara_testharness #(
     .NrLanes     (NrLanes         ),
+    .VLEN        (VLEN            ),
     .AxiAddrWidth(AxiAddrWidth    ),
     .AxiDataWidth(AxiWideDataWidth)
   ) dut (