From 20ae7d153af9c9f956ebdf1262ca2e2dc6a503a3 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 6 Sep 2024 15:37:53 +0200 Subject: [PATCH] [hardware] :art: adjust vertical alignment --- hardware/src/accel_dispatcher_ideal.sv | 10 +- hardware/src/ara.sv | 32 +-- hardware/src/ara_dispatcher.sv | 4 +- hardware/src/ara_ring_buffer.sv | 306 ++++++++++++------------- hardware/src/ara_xif_handler.sv | 62 ++--- 5 files changed, 207 insertions(+), 207 deletions(-) diff --git a/hardware/src/accel_dispatcher_ideal.sv b/hardware/src/accel_dispatcher_ideal.sv index b439583fb..a59641ead 100644 --- a/hardware/src/accel_dispatcher_ideal.sv +++ b/hardware/src/accel_dispatcher_ideal.sv @@ -127,7 +127,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; #( if (!rst_ni) begin perf_cnt_q <= '0; was_reset <= 1'b1; - end else begin + end else begin perf_cnt_q <= perf_cnt_d; end end @@ -209,7 +209,7 @@ endmodule acc_req_o.req_valid = 1'b0; // Flush the answer - acc_req_o.resp_ready = 1'b1; + acc_req_o.resp_ready = 1'b1; acc_req_o = '0; acc_req_o.frm = fpnew_pkg::RNE; @@ -252,9 +252,9 @@ endmodule $display("Start counting..."); // Loop until the last instruction is dispatched and until ara is idle again while (i_system.acc_req_valid || !i_system.i_ara.ara_idle) begin - perf_cnt_d = perf_cnt_q + 1; + perf_cnt_d = perf_cnt_q + 1; @(negedge clk_i); - end + end $display("Stop counting."); perf_cnt_d = perf_cnt_q; $display("[cycles]: %d", int'(perf_cnt_q)); @@ -265,7 +265,7 @@ endmodule always_ff @(posedge clk_i, negedge rst_ni) begin : p_perf_cnt_ideal if (!rst_ni) begin perf_cnt_q <= '0; - end else begin + end else begin perf_cnt_q <= perf_cnt_d; end end diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv index c433fd126..8f1503c1c 100644 --- a/hardware/src/ara.sv +++ b/hardware/src/ara.sv @@ -16,6 +16,15 @@ module ara import ara_pkg::*; #( parameter fpext_support_e FPExtSupport = FPExtSupportEnable, // Support for fixed-point data types parameter fixpt_support_e FixPtSupport = FixedPointEnable, + // X-Interface + parameter type readregflags_t = logic, + parameter type writeregflags_t = logic, + parameter type x_req_t = logic, + parameter type x_resp_t = logic, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_result_t = logic, + parameter type x_acc_resp_t = logic, // AXI Interface parameter int unsigned AxiDataWidth = 0, parameter int unsigned AxiAddrWidth = 0, @@ -33,14 +42,6 @@ module ara import ara_pkg::*; #( parameter int unsigned HARTID_WIDTH = ariane_pkg::NR_RGPR_PORTS, parameter int unsigned ID_WIDTH = ariane_pkg::TRANS_ID_BITS, - parameter type readregflags_t = logic, - parameter type writeregflags_t = logic, - parameter type x_req_t = core_v_xif_pkg::x_req_t, - parameter type x_resp_t = core_v_xif_pkg::x_resp_t, - parameter type x_issue_req_t = core_v_xif_pkg::x_issue_req_t, - parameter type x_issue_resp_t = core_v_xif_pkg::x_issue_resp_t, - parameter type x_result_t = core_v_xif_pkg::x_result_t, - parameter type x_acc_resp_t = core_v_xif_pkg::x_acc_resp_t ) ( // Clock and Reset input logic clk_i, @@ -74,7 +75,6 @@ module ara import ara_pkg::*; #( localparam int unsigned StrbWidth = DataWidth / 8; typedef logic [StrbWidth-1:0] strb_t; - ////////////////// // Dispatcher // ////////////////// @@ -132,13 +132,13 @@ module ara import ara_pkg::*; #( logic instruction_ready; ara_dispatcher #( - .NrLanes(NrLanes), + .NrLanes (NrLanes ), .instr_pack_t(instr_pack_t), - .x_req_t (x_req_t), - .x_resp_t (x_resp_t), - .x_result_t (x_result_t), + .x_req_t (x_req_t ), + .x_resp_t (x_resp_t ), + .x_result_t (x_result_t ), .x_acc_resp_t(x_acc_resp_t), - .csr_sync_t (csr_sync_t) + .csr_sync_t (csr_sync_t ) ) i_dispatcher ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -214,7 +214,7 @@ module ara import ara_pkg::*; #( // Sequencer // ///////////////// - // Interface with the PEs + // Interface with the PEs pe_req_t pe_req; logic pe_req_valid; logic [NrPEs-1:0] pe_req_ready; @@ -577,4 +577,4 @@ module ara import ara_pkg::*; #( $error( "[ara] Cannot support half-precision floating-point on Ara if Ariane does not support it."); -endmodule : ara \ No newline at end of file +endmodule : ara diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv index 9ee655f53..812b2bf55 100644 --- a/hardware/src/ara_dispatcher.sv +++ b/hardware/src/ara_dispatcher.sv @@ -16,7 +16,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( parameter fpext_support_e FPExtSupport = FPExtSupportEnable, // Support for fixed-point data types parameter fixpt_support_e FixPtSupport = FixedPointEnable, - + // X-Interface parameter type instr_pack_t = riscv::instruction_t, parameter type x_req_t = core_v_xif_pkg::x_req_t, parameter type x_resp_t = core_v_xif_pkg::x_resp_t, @@ -3282,4 +3282,4 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #( assign csr_sync_o.vxsat = vxsat_d; assign csr_sync_o.vxrm = vxrm_d; -endmodule : ara_dispatcher \ No newline at end of file +endmodule : ara_dispatcher diff --git a/hardware/src/ara_ring_buffer.sv b/hardware/src/ara_ring_buffer.sv index c22e47222..da1f1f877 100644 --- a/hardware/src/ara_ring_buffer.sv +++ b/hardware/src/ara_ring_buffer.sv @@ -8,158 +8,158 @@ module ara_ring_buffer #( - parameter int unsigned ID_WIDTH = 8, - parameter int unsigned DEPTH = 1, // Make sure that there are never more ids stored then the depth of the buffer - parameter type readregflags_t = logic, - parameter type dtype = logic, - // DO NOT OVERWRITE THIS PARAMETER - parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 - ) ( - // Clock and Reset - input logic clk_i, - input logic rst_ni, - // State information - output logic full_o, - output logic empty_o, - // Control information - input logic push_i, - input logic commit_i, - input logic register_valid_i, - input logic flush_i, - output logic valid_o, - input logic ready_i, - // Data - input logic [ID_WIDTH-1:0] commit_id_i, - input logic [ID_WIDTH-1:0] reg_id_i, - input logic [ID_WIDTH-1:0] id_i, - input dtype data_i, - // Register information - input logic [riscv::XLEN-1:0] rs1_i, - input logic [riscv::XLEN-1:0] rs2_i, - input readregflags_t rs_valid_i, - input fpnew_pkg::roundmode_e frm_i, - // Instruction information - output dtype data_o - ); - // Clock gating control - logic gate_clock; - // Memory - dtype [DEPTH-1:0] mem_d, mem_q; - logic [2**ID_WIDTH-1:0][ADDR_DEPTH-1:0] id_mem_d, id_mem_q; - // Pointer to indicate head and tail - logic [ADDR_DEPTH-1:0] head_d, head_q; - logic [ADDR_DEPTH-1:0] tail_d, tail_q; - // Pointer to indicate the commitable instructions - logic [ADDR_DEPTH-1:0] commit_d, commit_q; - // Usage indicator - logic [ADDR_DEPTH:0] usage_d, usage_q; - logic [ADDR_DEPTH:0] usage; - logic [ADDR_DEPTH-1:0] usage_cap; - - - // assign full_o = (tail_q+1'b1 == head_q) ? 1'b1 : 1'b0; - // assign empty_o = (tail_q == head_q) ? 1'b1 : 1'b0; - assign full_o = (usage_q == DEPTH[$clog2(DEPTH):0]); - assign empty_o = (usage_q == '0); - - - assign valid_o = (mem_q[head_q].rs_valid != '0 || mem_d[head_q].rs_valid != '0) && !(head_q == commit_q && head_q == commit_d) && !(empty_o); // (mem_q[head_q].rs_valid == mem_q[head_q].register_read) - // (mem_q[head_q].rs_valid != '0 && mem_d[head_q].rs_valid != '0) && - - - // Read and write logic - always_comb begin - // Default assignment - mem_d = mem_q; - id_mem_d = id_mem_q; - head_d = head_q; - tail_d = tail_q; - commit_d = commit_q; - usage_d = usage_q; - usage = '0; - usage_cap = '0; - gate_clock = 1'b1; - - // Write - if (push_i && ~full_o) begin - // Un-gate the clock - gate_clock = 1'b0; - // Write to mem - mem_d[tail_q] = data_i; - // Link the tail id to id_i - id_mem_d[id_i] = tail_q; - // Push the tail by one - tail_d = tail_q + 1'b1; - // Increment usage - usage = usage_q + 1'b1; - usage_d = usage; - end - - // Write Register information - if (register_valid_i) begin - // Un-gate the clock - gate_clock = 1'b0; - // Write to mem - mem_d[id_mem_q[reg_id_i]].rs1 = rs1_i; - mem_d[id_mem_q[reg_id_i]].rs2 = rs2_i; - mem_d[id_mem_q[reg_id_i]].rs_valid = rs_valid_i; - mem_d[id_mem_q[reg_id_i]].frm = frm_i; - end - - // Commit - if (commit_i) begin - // Push the commit pointer to the - commit_d = id_mem_q[commit_id_i] + 1'b1; - end - - // Read - if (valid_o && ~empty_o && ready_i) begin - // Pop the head by one - head_d = head_q + 1'b1; - // Decrease usage - usage = usage_d -1'b1; - usage_d = usage; - end - - // Flush - if (flush_i && ~empty_o) begin - // When we flush the buffer we take an id and flush all values that where pushed after that id including the id - tail_d = id_mem_q[commit_id_i]; - // Update usage - usage_cap = id_mem_q[commit_id_i] - head_d; - usage_d = usage_cap; - end - - // Assign output - data_o = mem_d[head_q]; - end - - - always_ff @(posedge clk_i or negedge rst_ni) begin - if(~rst_ni) begin - head_q <= '0; - tail_q <= '0; - commit_q <= '0; - usage_q <= '0; - end else begin - head_q <= head_d; - tail_q <= tail_d; - commit_q <= commit_d; - usage_q <= usage_d; - end - end - - always_ff @(posedge clk_i or negedge rst_ni) begin - if(~rst_ni) begin - mem_q <= '0; - id_mem_q <= '0; - end else if (!gate_clock) begin - mem_q <= mem_d; - id_mem_q <= id_mem_d; - end - end - - // full_write : assert property( + parameter int unsigned ID_WIDTH = 8, + parameter int unsigned DEPTH = 1, // Make sure that there are never more ids stored then the depth of the buffer + parameter type readregflags_t = logic, + parameter type dtype = logic, + // DO NOT OVERWRITE THIS PARAMETER + parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1 + ) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + // State information + output logic full_o, + output logic empty_o, + // Control information + input logic push_i, + input logic commit_i, + input logic register_valid_i, + input logic flush_i, + output logic valid_o, + input logic ready_i, + // Data + input logic [ID_WIDTH-1:0] commit_id_i, + input logic [ID_WIDTH-1:0] reg_id_i, + input logic [ID_WIDTH-1:0] id_i, + input dtype data_i, + // Register information + input logic [riscv::XLEN-1:0] rs1_i, + input logic [riscv::XLEN-1:0] rs2_i, + input readregflags_t rs_valid_i, + input fpnew_pkg::roundmode_e frm_i, + // Instruction information + output dtype data_o + ); + // Clock gating control + logic gate_clock; + // Memory + dtype [DEPTH-1:0] mem_d, mem_q; + logic [2**ID_WIDTH-1:0][ADDR_DEPTH-1:0] id_mem_d, id_mem_q; + // Pointer to indicate head and tail + logic [ADDR_DEPTH-1:0] head_d, head_q; + logic [ADDR_DEPTH-1:0] tail_d, tail_q; + // Pointer to indicate the commitable instructions + logic [ADDR_DEPTH-1:0] commit_d, commit_q; + // Usage indicator + logic [ADDR_DEPTH:0] usage_d, usage_q; + logic [ADDR_DEPTH:0] usage; + logic [ADDR_DEPTH-1:0] usage_cap; + + + // assign full_o = (tail_q+1'b1 == head_q) ? 1'b1 : 1'b0; + // assign empty_o = (tail_q == head_q) ? 1'b1 : 1'b0; + assign full_o = (usage_q == DEPTH[$clog2(DEPTH):0]); + assign empty_o = (usage_q == '0); + + + assign valid_o = (mem_q[head_q].rs_valid != '0 || mem_d[head_q].rs_valid != '0) && !(head_q == commit_q && head_q == commit_d) && !(empty_o); // (mem_q[head_q].rs_valid == mem_q[head_q].register_read) + // (mem_q[head_q].rs_valid != '0 && mem_d[head_q].rs_valid != '0) && + + + // Read and write logic + always_comb begin + // Default assignment + mem_d = mem_q; + id_mem_d = id_mem_q; + head_d = head_q; + tail_d = tail_q; + commit_d = commit_q; + usage_d = usage_q; + usage = '0; + usage_cap = '0; + gate_clock = 1'b1; + + // Write + if (push_i && ~full_o) begin + // Un-gate the clock + gate_clock = 1'b0; + // Write to mem + mem_d[tail_q] = data_i; + // Link the tail id to id_i + id_mem_d[id_i] = tail_q; + // Push the tail by one + tail_d = tail_q + 1'b1; + // Increment usage + usage = usage_q + 1'b1; + usage_d = usage; + end + + // Write Register information + if (register_valid_i) begin + // Un-gate the clock + gate_clock = 1'b0; + // Write to mem + mem_d[id_mem_q[reg_id_i]].rs1 = rs1_i; + mem_d[id_mem_q[reg_id_i]].rs2 = rs2_i; + mem_d[id_mem_q[reg_id_i]].rs_valid = rs_valid_i; + mem_d[id_mem_q[reg_id_i]].frm = frm_i; + end + + // Commit + if (commit_i) begin + // Push the commit pointer to the + commit_d = id_mem_q[commit_id_i] + 1'b1; + end + + // Read + if (valid_o && ~empty_o && ready_i) begin + // Pop the head by one + head_d = head_q + 1'b1; + // Decrease usage + usage = usage_d -1'b1; + usage_d = usage; + end + + // Flush + if (flush_i && ~empty_o) begin + // When we flush the buffer we take an id and flush all values that where pushed after that id including the id + tail_d = id_mem_q[commit_id_i]; + // Update usage + usage_cap = id_mem_q[commit_id_i] - head_d; + usage_d = usage_cap; + end + + // Assign output + data_o = mem_d[head_q]; + end + + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + head_q <= '0; + tail_q <= '0; + commit_q <= '0; + usage_q <= '0; + end else begin + head_q <= head_d; + tail_q <= tail_d; + commit_q <= commit_d; + usage_q <= usage_d; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + mem_q <= '0; + id_mem_q <= '0; + end else if (!gate_clock) begin + mem_q <= mem_d; + id_mem_q <= id_mem_d; + end + end + + // full_write : assert property( // @(posedge clk_i) disable iff (~rst_ni) (full_o |-> ~push_i)) // else $fatal (1, "Trying to push new data although the BUFFER is full."); @@ -167,4 +167,4 @@ module ara_ring_buffer #( // @(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~(valid_o && ready_i))) // else $fatal (1, "Trying to pop data although the BUFFER is empty."); -endmodule : ara_ring_buffer \ No newline at end of file +endmodule : ara_ring_buffer diff --git a/hardware/src/ara_xif_handler.sv b/hardware/src/ara_xif_handler.sv index a912f08c2..1ab034b07 100644 --- a/hardware/src/ara_xif_handler.sv +++ b/hardware/src/ara_xif_handler.sv @@ -7,41 +7,41 @@ // Handler to take care of the XIF signals module ara_xif_handler #( - parameter int unsigned NrLanes = 0, - parameter int unsigned HARTID_WIDTH = ariane_pkg::NR_RGPR_PORTS, - parameter int unsigned ID_WIDTH = ariane_pkg::TRANS_ID_BITS, - parameter type readregflags_t = logic, - parameter type writeregflags_t = logic, - parameter type x_req_t = core_v_xif_pkg::x_req_t, - parameter type x_resp_t = core_v_xif_pkg::x_resp_t, - parameter type x_issue_req_t = core_v_xif_pkg::x_issue_req_t, - parameter type x_issue_resp_t = core_v_xif_pkg::x_issue_resp_t, - parameter type x_result_t = core_v_xif_pkg::x_result_t, - parameter type x_acc_resp_t = core_v_xif_pkg::x_acc_resp_t, - parameter type csr_sync_t = logic, - parameter type instr_pack_t = logic - ) ( - // Clock and Reset - input logic clk_i, - input logic rst_ni, - // XIF - input x_req_t core_v_xif_req_i, - output x_resp_t core_v_xif_resp_o, + parameter int unsigned NrLanes = 0, + parameter int unsigned HARTID_WIDTH = ariane_pkg::NR_RGPR_PORTS, + parameter int unsigned ID_WIDTH = ariane_pkg::TRANS_ID_BITS, + parameter type readregflags_t = logic, + parameter type writeregflags_t = logic, + parameter type x_req_t = logic, + parameter type x_resp_t = logic, + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_result_t = logic, + parameter type x_acc_resp_t = logic, + parameter type csr_sync_t = logic, + parameter type instr_pack_t = logic + ) ( + // Clock and Reset + input logic clk_i, + input logic rst_ni, + // XIF + input x_req_t core_v_xif_req_i, + output x_resp_t core_v_xif_resp_o, // <-> Ara Dispatcher - output instr_pack_t instruction_o, - output logic instruction_valid_o, - input logic instruction_ready_i, - input csr_sync_t csr_sync_i, - input x_resp_t core_v_xif_resp_i, + output instr_pack_t instruction_o, + output logic instruction_valid_o, + input logic instruction_ready_i, + input csr_sync_t csr_sync_i, + input x_resp_t core_v_xif_resp_i, // Temp - input logic ara_idle, + input logic ara_idle, input logic [NrLanes-1:0] vxsat_flag, input logic [NrLanes-1:0][4:0] fflags_ex, input logic [NrLanes-1:0] fflags_ex_valid, - input logic load_complete, - input logic store_complete, - input logic store_pending - ); + input logic load_complete, + input logic store_complete, + input logic store_pending + ); logic csr_stall; logic csr_block; @@ -208,4 +208,4 @@ module ara_xif_handler #( csr_instr_id_q <= csr_instr_id_d; end end -endmodule : ara_xif_handler \ No newline at end of file +endmodule : ara_xif_handler