From 20a1bd3de6b6b2fc4ad7e581528e25a83bb9232a Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Wed, 4 Dec 2024 16:57:12 +0100 Subject: [PATCH] [hardware] Explicitly use fewer bits in vldu --- hardware/src/vlsu/vldu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hardware/src/vlsu/vldu.sv b/hardware/src/vlsu/vldu.sv index b26a6b44e..4171d20c3 100644 --- a/hardware/src/vlsu/vldu.sv +++ b/hardware/src/vlsu/vldu.sv @@ -295,9 +295,9 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #( && !result_queue_full) begin : axi_r_beat_read // Bytes valid in the current R beat // If non-unit strided load, we do not progress within the beat - automatic shortint unsigned lower_byte = beat_lower_byte(axi_addrgen_req_i.addr, + automatic logic [idx_width(AxiDataWidth/8)-1:0] lower_byte = beat_lower_byte(axi_addrgen_req_i.addr, axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, axi_len_q); - automatic shortint unsigned upper_byte = beat_upper_byte(axi_addrgen_req_i.addr, + automatic logic [idx_width(AxiDataWidth/8)-1:0] upper_byte = beat_upper_byte(axi_addrgen_req_i.addr, axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, axi_len_q); // Is there a vector instruction ready to be issued?