diff --git a/Bender.lock b/Bender.lock
index b77ca8a5b..5d416f38f 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -30,7 +30,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 5dfb8935db1bef2e7238b3025baf2d20b473784d
+    revision: 4b4a335dd1e51fec8291102fffe53b79447af1e2
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git
diff --git a/Bender.yml b/Bender.yml
index 09d6bdd44..8a7486ca3 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -10,7 +10,7 @@ package:
 dependencies:
   axi:                { git: "https://github.com/pulp-platform/axi.git",                version: 0.39.1                               }
   common_cells:       { git: "https://github.com/pulp-platform/common_cells.git",       version: 1.22.1                               }
-  cva6:               { git: "https://github.com/pulp-platform/cva6.git",               rev: 5dfb8935db1bef2e7238b3025baf2d20b473784d } # paulsc/v2-chs
+  cva6:               { git: "https://github.com/pulp-platform/cva6.git",               rev: 4b4a335dd1e51fec8291102fffe53b79447af1e2 } # mp/pulp-v2
   tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13                               }
   apb:                { git: "https://github.com/pulp-platform/apb.git",                version: 0.2.4                                }
 
@@ -68,7 +68,7 @@ sources:
     - target: ara_test
       files:
         # Level 1
-        - hardware/tb/mock_uart.sv
+        - hardware/deps/cva6/corev_apu/tb/common/mock_uart.sv
         - hardware/tb/ara_testharness.sv
         # Level 2
         - hardware/tb/ara_tb.sv
diff --git a/hardware/tb/mock_uart.sv b/hardware/tb/mock_uart.sv
deleted file mode 100644
index 6a14904b1..000000000
--- a/hardware/tb/mock_uart.sv
+++ /dev/null
@@ -1,120 +0,0 @@
-// Copyright 2018 ETH Zurich and University of Bologna.
-// Copyright and related rights are licensed under the Solderpad Hardware
-// License, Version 0.51 (the "License"); you may not use this file except in
-// compliance with the License.  You may obtain a copy of the License at
-// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-// or agreed to in writing, software, hardware and materials distributed under
-// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-// CONDITIONS OF ANY KIND, either express or implied. See the License for the
-// specific language governing permissions and limitations under the License.
-//
-// Author: Florian Zaruba, ETH Zurich
-// Date: 28/09/2018
-// Description: Mock replacement for UART in testbench (not synthesiesable!)
-
-module mock_uart (
-    input  logic          clk_i,
-    input  logic          rst_ni,
-    input  logic          penable_i,
-    input  logic          pwrite_i,
-    input  logic [31:0]   paddr_i,
-    input  logic          psel_i,
-    input  logic [31:0]   pwdata_i,
-    output logic [31:0]   prdata_o,
-    output logic          pready_o,
-    output logic          pslverr_o
-);
-    localparam RBR = 0;
-    localparam THR = 0;
-    localparam IER = 1;
-    localparam IIR = 2;
-    localparam FCR = 2;
-    localparam LCR = 3;
-    localparam MCR = 4;
-    localparam LSR = 5;
-    localparam MSR = 6;
-    localparam SCR = 7;
-    localparam DLL = 0;
-    localparam DLM = 1;
-
-    localparam THRE = 5; // transmit holding register empty
-    localparam TEMT = 6; // transmit holding register empty
-
-    byte lcr = 0;
-    byte dlm = 0;
-    byte dll = 0;
-    byte mcr = 0;
-    byte lsr = 0;
-    byte ier = 0;
-    byte msr = 0;
-    byte scr = 0;
-    logic fifo_enabled = 1'b0;
-
-    assign pready_o = 1'b1;
-    assign pslverr_o = 1'b0;
-
-    function void uart_tx(byte ch);
-        $write("%c", ch);
-    endfunction : uart_tx
-
-/* verilator lint_off WIDTHTRUNC */
-/* verilator lint_off WIDTHEXPAND */
-/* verilator lint_off WIDTHCONCAT */
-
-    always_ff @(posedge clk_i or negedge rst_ni) begin
-        if (rst_ni) begin
-            if (psel_i & penable_i & pwrite_i) begin
-                case ((paddr_i >> 'h2) & 'h7)
-                    THR: begin
-                        if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]);
-                        else uart_tx(byte'(pwdata_i[7:0]));
-                    end
-                    IER: begin
-                        if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]);
-                        else ier <= byte'(pwdata_i[7:0] & 'hF);
-                    end
-                    FCR: begin
-                        if (pwdata_i[0]) fifo_enabled <= 1'b1;
-                        else fifo_enabled <= 1'b0;
-                    end
-                    LCR: lcr <= byte'(pwdata_i[7:0]);
-                    MCR: mcr <= byte'(pwdata_i[7:0] & 'h1F);
-                    LSR: lsr <= byte'(pwdata_i[7:0]);
-                    MSR: msr <= byte'(pwdata_i[7:0]);
-                    SCR: scr <= byte'(pwdata_i[7:0]);
-                    default:;
-                endcase
-            end
-        end
-    end
-
-    always_comb begin
-        prdata_o = '0;
-        if (psel_i & penable_i & ~pwrite_i) begin
-            case ((paddr_i >> 'h2) & 'h7)
-                THR: begin
-                    if (lcr & 'h80) prdata_o = {24'b0, dll};
-                end
-                IER: begin
-                    if (lcr & 'h80) prdata_o = {24'b0, dlm};
-                    else prdata_o = {24'b0, ier};
-                end
-                IIR: begin
-                    if (fifo_enabled) prdata_o = {24'b0, 8'hc0};
-                    else prdata_o = {24'b0, 8'b0};
-                end
-                LCR: prdata_o = {24'b0, lcr};
-                MCR: prdata_o = {24'b0, mcr};
-                LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))};
-                MSR: prdata_o = {24'b0, msr};
-                SCR: prdata_o = {24'b0, scr};
-                default:;
-            endcase
-        end
-    end
-
-/* verilator lint_on WIDTHTRUNC */
-/* verilator lint_on WIDTHEXPAND */
-/* verilator lint_on WIDTHCONCAT */
-
-endmodule