From 10c76d9fa89df71cbc1869aa74b833f0f9dc45b5 Mon Sep 17 00:00:00 2001
From: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Date: Fri, 8 Nov 2024 12:13:57 +0100
Subject: [PATCH] [FUNCTIONALITIES] Bump functionalities with segment and whole
 reg load/stores

---
 FUNCTIONALITIES.md | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/FUNCTIONALITIES.md b/FUNCTIONALITIES.md
index 2e26a7903..67c08d9b1 100644
--- a/FUNCTIONALITIES.md
+++ b/FUNCTIONALITIES.md
@@ -15,6 +15,14 @@ This file specifies the functionalities of the RISC-V Vector Specification suppo
 - Vector strided stores: `vsse<eew>`
 - Vector indexed loads: `vluxei<eew>`, `vloxei<eew>`
 - Vector indexed stores: `vsuxei<eew>`, `vsoxei<eew>`
+- Vector unit-strided segment loads: `vlseg<nf>e<eew>.v`
+- Vector unit-strided segment stores: `vsseg<nf>e<eew>.v`
+- Vector non-unit-strided segment loads: `vlsseg<nf>e<eew>.v`
+- Vector non-unit-strided segment stores: `vssseg<nf>e<eew>.v`
+- Vector indexed segment loads: `vluxseg<nf>ei<eew>.v`, `vloxseg<nf>ei<eew>.v`
+- Vector indexed segment stores: `vsuxseg<nf>ei<eew>.v`, `vsoxseg<nf>ei<eew>.v`
+- Vector whole-register loads: `vl<nf>re<eew>.v`
+- Vector whole-register stores: `vs<nf>r.v`
 
 ## Vector Integer Arithmetic Instructions