From 78ed65a1befd4e063e4578a738be0d2b24202cae Mon Sep 17 00:00:00 2001 From: Tim Fischer Date: Wed, 1 Nov 2023 09:43:50 +0100 Subject: [PATCH] chimney: Fix double driven signals --- src/floo_axi_chimney.sv | 4 ++-- src/floo_narrow_wide_chimney.sv | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/floo_axi_chimney.sv b/src/floo_axi_chimney.sv index a05ebc22..a14d3ed1 100644 --- a/src/floo_axi_chimney.sv +++ b/src/floo_axi_chimney.sv @@ -155,7 +155,7 @@ module floo_axi_chimney .rst_ni, .data_i ( axi_in_req_i.aw ), .valid_i ( axi_in_req_i.aw_valid ), - .ready_o ( axi_in_rsp_o.aw_ready ), + .ready_o ( axi_rsp_out.aw_ready ), .data_o ( axi_aw_queue ), .valid_o ( axi_aw_queue_valid_out ), .ready_i ( axi_aw_queue_ready_in ) @@ -168,7 +168,7 @@ module floo_axi_chimney .rst_ni, .data_i ( axi_in_req_i.ar ), .valid_i ( axi_in_req_i.ar_valid ), - .ready_o ( axi_in_rsp_o.ar_ready ), + .ready_o ( axi_rsp_out.ar_ready ), .data_o ( axi_ar_queue ), .valid_o ( axi_ar_queue_valid_out ), .ready_i ( axi_ar_queue_ready_in ) diff --git a/src/floo_narrow_wide_chimney.sv b/src/floo_narrow_wide_chimney.sv index 57e94bf0..c412c863 100644 --- a/src/floo_narrow_wide_chimney.sv +++ b/src/floo_narrow_wide_chimney.sv @@ -212,7 +212,7 @@ module floo_narrow_wide_chimney .rst_ni, .data_i ( axi_narrow_in_req_i.aw ), .valid_i ( axi_narrow_in_req_i.aw_valid ), - .ready_o ( axi_narrow_in_rsp_o.aw_ready ), + .ready_o ( axi_narrow_rsp_out.aw_ready ), .data_o ( axi_narrow_aw_queue ), .valid_o ( axi_narrow_aw_queue_valid_out ), .ready_i ( axi_narrow_aw_queue_ready_in ) @@ -225,7 +225,7 @@ module floo_narrow_wide_chimney .rst_ni, .data_i ( axi_narrow_in_req_i.ar ), .valid_i ( axi_narrow_in_req_i.ar_valid ), - .ready_o ( axi_narrow_in_rsp_o.ar_ready ), + .ready_o ( axi_narrow_rsp_out.ar_ready ), .data_o ( axi_narrow_ar_queue ), .valid_o ( axi_narrow_ar_queue_valid_out ), .ready_i ( axi_narrow_ar_queue_ready_in ) @@ -234,10 +234,10 @@ module floo_narrow_wide_chimney end else begin : gen_ax_no_cuts assign axi_narrow_aw_queue = axi_narrow_in_req_i.aw; assign axi_narrow_aw_queue_valid_out = axi_narrow_in_req_i.aw_valid; - assign axi_narrow_in_rsp_o.aw_ready = axi_narrow_aw_queue_ready_in; + assign axi_narrow_rsp_out.aw_ready = axi_narrow_aw_queue_ready_in; assign axi_narrow_ar_queue = axi_narrow_in_req_i.ar; assign axi_narrow_ar_queue_valid_out = axi_narrow_in_req_i.ar_valid; - assign axi_narrow_in_rsp_o.ar_ready = axi_narrow_ar_queue_ready_in; + assign axi_narrow_rsp_out.ar_ready = axi_narrow_ar_queue_ready_in; end end else begin : gen_narrow_err_slv_port @@ -273,7 +273,7 @@ module floo_narrow_wide_chimney .rst_ni, .data_i ( axi_wide_in_req_i.aw ), .valid_i ( axi_wide_in_req_i.aw_valid ), - .ready_o ( axi_wide_in_rsp_o.aw_ready ), + .ready_o ( axi_wide_rsp_out.aw_ready ), .data_o ( axi_wide_aw_queue ), .valid_o ( axi_wide_aw_queue_valid_out ), .ready_i ( axi_wide_aw_queue_ready_in ) @@ -286,7 +286,7 @@ module floo_narrow_wide_chimney .rst_ni, .data_i ( axi_wide_in_req_i.ar ), .valid_i ( axi_wide_in_req_i.ar_valid ), - .ready_o ( axi_wide_in_rsp_o.ar_ready ), + .ready_o ( axi_wide_rsp_out.ar_ready ), .data_o ( axi_wide_ar_queue ), .valid_o ( axi_wide_ar_queue_valid_out ), .ready_i ( axi_wide_ar_queue_ready_in ) @@ -294,10 +294,10 @@ module floo_narrow_wide_chimney end else begin : gen_ax_no_cuts assign axi_wide_aw_queue = axi_wide_in_req_i.aw; assign axi_wide_aw_queue_valid_out = axi_wide_in_req_i.aw_valid; - assign axi_wide_in_rsp_o.aw_ready = axi_wide_aw_queue_ready_in; + assign axi_wide_rsp_out.aw_ready = axi_wide_aw_queue_ready_in; assign axi_wide_ar_queue = axi_wide_in_req_i.ar; assign axi_wide_ar_queue_valid_out = axi_wide_in_req_i.ar_valid; - assign axi_wide_in_rsp_o.ar_ready = axi_wide_ar_queue_ready_in; + assign axi_wide_rsp_out.ar_ready = axi_wide_ar_queue_ready_in; end end else begin : gen_wide_err_slv_port axi_err_slv #(