diff --git a/hw/floo_axi_chimney.sv b/hw/floo_axi_chimney.sv
index c26e4f54..b04e4591 100644
--- a/hw/floo_axi_chimney.sv
+++ b/hw/floo_axi_chimney.sv
@@ -207,33 +207,6 @@ module floo_axi_chimney #(
       assign axi_rsp_out.ar_ready = axi_ar_queue_ready_in;
     end
 
-    logic aw_out_queue_valid, aw_out_queue_ready;
-    axi_out_aw_chan_t axi_aw_queue_out;
-
-    // Since AW and W are transferred over the same link, it can happen that
-    // a downstream module does not accept the AW until the W is valid.
-    // Therefore, we need to add a spill register for the AW channel.
-    spill_register #(
-      .T (axi_out_aw_chan_t)
-    ) i_aw_out_queue (
-      .clk_i    ( clk_i                     ),
-      .rst_ni   ( rst_ni                    ),
-      .valid_i  ( meta_buf_req_out.aw_valid ),
-      .ready_o  ( aw_out_queue_ready        ),
-      .data_i   ( meta_buf_req_out.aw       ),
-      .valid_o  ( aw_out_queue_valid        ),
-      .ready_i  ( axi_out_rsp_i.aw_ready    ),
-      .data_o   ( axi_aw_queue_out          )
-    );
-
-    always_comb begin
-      axi_out_req_o = meta_buf_req_out;
-      axi_out_req_o.aw_valid = aw_out_queue_valid;
-      axi_out_req_o.aw = axi_aw_queue_out;
-      meta_buf_rsp_in = axi_out_rsp_i;
-      meta_buf_rsp_in.aw_ready = aw_out_queue_ready;
-    end
-
   end else begin : gen_err_slv_port
     axi_err_slv #(
       .AxiIdWidth ( AxiCfg.InIdWidth  ),
@@ -289,6 +262,34 @@ module floo_axi_chimney #(
     assign floo_rsp_o.ready = floo_rsp_out_ready;
   end
 
+
+  logic aw_out_queue_valid, aw_out_queue_ready;
+  axi_out_aw_chan_t axi_aw_queue_out;
+
+  // Since AW and W are transferred over the same link, it can happen that
+  // a downstream module does not accept the AW until the W is valid.
+  // Therefore, we need to add a spill register for the AW channel.
+  spill_register #(
+    .T (axi_out_aw_chan_t)
+  ) i_aw_out_queue (
+    .clk_i    ( clk_i                     ),
+    .rst_ni   ( rst_ni                    ),
+    .valid_i  ( meta_buf_req_out.aw_valid ),
+    .ready_o  ( aw_out_queue_ready        ),
+    .data_i   ( meta_buf_req_out.aw       ),
+    .valid_o  ( aw_out_queue_valid        ),
+    .ready_i  ( axi_out_rsp_i.aw_ready    ),
+    .data_o   ( axi_aw_queue_out          )
+  );
+
+  always_comb begin
+    axi_out_req_o = meta_buf_req_out;
+    axi_out_req_o.aw_valid = aw_out_queue_valid;
+    axi_out_req_o.aw = axi_aw_queue_out;
+    meta_buf_rsp_in = axi_out_rsp_i;
+    meta_buf_rsp_in.aw_ready = aw_out_queue_ready;
+  end
+
   ///////////////////////
   //  Reorder Buffers  //
   ///////////////////////
diff --git a/hw/floo_nw_chimney.sv b/hw/floo_nw_chimney.sv
index 750dc6ef..e1084c3e 100644
--- a/hw/floo_nw_chimney.sv
+++ b/hw/floo_nw_chimney.sv
@@ -271,33 +271,6 @@ module floo_nw_chimney #(
       assign axi_narrow_rsp_out.ar_ready = axi_narrow_ar_queue_ready_in;
     end
 
-    logic narrow_aw_out_queue_valid, narrow_aw_out_queue_ready;
-    axi_narrow_out_aw_chan_t axi_narrow_aw_queue_out;
-
-    // Since AW and W are transferred over the same link, it can happen that
-    // a downstream module does not accept the AW until the W is valid.
-    // Therefore, we need to add a spill register for the AW channel.
-    spill_register #(
-      .T (axi_narrow_out_aw_chan_t)
-    ) i_aw_narrow_out_queue (
-      .clk_i    ( clk_i                                 ),
-      .rst_ni   ( rst_ni                                ),
-      .valid_i  ( axi_narrow_meta_buf_req_out.aw_valid  ),
-      .ready_o  ( narrow_aw_out_queue_ready             ),
-      .data_i   ( axi_narrow_meta_buf_req_out.aw        ),
-      .valid_o  ( narrow_aw_out_queue_valid             ),
-      .ready_i  ( axi_narrow_out_rsp_i.aw_ready         ),
-      .data_o   ( axi_narrow_aw_queue_out               )
-    );
-
-    always_comb begin
-      axi_narrow_out_req_o = axi_narrow_meta_buf_req_out;
-      axi_narrow_out_req_o.aw_valid = narrow_aw_out_queue_valid;
-      axi_narrow_out_req_o.aw = axi_narrow_aw_queue_out;
-      axi_narrow_meta_buf_rsp_in = axi_narrow_out_rsp_i;
-      axi_narrow_meta_buf_rsp_in.aw_ready = narrow_aw_out_queue_ready;
-    end
-
   end else begin : gen_narrow_err_slv_port
     axi_err_slv #(
       .AxiIdWidth ( AxiCfgN.InIdWidth   ),
@@ -358,32 +331,6 @@ module floo_nw_chimney #(
       assign axi_wide_rsp_out.ar_ready = axi_wide_ar_queue_ready_in;
     end
 
-    logic wide_aw_out_queue_valid, wide_aw_out_queue_ready;
-    axi_wide_out_aw_chan_t axi_wide_aw_queue_out;
-
-    // Since AW and W are transferred over the same link, it can happen that
-    // a downstream module does not accept the AW until the W is valid.
-    // Therefore, we need to add a spill register for the AW channel.
-    spill_register #(
-      .T (axi_wide_out_aw_chan_t)
-    ) i_aw_out_queue (
-      .clk_i    ( clk_i                               ),
-      .rst_ni   ( rst_ni                              ),
-      .valid_i  ( axi_wide_meta_buf_req_out.aw_valid  ),
-      .ready_o  ( wide_aw_out_queue_ready             ),
-      .data_i   ( axi_wide_meta_buf_req_out.aw        ),
-      .valid_o  ( wide_aw_out_queue_valid             ),
-      .ready_i  ( axi_wide_out_rsp_i.aw_ready         ),
-      .data_o   ( axi_wide_aw_queue_out               )
-    );
-
-    always_comb begin
-      axi_wide_out_req_o = axi_wide_meta_buf_req_out;
-      axi_wide_out_req_o.aw_valid = wide_aw_out_queue_valid;
-      axi_wide_out_req_o.aw = axi_wide_aw_queue_out;
-      axi_wide_meta_buf_rsp_in = axi_wide_out_rsp_i;
-      axi_wide_meta_buf_rsp_in.aw_ready = wide_aw_out_queue_ready;
-    end
   end else begin : gen_wide_err_slv_port
     axi_err_slv #(
       .AxiIdWidth ( AxiCfgW.InIdWidth ),
@@ -456,6 +403,53 @@ module floo_nw_chimney #(
     assign floo_wide_o.ready = floo_wide_out_ready;
   end
 
+  logic narrow_aw_out_queue_valid, narrow_aw_out_queue_ready;
+  logic wide_aw_out_queue_valid, wide_aw_out_queue_ready;
+  axi_narrow_out_aw_chan_t axi_narrow_aw_queue_out;
+  axi_wide_out_aw_chan_t axi_wide_aw_queue_out;
+
+  // Since AW and W are transferred over the same link, it can happen that
+  // a downstream module does not accept the AW until the W is valid.
+  // Therefore, we need to add a spill register for the AW channel.
+  spill_register #(
+    .T (axi_narrow_out_aw_chan_t)
+  ) i_aw_narrow_out_queue (
+    .clk_i    ( clk_i                                 ),
+    .rst_ni   ( rst_ni                                ),
+    .valid_i  ( axi_narrow_meta_buf_req_out.aw_valid  ),
+    .ready_o  ( narrow_aw_out_queue_ready             ),
+    .data_i   ( axi_narrow_meta_buf_req_out.aw        ),
+    .valid_o  ( narrow_aw_out_queue_valid             ),
+    .ready_i  ( axi_narrow_out_rsp_i.aw_ready         ),
+    .data_o   ( axi_narrow_aw_queue_out               )
+  );
+
+  spill_register #(
+    .T (axi_wide_out_aw_chan_t)
+  ) i_aw_out_queue (
+    .clk_i    ( clk_i                               ),
+    .rst_ni   ( rst_ni                              ),
+    .valid_i  ( axi_wide_meta_buf_req_out.aw_valid  ),
+    .ready_o  ( wide_aw_out_queue_ready             ),
+    .data_i   ( axi_wide_meta_buf_req_out.aw        ),
+    .valid_o  ( wide_aw_out_queue_valid             ),
+    .ready_i  ( axi_wide_out_rsp_i.aw_ready         ),
+    .data_o   ( axi_wide_aw_queue_out               )
+  );
+
+  always_comb begin
+    axi_narrow_out_req_o = axi_narrow_meta_buf_req_out;
+    axi_narrow_out_req_o.aw_valid = narrow_aw_out_queue_valid;
+    axi_narrow_out_req_o.aw = axi_narrow_aw_queue_out;
+    axi_narrow_meta_buf_rsp_in = axi_narrow_out_rsp_i;
+    axi_narrow_meta_buf_rsp_in.aw_ready = narrow_aw_out_queue_ready;
+    axi_wide_out_req_o = axi_wide_meta_buf_req_out;
+    axi_wide_out_req_o.aw_valid = wide_aw_out_queue_valid;
+    axi_wide_out_req_o.aw = axi_wide_aw_queue_out;
+    axi_wide_meta_buf_rsp_in = axi_wide_out_rsp_i;
+    axi_wide_meta_buf_rsp_in.aw_ready = wide_aw_out_queue_ready;
+  end
+
   ///////////////////////
   //  Reorder Buffers  //
   ///////////////////////